From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,T_MIXED_ES, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E1B3C65BAE for ; Thu, 13 Dec 2018 12:59:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F325220645 for ; Thu, 13 Dec 2018 12:59:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F325220645 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729278AbeLMM7f (ORCPT ); Thu, 13 Dec 2018 07:59:35 -0500 Received: from metis.ext.pengutronix.de ([85.220.165.71]:57419 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728803AbeLMM7e (ORCPT ); Thu, 13 Dec 2018 07:59:34 -0500 Received: from lupine.hi.pengutronix.de ([2001:67c:670:100:3ad5:47ff:feaf:1a17] helo=lupine) by metis.ext.pengutronix.de with esmtp (Exim 4.89) (envelope-from ) id 1gXQaN-0000m9-97; Thu, 13 Dec 2018 13:59:27 +0100 Message-ID: <1544705964.5886.1.camel@pengutronix.de> Subject: Re: [PATCH v5 02/12] gpu: ipu-csi: Swap fields according to input/output field types From: Philipp Zabel To: Steve Longerbeam , linux-media@vger.kernel.org Cc: Mauro Carvalho Chehab , Greg Kroah-Hartman , Bartlomiej Zolnierkiewicz , "open list:DRM DRIVERS FOR FREESCALE IMX" , open list , "open list:STAGING SUBSYSTEM" , "open list:FRAMEBUFFER LAYER" Date: Thu, 13 Dec 2018 13:59:24 +0100 In-Reply-To: <20181017000027.23696-3-slongerbeam@gmail.com> References: <20181017000027.23696-1-slongerbeam@gmail.com> <20181017000027.23696-3-slongerbeam@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.6-1+deb9u1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:100:3ad5:47ff:feaf:1a17 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Steve, On Tue, 2018-10-16 at 17:00 -0700, Steve Longerbeam wrote: > The function ipu_csi_init_interface() was inverting the F-bit for > NTSC case, in the CCIR_CODE_1/2 registers. The result being that > for NTSC bottom-top field order, the CSI would swap fields and > capture in top-bottom order. > > Instead, base field swap on the field order of the input to the CSI, > and the field order of the requested output. If the input/output > fields are sequential but different, swap fields, otherwise do > not swap. This requires passing both the input and output mbus > frame formats to ipu_csi_init_interface(). > > Move this code to a new private function ipu_csi_set_bt_interlaced_codes() > that programs the CCIR_CODE_1/2 registers for interlaced BT.656 (and > possibly interlaced BT.1120 in the future). > > When detecting input video standard from the input frame width/height, > make sure to double height if input field type is alternate, since > in that case input height only includes lines for one field. > > Signed-off-by: Steve Longerbeam > --- > Changes since v4: > - Cleaned up some convoluted code in ipu_csi_init_interface(), suggested > by Philipp Zabel. > - Fixed a regression in csi_setup(), caught by Philipp. > --- > drivers/gpu/ipu-v3/ipu-csi.c | 119 +++++++++++++++------- > drivers/staging/media/imx/imx-media-csi.c | 17 +--- > include/video/imx-ipu-v3.h | 3 +- > 3 files changed, 88 insertions(+), 51 deletions(-) > > diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c > index aa0e30a2ba18..4a15e513fa05 100644 > --- a/drivers/gpu/ipu-v3/ipu-csi.c > +++ b/drivers/gpu/ipu-v3/ipu-csi.c > @@ -325,6 +325,15 @@ static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code, > return 0; > } > > +/* translate alternate field mode based on given standard */ > +static inline enum v4l2_field > +ipu_csi_translate_field(enum v4l2_field field, v4l2_std_id std) > +{ > + return (field != V4L2_FIELD_ALTERNATE) ? field : > + ((std & V4L2_STD_525_60) ? > + V4L2_FIELD_SEQ_BT : V4L2_FIELD_SEQ_TB); > +} > + > /* > * Fill a CSI bus config struct from mbus_config and mbus_framefmt. > */ > @@ -374,22 +383,75 @@ static int fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg, > return 0; > } > > +static int ipu_csi_set_bt_interlaced_codes(struct ipu_csi *csi, > + struct v4l2_mbus_framefmt *infmt, > + struct v4l2_mbus_framefmt *outfmt, infmt and outfmt parameters could be const. > + v4l2_std_id std) > +{ > + enum v4l2_field infield, outfield; > + bool swap_fields; > + > + /* get translated field type of input and output */ > + infield = ipu_csi_translate_field(infmt->field, std); > + outfield = ipu_csi_translate_field(outfmt->field, std); > + > + /* > + * Write the H-V-F codes the CSI will match against the > + * incoming data for start/end of active and blanking > + * field intervals. If input and output field types are > + * sequential but not the same (one is SEQ_BT and the other > + * is SEQ_TB), swap the F-bit so that the CSI will capture > + * field 1 lines before field 0 lines. > + */ > + swap_fields = (V4L2_FIELD_IS_SEQUENTIAL(infield) && > + V4L2_FIELD_IS_SEQUENTIAL(outfield) && > + infield != outfield); > + > + if (!swap_fields) { > + /* > + * Field0BlankEnd = 110, Field0BlankStart = 010 > + * Field0ActiveEnd = 100, Field0ActiveStart = 000 > + * Field1BlankEnd = 111, Field1BlankStart = 011 > + * Field1ActiveEnd = 101, Field1ActiveStart = 001 > + */ > + ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN, > + CSI_CCIR_CODE_1); > + ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2); > + } else { > + dev_dbg(csi->ipu->dev, "capture field swap\n"); > + > + /* same as above but with F-bit inverted */ > + ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN, > + CSI_CCIR_CODE_1); > + ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2); > + } > + > + ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3); > + > + return 0; > +} > + > + > int ipu_csi_init_interface(struct ipu_csi *csi, > struct v4l2_mbus_config *mbus_cfg, > - struct v4l2_mbus_framefmt *mbus_fmt) > + struct v4l2_mbus_framefmt *infmt, > + struct v4l2_mbus_framefmt *outfmt) > { > struct ipu_csi_bus_config cfg; > unsigned long flags; > u32 width, height, data = 0; > + v4l2_std_id std; > int ret; > > - ret = fill_csi_bus_cfg(&cfg, mbus_cfg, mbus_fmt); > + ret = fill_csi_bus_cfg(&cfg, mbus_cfg, infmt); > if (ret < 0) > return ret; > > /* set default sensor frame width and height */ > - width = mbus_fmt->width; > - height = mbus_fmt->height; > + width = infmt->width; > + height = infmt->height; > + if (infmt->field == V4L2_FIELD_ALTERNATE) > + height *= 2; > > /* Set the CSI_SENS_CONF register remaining fields */ > data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT | > @@ -416,42 +478,22 @@ int ipu_csi_init_interface(struct ipu_csi *csi, > ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3); > break; > case IPU_CSI_CLK_MODE_CCIR656_INTERLACED: > - if (mbus_fmt->width == 720 && mbus_fmt->height == 576) { > - /* > - * PAL case > - * > - * Field0BlankEnd = 0x6, Field0BlankStart = 0x2, > - * Field0ActiveEnd = 0x4, Field0ActiveStart = 0 > - * Field1BlankEnd = 0x7, Field1BlankStart = 0x3, > - * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1 > - */ > - height = 625; /* framelines for PAL */ > - > - ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN, > - CSI_CCIR_CODE_1); > - ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2); > - ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3); > - } else if (mbus_fmt->width == 720 && mbus_fmt->height == 480) { > - /* > - * NTSC case > - * > - * Field0BlankEnd = 0x7, Field0BlankStart = 0x3, > - * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1 > - * Field1BlankEnd = 0x6, Field1BlankStart = 0x2, > - * Field1ActiveEnd = 0x4, Field1ActiveStart = 0 > - */ > - height = 525; /* framelines for NTSC */ > - > - ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN, > - CSI_CCIR_CODE_1); > - ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2); > - ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3); > + if (width == 720 && height == 480) { > + std = V4L2_STD_NTSC; > + height = 525; > + } else if (width == 720 && height == 576) { > + std = V4L2_STD_PAL; > + height = 625; > } else { > dev_err(csi->ipu->dev, > - "Unsupported CCIR656 interlaced video mode\n"); > - spin_unlock_irqrestore(&csi->lock, flags); > - return -EINVAL; > + "Unsupported interlaced video mode\n"); > + ret = -EINVAL; > + goto out_unlock; > } > + > + ret = ipu_csi_set_bt_interlaced_codes(csi, infmt, outfmt, std); > + if (ret) > + goto out_unlock; > break; > case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR: > case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR: > @@ -476,9 +518,10 @@ int ipu_csi_init_interface(struct ipu_csi *csi, > dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n", > ipu_csi_read(csi, CSI_ACT_FRM_SIZE)); > > +out_unlock: > spin_unlock_irqrestore(&csi->lock, flags); > > - return 0; > + return ret; > } > EXPORT_SYMBOL_GPL(ipu_csi_init_interface); > > diff --git a/drivers/staging/media/imx/imx-media-csi.c b/drivers/staging/media/imx/imx-media-csi.c > index 4223f8d418ae..7ecbd4d76d09 100644 > --- a/drivers/staging/media/imx/imx-media-csi.c > +++ b/drivers/staging/media/imx/imx-media-csi.c > @@ -663,15 +663,14 @@ static void csi_idmac_stop(struct csi_priv *priv) > /* Update the CSI whole sensor and active windows */ > static int csi_setup(struct csi_priv *priv) > { > - struct v4l2_mbus_framefmt *infmt, *outfmt; > + struct v4l2_mbus_framefmt infmt, outfmt; > const struct imx_media_pixfmt *incc; > struct v4l2_mbus_config mbus_cfg; > - struct v4l2_mbus_framefmt if_fmt; > struct v4l2_rect crop; > > - infmt = &priv->format_mbus[CSI_SINK_PAD]; > + infmt = priv->format_mbus[CSI_SINK_PAD]; Maybe still call this if_fmt, or maybe csi_fmt, to indicate this is not just the userspace visible input format as determined by the pad, but the modified format we set the interface to? Not a strong preference, though. > incc = priv->cc[CSI_SINK_PAD]; > - outfmt = &priv->format_mbus[priv->active_output_pad]; > + outfmt = priv->format_mbus[priv->active_output_pad]; Copying the output format onto the stack seems unnecessary to me. > > /* compose mbus_config from the upstream endpoint */ > mbus_cfg.type = priv->upstream_ep.bus_type; > @@ -679,12 +678,6 @@ static int csi_setup(struct csi_priv *priv) > priv->upstream_ep.bus.parallel.flags : > priv->upstream_ep.bus.mipi_csi2.flags; > > - /* > - * we need to pass input frame to CSI interface, but > - * with translated field type from output format > - */ > - if_fmt = *infmt; > - if_fmt.field = outfmt->field; > crop = priv->crop; > > /* > @@ -692,7 +685,7 @@ static int csi_setup(struct csi_priv *priv) > * generic/bayer data > */ > if (is_parallel_bus(&priv->upstream_ep) && incc->cycles) { > - if_fmt.width *= incc->cycles; > + infmt.width *= incc->cycles; > crop.width *= incc->cycles; > } > > @@ -702,7 +695,7 @@ static int csi_setup(struct csi_priv *priv) > priv->crop.width == 2 * priv->compose.width, > priv->crop.height == 2 * priv->compose.height); > > - ipu_csi_init_interface(priv->csi, &mbus_cfg, &if_fmt); > + ipu_csi_init_interface(priv->csi, &mbus_cfg, &infmt, &outfmt); We can just pass the &priv->format_mbus[priv->active_output_pad] here, or keep using struct v4l2_mbus_framefmt *outfmt as a shorthand. > > ipu_csi_set_dest(priv->csi, priv->dest); > > diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h > index abbad94e14a1..f44a35192313 100644 > --- a/include/video/imx-ipu-v3.h > +++ b/include/video/imx-ipu-v3.h > @@ -352,7 +352,8 @@ int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan, > struct ipu_csi; > int ipu_csi_init_interface(struct ipu_csi *csi, > struct v4l2_mbus_config *mbus_cfg, > - struct v4l2_mbus_framefmt *mbus_fmt); > + struct v4l2_mbus_framefmt *infmt, > + struct v4l2_mbus_framefmt *outfmt); > bool ipu_csi_is_interlaced(struct ipu_csi *csi); > void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w); > void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w); Either way, Reviewed-by: Philipp Zabel regards Philipp From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philipp Zabel Date: Thu, 13 Dec 2018 12:59:24 +0000 Subject: Re: [PATCH v5 02/12] gpu: ipu-csi: Swap fields according to input/output field types Message-Id: <1544705964.5886.1.camel@pengutronix.de> List-Id: References: <20181017000027.23696-1-slongerbeam@gmail.com> <20181017000027.23696-3-slongerbeam@gmail.com> In-Reply-To: <20181017000027.23696-3-slongerbeam@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Steve Longerbeam , linux-media@vger.kernel.org Cc: "open list:STAGING SUBSYSTEM" , "open list:FRAMEBUFFER LAYER" , Bartlomiej Zolnierkiewicz , Greg Kroah-Hartman , open list , "open list:DRM DRIVERS FOR FREESCALE IMX" , Mauro Carvalho Chehab Hi Steve, On Tue, 2018-10-16 at 17:00 -0700, Steve Longerbeam wrote: > The function ipu_csi_init_interface() was inverting the F-bit for > NTSC case, in the CCIR_CODE_1/2 registers. The result being that > for NTSC bottom-top field order, the CSI would swap fields and > capture in top-bottom order. > > Instead, base field swap on the field order of the input to the CSI, > and the field order of the requested output. If the input/output > fields are sequential but different, swap fields, otherwise do > not swap. This requires passing both the input and output mbus > frame formats to ipu_csi_init_interface(). > > Move this code to a new private function ipu_csi_set_bt_interlaced_codes() > that programs the CCIR_CODE_1/2 registers for interlaced BT.656 (and > possibly interlaced BT.1120 in the future). > > When detecting input video standard from the input frame width/height, > make sure to double height if input field type is alternate, since > in that case input height only includes lines for one field. > > Signed-off-by: Steve Longerbeam > --- > Changes since v4: > - Cleaned up some convoluted code in ipu_csi_init_interface(), suggested > by Philipp Zabel. > - Fixed a regression in csi_setup(), caught by Philipp. > --- > drivers/gpu/ipu-v3/ipu-csi.c | 119 +++++++++++++++------- > drivers/staging/media/imx/imx-media-csi.c | 17 +--- > include/video/imx-ipu-v3.h | 3 +- > 3 files changed, 88 insertions(+), 51 deletions(-) > > diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c > index aa0e30a2ba18..4a15e513fa05 100644 > --- a/drivers/gpu/ipu-v3/ipu-csi.c > +++ b/drivers/gpu/ipu-v3/ipu-csi.c > @@ -325,6 +325,15 @@ static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code, > return 0; > } > > +/* translate alternate field mode based on given standard */ > +static inline enum v4l2_field > +ipu_csi_translate_field(enum v4l2_field field, v4l2_std_id std) > +{ > + return (field != V4L2_FIELD_ALTERNATE) ? field : > + ((std & V4L2_STD_525_60) ? > + V4L2_FIELD_SEQ_BT : V4L2_FIELD_SEQ_TB); > +} > + > /* > * Fill a CSI bus config struct from mbus_config and mbus_framefmt. > */ > @@ -374,22 +383,75 @@ static int fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg, > return 0; > } > > +static int ipu_csi_set_bt_interlaced_codes(struct ipu_csi *csi, > + struct v4l2_mbus_framefmt *infmt, > + struct v4l2_mbus_framefmt *outfmt, infmt and outfmt parameters could be const. > + v4l2_std_id std) > +{ > + enum v4l2_field infield, outfield; > + bool swap_fields; > + > + /* get translated field type of input and output */ > + infield = ipu_csi_translate_field(infmt->field, std); > + outfield = ipu_csi_translate_field(outfmt->field, std); > + > + /* > + * Write the H-V-F codes the CSI will match against the > + * incoming data for start/end of active and blanking > + * field intervals. If input and output field types are > + * sequential but not the same (one is SEQ_BT and the other > + * is SEQ_TB), swap the F-bit so that the CSI will capture > + * field 1 lines before field 0 lines. > + */ > + swap_fields = (V4L2_FIELD_IS_SEQUENTIAL(infield) && > + V4L2_FIELD_IS_SEQUENTIAL(outfield) && > + infield != outfield); > + > + if (!swap_fields) { > + /* > + * Field0BlankEnd = 110, Field0BlankStart = 010 > + * Field0ActiveEnd = 100, Field0ActiveStart = 000 > + * Field1BlankEnd = 111, Field1BlankStart = 011 > + * Field1ActiveEnd = 101, Field1ActiveStart = 001 > + */ > + ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN, > + CSI_CCIR_CODE_1); > + ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2); > + } else { > + dev_dbg(csi->ipu->dev, "capture field swap\n"); > + > + /* same as above but with F-bit inverted */ > + ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN, > + CSI_CCIR_CODE_1); > + ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2); > + } > + > + ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3); > + > + return 0; > +} > + > + > int ipu_csi_init_interface(struct ipu_csi *csi, > struct v4l2_mbus_config *mbus_cfg, > - struct v4l2_mbus_framefmt *mbus_fmt) > + struct v4l2_mbus_framefmt *infmt, > + struct v4l2_mbus_framefmt *outfmt) > { > struct ipu_csi_bus_config cfg; > unsigned long flags; > u32 width, height, data = 0; > + v4l2_std_id std; > int ret; > > - ret = fill_csi_bus_cfg(&cfg, mbus_cfg, mbus_fmt); > + ret = fill_csi_bus_cfg(&cfg, mbus_cfg, infmt); > if (ret < 0) > return ret; > > /* set default sensor frame width and height */ > - width = mbus_fmt->width; > - height = mbus_fmt->height; > + width = infmt->width; > + height = infmt->height; > + if (infmt->field = V4L2_FIELD_ALTERNATE) > + height *= 2; > > /* Set the CSI_SENS_CONF register remaining fields */ > data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT | > @@ -416,42 +478,22 @@ int ipu_csi_init_interface(struct ipu_csi *csi, > ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3); > break; > case IPU_CSI_CLK_MODE_CCIR656_INTERLACED: > - if (mbus_fmt->width = 720 && mbus_fmt->height = 576) { > - /* > - * PAL case > - * > - * Field0BlankEnd = 0x6, Field0BlankStart = 0x2, > - * Field0ActiveEnd = 0x4, Field0ActiveStart = 0 > - * Field1BlankEnd = 0x7, Field1BlankStart = 0x3, > - * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1 > - */ > - height = 625; /* framelines for PAL */ > - > - ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN, > - CSI_CCIR_CODE_1); > - ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2); > - ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3); > - } else if (mbus_fmt->width = 720 && mbus_fmt->height = 480) { > - /* > - * NTSC case > - * > - * Field0BlankEnd = 0x7, Field0BlankStart = 0x3, > - * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1 > - * Field1BlankEnd = 0x6, Field1BlankStart = 0x2, > - * Field1ActiveEnd = 0x4, Field1ActiveStart = 0 > - */ > - height = 525; /* framelines for NTSC */ > - > - ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN, > - CSI_CCIR_CODE_1); > - ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2); > - ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3); > + if (width = 720 && height = 480) { > + std = V4L2_STD_NTSC; > + height = 525; > + } else if (width = 720 && height = 576) { > + std = V4L2_STD_PAL; > + height = 625; > } else { > dev_err(csi->ipu->dev, > - "Unsupported CCIR656 interlaced video mode\n"); > - spin_unlock_irqrestore(&csi->lock, flags); > - return -EINVAL; > + "Unsupported interlaced video mode\n"); > + ret = -EINVAL; > + goto out_unlock; > } > + > + ret = ipu_csi_set_bt_interlaced_codes(csi, infmt, outfmt, std); > + if (ret) > + goto out_unlock; > break; > case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR: > case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR: > @@ -476,9 +518,10 @@ int ipu_csi_init_interface(struct ipu_csi *csi, > dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n", > ipu_csi_read(csi, CSI_ACT_FRM_SIZE)); > > +out_unlock: > spin_unlock_irqrestore(&csi->lock, flags); > > - return 0; > + return ret; > } > EXPORT_SYMBOL_GPL(ipu_csi_init_interface); > > diff --git a/drivers/staging/media/imx/imx-media-csi.c b/drivers/staging/media/imx/imx-media-csi.c > index 4223f8d418ae..7ecbd4d76d09 100644 > --- a/drivers/staging/media/imx/imx-media-csi.c > +++ b/drivers/staging/media/imx/imx-media-csi.c > @@ -663,15 +663,14 @@ static void csi_idmac_stop(struct csi_priv *priv) > /* Update the CSI whole sensor and active windows */ > static int csi_setup(struct csi_priv *priv) > { > - struct v4l2_mbus_framefmt *infmt, *outfmt; > + struct v4l2_mbus_framefmt infmt, outfmt; > const struct imx_media_pixfmt *incc; > struct v4l2_mbus_config mbus_cfg; > - struct v4l2_mbus_framefmt if_fmt; > struct v4l2_rect crop; > > - infmt = &priv->format_mbus[CSI_SINK_PAD]; > + infmt = priv->format_mbus[CSI_SINK_PAD]; Maybe still call this if_fmt, or maybe csi_fmt, to indicate this is not just the userspace visible input format as determined by the pad, but the modified format we set the interface to? Not a strong preference, though. > incc = priv->cc[CSI_SINK_PAD]; > - outfmt = &priv->format_mbus[priv->active_output_pad]; > + outfmt = priv->format_mbus[priv->active_output_pad]; Copying the output format onto the stack seems unnecessary to me. > > /* compose mbus_config from the upstream endpoint */ > mbus_cfg.type = priv->upstream_ep.bus_type; > @@ -679,12 +678,6 @@ static int csi_setup(struct csi_priv *priv) > priv->upstream_ep.bus.parallel.flags : > priv->upstream_ep.bus.mipi_csi2.flags; > > - /* > - * we need to pass input frame to CSI interface, but > - * with translated field type from output format > - */ > - if_fmt = *infmt; > - if_fmt.field = outfmt->field; > crop = priv->crop; > > /* > @@ -692,7 +685,7 @@ static int csi_setup(struct csi_priv *priv) > * generic/bayer data > */ > if (is_parallel_bus(&priv->upstream_ep) && incc->cycles) { > - if_fmt.width *= incc->cycles; > + infmt.width *= incc->cycles; > crop.width *= incc->cycles; > } > > @@ -702,7 +695,7 @@ static int csi_setup(struct csi_priv *priv) > priv->crop.width = 2 * priv->compose.width, > priv->crop.height = 2 * priv->compose.height); > > - ipu_csi_init_interface(priv->csi, &mbus_cfg, &if_fmt); > + ipu_csi_init_interface(priv->csi, &mbus_cfg, &infmt, &outfmt); We can just pass the &priv->format_mbus[priv->active_output_pad] here, or keep using struct v4l2_mbus_framefmt *outfmt as a shorthand. > > ipu_csi_set_dest(priv->csi, priv->dest); > > diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h > index abbad94e14a1..f44a35192313 100644 > --- a/include/video/imx-ipu-v3.h > +++ b/include/video/imx-ipu-v3.h > @@ -352,7 +352,8 @@ int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan, > struct ipu_csi; > int ipu_csi_init_interface(struct ipu_csi *csi, > struct v4l2_mbus_config *mbus_cfg, > - struct v4l2_mbus_framefmt *mbus_fmt); > + struct v4l2_mbus_framefmt *infmt, > + struct v4l2_mbus_framefmt *outfmt); > bool ipu_csi_is_interlaced(struct ipu_csi *csi); > void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w); > void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w); Either way, Reviewed-by: Philipp Zabel regards Philipp From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philipp Zabel Subject: Re: [PATCH v5 02/12] gpu: ipu-csi: Swap fields according to input/output field types Date: Thu, 13 Dec 2018 13:59:24 +0100 Message-ID: <1544705964.5886.1.camel@pengutronix.de> References: <20181017000027.23696-1-slongerbeam@gmail.com> <20181017000027.23696-3-slongerbeam@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0C5F86E92B for ; Thu, 13 Dec 2018 12:59:33 +0000 (UTC) In-Reply-To: <20181017000027.23696-3-slongerbeam@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Steve Longerbeam , linux-media@vger.kernel.org Cc: "open list:STAGING SUBSYSTEM" , "open list:FRAMEBUFFER LAYER" , Bartlomiej Zolnierkiewicz , Greg Kroah-Hartman , open list , "open list:DRM DRIVERS FOR FREESCALE IMX" , Mauro Carvalho Chehab List-Id: dri-devel@lists.freedesktop.org SGkgU3RldmUsCgpPbiBUdWUsIDIwMTgtMTAtMTYgYXQgMTc6MDAgLTA3MDAsIFN0ZXZlIExvbmdl cmJlYW0gd3JvdGU6Cj4gVGhlIGZ1bmN0aW9uIGlwdV9jc2lfaW5pdF9pbnRlcmZhY2UoKSB3YXMg aW52ZXJ0aW5nIHRoZSBGLWJpdCBmb3IKPiBOVFNDIGNhc2UsIGluIHRoZSBDQ0lSX0NPREVfMS8y IHJlZ2lzdGVycy4gVGhlIHJlc3VsdCBiZWluZyB0aGF0Cj4gZm9yIE5UU0MgYm90dG9tLXRvcCBm aWVsZCBvcmRlciwgdGhlIENTSSB3b3VsZCBzd2FwIGZpZWxkcyBhbmQKPiBjYXB0dXJlIGluIHRv cC1ib3R0b20gb3JkZXIuCj4gCj4gSW5zdGVhZCwgYmFzZSBmaWVsZCBzd2FwIG9uIHRoZSBmaWVs ZCBvcmRlciBvZiB0aGUgaW5wdXQgdG8gdGhlIENTSSwKPiBhbmQgdGhlIGZpZWxkIG9yZGVyIG9m IHRoZSByZXF1ZXN0ZWQgb3V0cHV0LiBJZiB0aGUgaW5wdXQvb3V0cHV0Cj4gZmllbGRzIGFyZSBz ZXF1ZW50aWFsIGJ1dCBkaWZmZXJlbnQsIHN3YXAgZmllbGRzLCBvdGhlcndpc2UgZG8KPiBub3Qg c3dhcC4gVGhpcyByZXF1aXJlcyBwYXNzaW5nIGJvdGggdGhlIGlucHV0IGFuZCBvdXRwdXQgbWJ1 cwo+IGZyYW1lIGZvcm1hdHMgdG8gaXB1X2NzaV9pbml0X2ludGVyZmFjZSgpLgo+IAo+IE1vdmUg dGhpcyBjb2RlIHRvIGEgbmV3IHByaXZhdGUgZnVuY3Rpb24gaXB1X2NzaV9zZXRfYnRfaW50ZXJs YWNlZF9jb2RlcygpCj4gdGhhdCBwcm9ncmFtcyB0aGUgQ0NJUl9DT0RFXzEvMiByZWdpc3RlcnMg Zm9yIGludGVybGFjZWQgQlQuNjU2IChhbmQKPiBwb3NzaWJseSBpbnRlcmxhY2VkIEJULjExMjAg aW4gdGhlIGZ1dHVyZSkuCj4gCj4gV2hlbiBkZXRlY3RpbmcgaW5wdXQgdmlkZW8gc3RhbmRhcmQg ZnJvbSB0aGUgaW5wdXQgZnJhbWUgd2lkdGgvaGVpZ2h0LAo+IG1ha2Ugc3VyZSB0byBkb3VibGUg aGVpZ2h0IGlmIGlucHV0IGZpZWxkIHR5cGUgaXMgYWx0ZXJuYXRlLCBzaW5jZQo+IGluIHRoYXQg Y2FzZSBpbnB1dCBoZWlnaHQgb25seSBpbmNsdWRlcyBsaW5lcyBmb3Igb25lIGZpZWxkLgo+IAo+ IFNpZ25lZC1vZmYtYnk6IFN0ZXZlIExvbmdlcmJlYW0gPHNsb25nZXJiZWFtQGdtYWlsLmNvbT4K PiAtLS0KPiBDaGFuZ2VzIHNpbmNlIHY0Ogo+IC0gQ2xlYW5lZCB1cCBzb21lIGNvbnZvbHV0ZWQg Y29kZSBpbiBpcHVfY3NpX2luaXRfaW50ZXJmYWNlKCksIHN1Z2dlc3RlZAo+ICAgYnkgUGhpbGlw cCBaYWJlbC4KPiAtIEZpeGVkIGEgcmVncmVzc2lvbiBpbiBjc2lfc2V0dXAoKSwgY2F1Z2h0IGJ5 IFBoaWxpcHAuCj4gLS0tCj4gIGRyaXZlcnMvZ3B1L2lwdS12My9pcHUtY3NpLmMgICAgICAgICAg ICAgIHwgMTE5ICsrKysrKysrKysrKysrKy0tLS0tLS0KPiAgZHJpdmVycy9zdGFnaW5nL21lZGlh L2lteC9pbXgtbWVkaWEtY3NpLmMgfCAgMTcgKy0tLQo+ICBpbmNsdWRlL3ZpZGVvL2lteC1pcHUt djMuaCAgICAgICAgICAgICAgICB8ICAgMyArLQo+ICAzIGZpbGVzIGNoYW5nZWQsIDg4IGluc2Vy dGlvbnMoKyksIDUxIGRlbGV0aW9ucygtKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9p cHUtdjMvaXB1LWNzaS5jIGIvZHJpdmVycy9ncHUvaXB1LXYzL2lwdS1jc2kuYwo+IGluZGV4IGFh MGUzMGEyYmExOC4uNGExNWU1MTNmYTA1IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2lwdS12 My9pcHUtY3NpLmMKPiArKysgYi9kcml2ZXJzL2dwdS9pcHUtdjMvaXB1LWNzaS5jCj4gQEAgLTMy NSw2ICszMjUsMTUgQEAgc3RhdGljIGludCBtYnVzX2NvZGVfdG9fYnVzX2NmZyhzdHJ1Y3QgaXB1 X2NzaV9idXNfY29uZmlnICpjZmcsIHUzMiBtYnVzX2NvZGUsCj4gIAlyZXR1cm4gMDsKPiAgfQo+ ICAKPiArLyogdHJhbnNsYXRlIGFsdGVybmF0ZSBmaWVsZCBtb2RlIGJhc2VkIG9uIGdpdmVuIHN0 YW5kYXJkICovCj4gK3N0YXRpYyBpbmxpbmUgZW51bSB2NGwyX2ZpZWxkCj4gK2lwdV9jc2lfdHJh bnNsYXRlX2ZpZWxkKGVudW0gdjRsMl9maWVsZCBmaWVsZCwgdjRsMl9zdGRfaWQgc3RkKQo+ICt7 Cj4gKwlyZXR1cm4gKGZpZWxkICE9IFY0TDJfRklFTERfQUxURVJOQVRFKSA/IGZpZWxkIDoKPiAr CQkoKHN0ZCAmIFY0TDJfU1REXzUyNV82MCkgPwo+ICsJCSBWNEwyX0ZJRUxEX1NFUV9CVCA6IFY0 TDJfRklFTERfU0VRX1RCKTsKPiArfQo+ICsKPiAgLyoKPiAgICogRmlsbCBhIENTSSBidXMgY29u ZmlnIHN0cnVjdCBmcm9tIG1idXNfY29uZmlnIGFuZCBtYnVzX2ZyYW1lZm10Lgo+ICAgKi8KPiBA QCAtMzc0LDIyICszODMsNzUgQEAgc3RhdGljIGludCBmaWxsX2NzaV9idXNfY2ZnKHN0cnVjdCBp cHVfY3NpX2J1c19jb25maWcgKmNzaWNmZywKPiAgCXJldHVybiAwOwo+ICB9Cj4gIAo+ICtzdGF0 aWMgaW50IGlwdV9jc2lfc2V0X2J0X2ludGVybGFjZWRfY29kZXMoc3RydWN0IGlwdV9jc2kgKmNz aSwKPiArCQkJCQkgICBzdHJ1Y3QgdjRsMl9tYnVzX2ZyYW1lZm10ICppbmZtdCwKPiArCQkJCQkg ICBzdHJ1Y3QgdjRsMl9tYnVzX2ZyYW1lZm10ICpvdXRmbXQsCgppbmZtdCBhbmQgb3V0Zm10IHBh cmFtZXRlcnMgY291bGQgYmUgY29uc3QuCgo+ICsJCQkJCSAgIHY0bDJfc3RkX2lkIHN0ZCkKPiAr ewo+ICsJZW51bSB2NGwyX2ZpZWxkIGluZmllbGQsIG91dGZpZWxkOwo+ICsJYm9vbCBzd2FwX2Zp ZWxkczsKPiArCj4gKwkvKiBnZXQgdHJhbnNsYXRlZCBmaWVsZCB0eXBlIG9mIGlucHV0IGFuZCBv dXRwdXQgKi8KPiArCWluZmllbGQgPSBpcHVfY3NpX3RyYW5zbGF0ZV9maWVsZChpbmZtdC0+Zmll bGQsIHN0ZCk7Cj4gKwlvdXRmaWVsZCA9IGlwdV9jc2lfdHJhbnNsYXRlX2ZpZWxkKG91dGZtdC0+ ZmllbGQsIHN0ZCk7Cj4gKwo+ICsJLyoKPiArCSAqIFdyaXRlIHRoZSBILVYtRiBjb2RlcyB0aGUg Q1NJIHdpbGwgbWF0Y2ggYWdhaW5zdCB0aGUKPiArCSAqIGluY29taW5nIGRhdGEgZm9yIHN0YXJ0 L2VuZCBvZiBhY3RpdmUgYW5kIGJsYW5raW5nCj4gKwkgKiBmaWVsZCBpbnRlcnZhbHMuIElmIGlu cHV0IGFuZCBvdXRwdXQgZmllbGQgdHlwZXMgYXJlCj4gKwkgKiBzZXF1ZW50aWFsIGJ1dCBub3Qg dGhlIHNhbWUgKG9uZSBpcyBTRVFfQlQgYW5kIHRoZSBvdGhlcgo+ICsJICogaXMgU0VRX1RCKSwg c3dhcCB0aGUgRi1iaXQgc28gdGhhdCB0aGUgQ1NJIHdpbGwgY2FwdHVyZQo+ICsJICogZmllbGQg MSBsaW5lcyBiZWZvcmUgZmllbGQgMCBsaW5lcy4KPiArCSAqLwo+ICsJc3dhcF9maWVsZHMgPSAo VjRMMl9GSUVMRF9JU19TRVFVRU5USUFMKGluZmllbGQpICYmCj4gKwkJICAgICAgIFY0TDJfRklF TERfSVNfU0VRVUVOVElBTChvdXRmaWVsZCkgJiYKPiArCQkgICAgICAgaW5maWVsZCAhPSBvdXRm aWVsZCk7Cj4gKwo+ICsJaWYgKCFzd2FwX2ZpZWxkcykgewo+ICsJCS8qCj4gKwkJICogRmllbGQw QmxhbmtFbmQgID0gMTEwLCBGaWVsZDBCbGFua1N0YXJ0ICA9IDAxMAo+ICsJCSAqIEZpZWxkMEFj dGl2ZUVuZCA9IDEwMCwgRmllbGQwQWN0aXZlU3RhcnQgPSAwMDAKPiArCQkgKiBGaWVsZDFCbGFu a0VuZCAgPSAxMTEsIEZpZWxkMUJsYW5rU3RhcnQgID0gMDExCj4gKwkJICogRmllbGQxQWN0aXZl RW5kID0gMTAxLCBGaWVsZDFBY3RpdmVTdGFydCA9IDAwMQo+ICsJCSAqLwo+ICsJCWlwdV9jc2lf d3JpdGUoY3NpLCAweDQwNTk2IHwgQ1NJX0NDSVJfRVJSX0RFVF9FTiwKPiArCQkJICAgICAgQ1NJ X0NDSVJfQ09ERV8xKTsKPiArCQlpcHVfY3NpX3dyaXRlKGNzaSwgMHhEMDdERiwgQ1NJX0NDSVJf Q09ERV8yKTsKPiArCX0gZWxzZSB7Cj4gKwkJZGV2X2RiZyhjc2ktPmlwdS0+ZGV2LCAiY2FwdHVy ZSBmaWVsZCBzd2FwXG4iKTsKPiArCj4gKwkJLyogc2FtZSBhcyBhYm92ZSBidXQgd2l0aCBGLWJp dCBpbnZlcnRlZCAqLwo+ICsJCWlwdV9jc2lfd3JpdGUoY3NpLCAweEQwN0RGIHwgQ1NJX0NDSVJf RVJSX0RFVF9FTiwKPiArCQkJICAgICAgQ1NJX0NDSVJfQ09ERV8xKTsKPiArCQlpcHVfY3NpX3dy aXRlKGNzaSwgMHg0MDU5NiwgQ1NJX0NDSVJfQ09ERV8yKTsKPiArCX0KPiArCj4gKwlpcHVfY3Np X3dyaXRlKGNzaSwgMHhGRjAwMDAsIENTSV9DQ0lSX0NPREVfMyk7Cj4gKwo+ICsJcmV0dXJuIDA7 Cj4gK30KPiArCj4gKwo+ICBpbnQgaXB1X2NzaV9pbml0X2ludGVyZmFjZShzdHJ1Y3QgaXB1X2Nz aSAqY3NpLAo+ICAJCQkgICBzdHJ1Y3QgdjRsMl9tYnVzX2NvbmZpZyAqbWJ1c19jZmcsCj4gLQkJ CSAgIHN0cnVjdCB2NGwyX21idXNfZnJhbWVmbXQgKm1idXNfZm10KQo+ICsJCQkgICBzdHJ1Y3Qg djRsMl9tYnVzX2ZyYW1lZm10ICppbmZtdCwKPiArCQkJICAgc3RydWN0IHY0bDJfbWJ1c19mcmFt ZWZtdCAqb3V0Zm10KQo+ICB7Cj4gIAlzdHJ1Y3QgaXB1X2NzaV9idXNfY29uZmlnIGNmZzsKPiAg CXVuc2lnbmVkIGxvbmcgZmxhZ3M7Cj4gIAl1MzIgd2lkdGgsIGhlaWdodCwgZGF0YSA9IDA7Cj4g Kwl2NGwyX3N0ZF9pZCBzdGQ7Cj4gIAlpbnQgcmV0Owo+ICAKPiAtCXJldCA9IGZpbGxfY3NpX2J1 c19jZmcoJmNmZywgbWJ1c19jZmcsIG1idXNfZm10KTsKPiArCXJldCA9IGZpbGxfY3NpX2J1c19j ZmcoJmNmZywgbWJ1c19jZmcsIGluZm10KTsKPiAgCWlmIChyZXQgPCAwKQo+ICAJCXJldHVybiBy ZXQ7Cj4gIAo+ICAJLyogc2V0IGRlZmF1bHQgc2Vuc29yIGZyYW1lIHdpZHRoIGFuZCBoZWlnaHQg Ki8KPiAtCXdpZHRoID0gbWJ1c19mbXQtPndpZHRoOwo+IC0JaGVpZ2h0ID0gbWJ1c19mbXQtPmhl aWdodDsKPiArCXdpZHRoID0gaW5mbXQtPndpZHRoOwo+ICsJaGVpZ2h0ID0gaW5mbXQtPmhlaWdo dDsKPiArCWlmIChpbmZtdC0+ZmllbGQgPT0gVjRMMl9GSUVMRF9BTFRFUk5BVEUpCj4gKwkJaGVp Z2h0ICo9IDI7Cj4gIAo+ICAJLyogU2V0IHRoZSBDU0lfU0VOU19DT05GIHJlZ2lzdGVyIHJlbWFp bmluZyBmaWVsZHMgKi8KPiAgCWRhdGEgfD0gY2ZnLmRhdGFfd2lkdGggPDwgQ1NJX1NFTlNfQ09O Rl9EQVRBX1dJRFRIX1NISUZUIHwKPiBAQCAtNDE2LDQyICs0NzgsMjIgQEAgaW50IGlwdV9jc2lf aW5pdF9pbnRlcmZhY2Uoc3RydWN0IGlwdV9jc2kgKmNzaSwKPiAgCQlpcHVfY3NpX3dyaXRlKGNz aSwgMHhGRjAwMDAsIENTSV9DQ0lSX0NPREVfMyk7Cj4gIAkJYnJlYWs7Cj4gIAljYXNlIElQVV9D U0lfQ0xLX01PREVfQ0NJUjY1Nl9JTlRFUkxBQ0VEOgo+IC0JCWlmIChtYnVzX2ZtdC0+d2lkdGgg PT0gNzIwICYmIG1idXNfZm10LT5oZWlnaHQgPT0gNTc2KSB7Cj4gLQkJCS8qCj4gLQkJCSAqIFBB TCBjYXNlCj4gLQkJCSAqCj4gLQkJCSAqIEZpZWxkMEJsYW5rRW5kID0gMHg2LCBGaWVsZDBCbGFu a1N0YXJ0ID0gMHgyLAo+IC0JCQkgKiBGaWVsZDBBY3RpdmVFbmQgPSAweDQsIEZpZWxkMEFjdGl2 ZVN0YXJ0ID0gMAo+IC0JCQkgKiBGaWVsZDFCbGFua0VuZCA9IDB4NywgRmllbGQxQmxhbmtTdGFy dCA9IDB4MywKPiAtCQkJICogRmllbGQxQWN0aXZlRW5kID0gMHg1LCBGaWVsZDFBY3RpdmVTdGFy dCA9IDB4MQo+IC0JCQkgKi8KPiAtCQkJaGVpZ2h0ID0gNjI1OyAvKiBmcmFtZWxpbmVzIGZvciBQ QUwgKi8KPiAtCj4gLQkJCWlwdV9jc2lfd3JpdGUoY3NpLCAweDQwNTk2IHwgQ1NJX0NDSVJfRVJS X0RFVF9FTiwKPiAtCQkJCQkgIENTSV9DQ0lSX0NPREVfMSk7Cj4gLQkJCWlwdV9jc2lfd3JpdGUo Y3NpLCAweEQwN0RGLCBDU0lfQ0NJUl9DT0RFXzIpOwo+IC0JCQlpcHVfY3NpX3dyaXRlKGNzaSwg MHhGRjAwMDAsIENTSV9DQ0lSX0NPREVfMyk7Cj4gLQkJfSBlbHNlIGlmIChtYnVzX2ZtdC0+d2lk dGggPT0gNzIwICYmIG1idXNfZm10LT5oZWlnaHQgPT0gNDgwKSB7Cj4gLQkJCS8qCj4gLQkJCSAq IE5UU0MgY2FzZQo+IC0JCQkgKgo+IC0JCQkgKiBGaWVsZDBCbGFua0VuZCA9IDB4NywgRmllbGQw QmxhbmtTdGFydCA9IDB4MywKPiAtCQkJICogRmllbGQwQWN0aXZlRW5kID0gMHg1LCBGaWVsZDBB Y3RpdmVTdGFydCA9IDB4MQo+IC0JCQkgKiBGaWVsZDFCbGFua0VuZCA9IDB4NiwgRmllbGQxQmxh bmtTdGFydCA9IDB4MiwKPiAtCQkJICogRmllbGQxQWN0aXZlRW5kID0gMHg0LCBGaWVsZDFBY3Rp dmVTdGFydCA9IDAKPiAtCQkJICovCj4gLQkJCWhlaWdodCA9IDUyNTsgLyogZnJhbWVsaW5lcyBm b3IgTlRTQyAqLwo+IC0KPiAtCQkJaXB1X2NzaV93cml0ZShjc2ksIDB4RDA3REYgfCBDU0lfQ0NJ Ul9FUlJfREVUX0VOLAo+IC0JCQkJCSAgQ1NJX0NDSVJfQ09ERV8xKTsKPiAtCQkJaXB1X2NzaV93 cml0ZShjc2ksIDB4NDA1OTYsIENTSV9DQ0lSX0NPREVfMik7Cj4gLQkJCWlwdV9jc2lfd3JpdGUo Y3NpLCAweEZGMDAwMCwgQ1NJX0NDSVJfQ09ERV8zKTsKPiArCQlpZiAod2lkdGggPT0gNzIwICYm IGhlaWdodCA9PSA0ODApIHsKPiArCQkJc3RkID0gVjRMMl9TVERfTlRTQzsKPiArCQkJaGVpZ2h0 ID0gNTI1Owo+ICsJCX0gZWxzZSBpZiAod2lkdGggPT0gNzIwICYmIGhlaWdodCA9PSA1NzYpIHsK PiArCQkJc3RkID0gVjRMMl9TVERfUEFMOwo+ICsJCQloZWlnaHQgPSA2MjU7Cj4gIAkJfSBlbHNl IHsKPiAgCQkJZGV2X2Vycihjc2ktPmlwdS0+ZGV2LAo+IC0JCQkJIlVuc3VwcG9ydGVkIENDSVI2 NTYgaW50ZXJsYWNlZCB2aWRlbyBtb2RlXG4iKTsKPiAtCQkJc3Bpbl91bmxvY2tfaXJxcmVzdG9y ZSgmY3NpLT5sb2NrLCBmbGFncyk7Cj4gLQkJCXJldHVybiAtRUlOVkFMOwo+ICsJCQkJIlVuc3Vw cG9ydGVkIGludGVybGFjZWQgdmlkZW8gbW9kZVxuIik7Cj4gKwkJCXJldCA9IC1FSU5WQUw7Cj4g KwkJCWdvdG8gb3V0X3VubG9jazsKPiAgCQl9Cj4gKwo+ICsJCXJldCA9IGlwdV9jc2lfc2V0X2J0 X2ludGVybGFjZWRfY29kZXMoY3NpLCBpbmZtdCwgb3V0Zm10LCBzdGQpOwo+ICsJCWlmIChyZXQp Cj4gKwkJCWdvdG8gb3V0X3VubG9jazsKPiAgCQlicmVhazsKPiAgCWNhc2UgSVBVX0NTSV9DTEtf TU9ERV9DQ0lSMTEyMF9QUk9HUkVTU0lWRV9ERFI6Cj4gIAljYXNlIElQVV9DU0lfQ0xLX01PREVf Q0NJUjExMjBfUFJPR1JFU1NJVkVfU0RSOgo+IEBAIC00NzYsOSArNTE4LDEwIEBAIGludCBpcHVf Y3NpX2luaXRfaW50ZXJmYWNlKHN0cnVjdCBpcHVfY3NpICpjc2ksCj4gIAlkZXZfZGJnKGNzaS0+ aXB1LT5kZXYsICJDU0lfQUNUX0ZSTV9TSVpFID0gMHglMDhYXG4iLAo+ICAJCWlwdV9jc2lfcmVh ZChjc2ksIENTSV9BQ1RfRlJNX1NJWkUpKTsKPiAgCj4gK291dF91bmxvY2s6Cj4gIAlzcGluX3Vu bG9ja19pcnFyZXN0b3JlKCZjc2ktPmxvY2ssIGZsYWdzKTsKPiAgCj4gLQlyZXR1cm4gMDsKPiAr CXJldHVybiByZXQ7Cj4gIH0KPiAgRVhQT1JUX1NZTUJPTF9HUEwoaXB1X2NzaV9pbml0X2ludGVy ZmFjZSk7Cj4gIAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3N0YWdpbmcvbWVkaWEvaW14L2lteC1t ZWRpYS1jc2kuYyBiL2RyaXZlcnMvc3RhZ2luZy9tZWRpYS9pbXgvaW14LW1lZGlhLWNzaS5jCj4g aW5kZXggNDIyM2Y4ZDQxOGFlLi43ZWNiZDRkNzZkMDkgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9z dGFnaW5nL21lZGlhL2lteC9pbXgtbWVkaWEtY3NpLmMKPiArKysgYi9kcml2ZXJzL3N0YWdpbmcv bWVkaWEvaW14L2lteC1tZWRpYS1jc2kuYwo+IEBAIC02NjMsMTUgKzY2MywxNCBAQCBzdGF0aWMg dm9pZCBjc2lfaWRtYWNfc3RvcChzdHJ1Y3QgY3NpX3ByaXYgKnByaXYpCj4gIC8qIFVwZGF0ZSB0 aGUgQ1NJIHdob2xlIHNlbnNvciBhbmQgYWN0aXZlIHdpbmRvd3MgKi8KPiAgc3RhdGljIGludCBj c2lfc2V0dXAoc3RydWN0IGNzaV9wcml2ICpwcml2KQo+ICB7Cj4gLQlzdHJ1Y3QgdjRsMl9tYnVz X2ZyYW1lZm10ICppbmZtdCwgKm91dGZtdDsKPiArCXN0cnVjdCB2NGwyX21idXNfZnJhbWVmbXQg aW5mbXQsIG91dGZtdDsKPiAgCWNvbnN0IHN0cnVjdCBpbXhfbWVkaWFfcGl4Zm10ICppbmNjOwo+ ICAJc3RydWN0IHY0bDJfbWJ1c19jb25maWcgbWJ1c19jZmc7Cj4gLQlzdHJ1Y3QgdjRsMl9tYnVz X2ZyYW1lZm10IGlmX2ZtdDsKPiAgCXN0cnVjdCB2NGwyX3JlY3QgY3JvcDsKPiAgCj4gLQlpbmZt dCA9ICZwcml2LT5mb3JtYXRfbWJ1c1tDU0lfU0lOS19QQURdOwo+ICsJaW5mbXQgPSBwcml2LT5m b3JtYXRfbWJ1c1tDU0lfU0lOS19QQURdOwoKTWF5YmUgc3RpbGwgY2FsbCB0aGlzIGlmX2ZtdCwg b3IgbWF5YmUgY3NpX2ZtdCwgdG8gaW5kaWNhdGUgdGhpcyBpcyBub3QKanVzdCB0aGUgdXNlcnNw YWNlIHZpc2libGUgaW5wdXQgZm9ybWF0IGFzIGRldGVybWluZWQgYnkgdGhlIHBhZCwgYnV0CnRo ZSBtb2RpZmllZCBmb3JtYXQgd2Ugc2V0IHRoZSBpbnRlcmZhY2UgdG8/IE5vdCBhIHN0cm9uZyBw cmVmZXJlbmNlLAp0aG91Z2guCgo+ICAJaW5jYyA9IHByaXYtPmNjW0NTSV9TSU5LX1BBRF07Cj4g LQlvdXRmbXQgPSAmcHJpdi0+Zm9ybWF0X21idXNbcHJpdi0+YWN0aXZlX291dHB1dF9wYWRdOwo+ ICsJb3V0Zm10ID0gcHJpdi0+Zm9ybWF0X21idXNbcHJpdi0+YWN0aXZlX291dHB1dF9wYWRdOwoK Q29weWluZyB0aGUgb3V0cHV0IGZvcm1hdCBvbnRvIHRoZSBzdGFjayBzZWVtcyB1bm5lY2Vzc2Fy eSB0byBtZS4KCj4gIAo+ICAJLyogY29tcG9zZSBtYnVzX2NvbmZpZyBmcm9tIHRoZSB1cHN0cmVh bSBlbmRwb2ludCAqLwo+ICAJbWJ1c19jZmcudHlwZSA9IHByaXYtPnVwc3RyZWFtX2VwLmJ1c190 eXBlOwo+IEBAIC02NzksMTIgKzY3OCw2IEBAIHN0YXRpYyBpbnQgY3NpX3NldHVwKHN0cnVjdCBj c2lfcHJpdiAqcHJpdikKPiAgCQlwcml2LT51cHN0cmVhbV9lcC5idXMucGFyYWxsZWwuZmxhZ3Mg Ogo+ICAJCXByaXYtPnVwc3RyZWFtX2VwLmJ1cy5taXBpX2NzaTIuZmxhZ3M7Cj4gIAo+IC0JLyoK PiAtCSAqIHdlIG5lZWQgdG8gcGFzcyBpbnB1dCBmcmFtZSB0byBDU0kgaW50ZXJmYWNlLCBidXQK PiAtCSAqIHdpdGggdHJhbnNsYXRlZCBmaWVsZCB0eXBlIGZyb20gb3V0cHV0IGZvcm1hdAo+IC0J ICovCj4gLQlpZl9mbXQgPSAqaW5mbXQ7Cj4gLQlpZl9mbXQuZmllbGQgPSBvdXRmbXQtPmZpZWxk Owo+ICAJY3JvcCA9IHByaXYtPmNyb3A7Cj4gIAo+ICAJLyoKPiBAQCAtNjkyLDcgKzY4NSw3IEBA IHN0YXRpYyBpbnQgY3NpX3NldHVwKHN0cnVjdCBjc2lfcHJpdiAqcHJpdikKPiAgCSAqIGdlbmVy aWMvYmF5ZXIgZGF0YQo+ICAJICovCj4gIAlpZiAoaXNfcGFyYWxsZWxfYnVzKCZwcml2LT51cHN0 cmVhbV9lcCkgJiYgaW5jYy0+Y3ljbGVzKSB7Cj4gLQkJaWZfZm10LndpZHRoICo9IGluY2MtPmN5 Y2xlczsKPiArCQlpbmZtdC53aWR0aCAqPSBpbmNjLT5jeWNsZXM7Cj4gIAkJY3JvcC53aWR0aCAq PSBpbmNjLT5jeWNsZXM7Cj4gIAl9Cj4gIAo+IEBAIC03MDIsNyArNjk1LDcgQEAgc3RhdGljIGlu dCBjc2lfc2V0dXAoc3RydWN0IGNzaV9wcml2ICpwcml2KQo+ICAJCQkgICAgIHByaXYtPmNyb3Au d2lkdGggPT0gMiAqIHByaXYtPmNvbXBvc2Uud2lkdGgsCj4gIAkJCSAgICAgcHJpdi0+Y3JvcC5o ZWlnaHQgPT0gMiAqIHByaXYtPmNvbXBvc2UuaGVpZ2h0KTsKPiAgCj4gLQlpcHVfY3NpX2luaXRf aW50ZXJmYWNlKHByaXYtPmNzaSwgJm1idXNfY2ZnLCAmaWZfZm10KTsKPiArCWlwdV9jc2lfaW5p dF9pbnRlcmZhY2UocHJpdi0+Y3NpLCAmbWJ1c19jZmcsICZpbmZtdCwgJm91dGZtdCk7CgpXZSBj YW4ganVzdCBwYXNzIHRoZSAmcHJpdi0+Zm9ybWF0X21idXNbcHJpdi0+YWN0aXZlX291dHB1dF9w YWRdIGhlcmUsCm9yIGtlZXAgdXNpbmcgc3RydWN0IHY0bDJfbWJ1c19mcmFtZWZtdCAqb3V0Zm10 IGFzIGEgc2hvcnRoYW5kLgoKPiAgCj4gIAlpcHVfY3NpX3NldF9kZXN0KHByaXYtPmNzaSwgcHJp di0+ZGVzdCk7Cj4gIAo+IGRpZmYgLS1naXQgYS9pbmNsdWRlL3ZpZGVvL2lteC1pcHUtdjMuaCBi L2luY2x1ZGUvdmlkZW8vaW14LWlwdS12My5oCj4gaW5kZXggYWJiYWQ5NGUxNGExLi5mNDRhMzUx OTIzMTMgMTAwNjQ0Cj4gLS0tIGEvaW5jbHVkZS92aWRlby9pbXgtaXB1LXYzLmgKPiArKysgYi9p bmNsdWRlL3ZpZGVvL2lteC1pcHUtdjMuaAo+IEBAIC0zNTIsNyArMzUyLDggQEAgaW50IGlwdV9w cmdfY2hhbm5lbF9jb25maWd1cmUoc3RydWN0IGlwdXYzX2NoYW5uZWwgKmlwdV9jaGFuLAo+ICBz dHJ1Y3QgaXB1X2NzaTsKPiAgaW50IGlwdV9jc2lfaW5pdF9pbnRlcmZhY2Uoc3RydWN0IGlwdV9j c2kgKmNzaSwKPiAgCQkJICAgc3RydWN0IHY0bDJfbWJ1c19jb25maWcgKm1idXNfY2ZnLAo+IC0J CQkgICBzdHJ1Y3QgdjRsMl9tYnVzX2ZyYW1lZm10ICptYnVzX2ZtdCk7Cj4gKwkJCSAgIHN0cnVj dCB2NGwyX21idXNfZnJhbWVmbXQgKmluZm10LAo+ICsJCQkgICBzdHJ1Y3QgdjRsMl9tYnVzX2Zy YW1lZm10ICpvdXRmbXQpOwo+ICBib29sIGlwdV9jc2lfaXNfaW50ZXJsYWNlZChzdHJ1Y3QgaXB1 X2NzaSAqY3NpKTsKPiAgdm9pZCBpcHVfY3NpX2dldF93aW5kb3coc3RydWN0IGlwdV9jc2kgKmNz aSwgc3RydWN0IHY0bDJfcmVjdCAqdyk7Cj4gIHZvaWQgaXB1X2NzaV9zZXRfd2luZG93KHN0cnVj dCBpcHVfY3NpICpjc2ksIHN0cnVjdCB2NGwyX3JlY3QgKncpOwoKRWl0aGVyIHdheSwKUmV2aWV3 ZWQtYnk6IFBoaWxpcHAgWmFiZWwgPHAuemFiZWxAcGVuZ3V0cm9uaXguZGU+CgpyZWdhcmRzClBo aWxpcHAKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJp LWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBz Oi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg==