From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:45506) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkXV7-0003Y9-8a for qemu-devel@nongnu.org; Fri, 18 Jan 2019 12:00:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gkXV5-00075V-3q for qemu-devel@nongnu.org; Fri, 18 Jan 2019 12:00:13 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:52923 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gkXV3-0006qh-2E for qemu-devel@nongnu.org; Fri, 18 Jan 2019 12:00:10 -0500 From: Aleksandar Markovic Date: Fri, 18 Jan 2019 17:59:37 +0100 Message-Id: <1547830785-7079-5-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1547830785-7079-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1547830785-7079-1-git-send-email-aleksandar.markovic@rt-rk.com> Subject: [Qemu-devel] [PULL v2 04/12] target/mips: Add fields for SAARI and SAAR CP0 registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com From: Yongbok Kim Add fields for SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 10 ++++++++-- target/mips/machine.c | 6 ++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index b095422..1c2c682 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -164,8 +164,8 @@ typedef struct mips_def_t mips_def_t; * 3 BadInstrX * 4 GuestCtl1 GuestCtl0Ext * 5 GuestCtl2 - * 6 GuestCtl3 - * 7 + * 6 SAARI GuestCtl3 + * 7 SAAR * * * Register 12 Register 13 Register 14 Register 15 @@ -546,6 +546,12 @@ struct CPUMIPSState { * CP0 Register 9 */ int32_t CP0_Count; + uint32_t CP0_SAARI; +#define CP0SAARI_TARGET 0 /* 5..0 */ + uint64_t CP0_SAAR[2]; +#define CP0SAAR_BASE 12 /* 43..12 */ +#define CP0SAAR_SIZE 1 /* 5..1 */ +#define CP0SAAR_EN 0 /* * CP0 Register 10 */ diff --git a/target/mips/machine.c b/target/mips/machine.c index 704e9c0..111d7c3 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = { const VMStateDescription vmstate_mips_cpu = { .name = "cpu", - .version_id = 15, - .minimum_version_id = 15, + .version_id = 16, + .minimum_version_id = 16, .post_load = cpu_post_load, .fields = (VMStateField[]) { /* Active TC */ @@ -274,6 +274,8 @@ const VMStateDescription vmstate_mips_cpu = { VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU), + VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU), + VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2), VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU), VMSTATE_INT32(env.CP0_Status, MIPSCPU), -- 2.7.4