From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-eopbgr150089.outbound.protection.outlook.com ([40.107.15.89]:5199 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726281AbfAVKR6 (ORCPT ); Tue, 22 Jan 2019 05:17:58 -0500 From: Jacky Bai Subject: [PATCH v2 2/2] pinctrl: freescale: Add imx8mm pinctrl driver support Date: Tue, 22 Jan 2019 10:17:19 +0000 Message-ID: <1548152509-25300-2-git-send-email-ping.bai@nxp.com> References: <1548152509-25300-1-git-send-email-ping.bai@nxp.com> In-Reply-To: <1548152509-25300-1-git-send-email-ping.bai@nxp.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org To: Aisheng Dong , "festevam@gmail.com" , "shawnguo@kernel.org" , "linus.walleij@linaro.org" , "robh+dt@kernel.org" Cc: "linux-gpio@vger.kernel.org" , "devicetree@vger.kernel.org" , dl-linux-imx List-ID: From: Bai Ping Add the pinctrl driver support for i.MX8MM. Signed-off-by: Bai Ping Acked-by: Aisheng Dong --- change v1->v2: - remove unnecessary header file include. --- drivers/pinctrl/freescale/Kconfig | 7 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imx8mm.c | 348 +++++++++++++++++++++++++= ++++ 3 files changed, 356 insertions(+) create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8mm.c diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/= Kconfig index 72b869d..05963a3 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -122,6 +122,13 @@ config PINCTRL_IMX7ULP help Say Y here to enable the imx7ulp pinctrl driver =20 +config PINCTRL_IMX8MM + bool "IMX8MM pinctrl driver" + depends on ARCH_MXC && ARM64 + select PINCTRL_IMX + help + Say Y here to enable the imx8mm pinctrl driver + config PINCTRL_IMX8MQ bool "IMX8MQ pinctrl driver" depends on ARCH_MXC && ARM64 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale= /Makefile index 6ee398a..d64dc5d 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_IMX6SX) +=3D pinctrl-imx6sx.o obj-$(CONFIG_PINCTRL_IMX6UL) +=3D pinctrl-imx6ul.o obj-$(CONFIG_PINCTRL_IMX7D) +=3D pinctrl-imx7d.o obj-$(CONFIG_PINCTRL_IMX7ULP) +=3D pinctrl-imx7ulp.o +obj-$(CONFIG_PINCTRL_IMX8MM) +=3D pinctrl-imx8mm.o obj-$(CONFIG_PINCTRL_IMX8MQ) +=3D pinctrl-imx8mq.o obj-$(CONFIG_PINCTRL_IMX8QXP) +=3D pinctrl-imx8qxp.o obj-$(CONFIG_PINCTRL_VF610) +=3D pinctrl-vf610.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mm.c b/drivers/pinctrl/f= reescale/pinctrl-imx8mm.c new file mode 100644 index 0000000..6d1038a --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx8mm.c @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2017-2018 NXP + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx8mm_pads { + MX8MM_PAD_RESERVE0 =3D 0, + MX8MM_PAD_RESERVE1 =3D 1, + MX8MM_PAD_RESERVE2 =3D 2, + MX8MM_PAD_RESERVE3 =3D 3, + MX8MM_PAD_RESERVE4 =3D 4, + MX8MM_PAD_RESERVE5 =3D 5, + MX8MM_PAD_RESERVE6 =3D 6, + MX8MM_PAD_RESERVE7 =3D 7, + MX8MM_PAD_RESERVE8 =3D 8, + MX8MM_PAD_RESERVE9 =3D 9, + MX8MM_IOMUXC_GPIO1_IO00 =3D 10, + MX8MM_IOMUXC_GPIO1_IO01 =3D 11, + MX8MM_IOMUXC_GPIO1_IO02 =3D 12, + MX8MM_IOMUXC_GPIO1_IO03 =3D 13, + MX8MM_IOMUXC_GPIO1_IO04 =3D 14, + MX8MM_IOMUXC_GPIO1_IO05 =3D 15, + MX8MM_IOMUXC_GPIO1_IO06 =3D 16, + MX8MM_IOMUXC_GPIO1_IO07 =3D 17, + MX8MM_IOMUXC_GPIO1_IO08 =3D 18, + MX8MM_IOMUXC_GPIO1_IO09 =3D 19, + MX8MM_IOMUXC_GPIO1_IO10 =3D 20, + MX8MM_IOMUXC_GPIO1_IO11 =3D 21, + MX8MM_IOMUXC_GPIO1_IO12 =3D 22, + MX8MM_IOMUXC_GPIO1_IO13 =3D 23, + MX8MM_IOMUXC_GPIO1_IO14 =3D 24, + MX8MM_IOMUXC_GPIO1_IO15 =3D 25, + MX8MM_IOMUXC_ENET_MDC =3D 26, + MX8MM_IOMUXC_ENET_MDIO =3D 27, + MX8MM_IOMUXC_ENET_TD3 =3D 28, + MX8MM_IOMUXC_ENET_TD2 =3D 29, + MX8MM_IOMUXC_ENET_TD1 =3D 30, + MX8MM_IOMUXC_ENET_TD0 =3D 31, + MX8MM_IOMUXC_ENET_TX_CTL =3D 32, + MX8MM_IOMUXC_ENET_TXC =3D 33, + MX8MM_IOMUXC_ENET_RX_CTL =3D 34, + MX8MM_IOMUXC_ENET_RXC =3D 35, + MX8MM_IOMUXC_ENET_RD0 =3D 36, + MX8MM_IOMUXC_ENET_RD1 =3D 37, + MX8MM_IOMUXC_ENET_RD2 =3D 38, + MX8MM_IOMUXC_ENET_RD3 =3D 39, + MX8MM_IOMUXC_SD1_CLK =3D 40, + MX8MM_IOMUXC_SD1_CMD =3D 41, + MX8MM_IOMUXC_SD1_DATA0 =3D 42, + MX8MM_IOMUXC_SD1_DATA1 =3D 43, + MX8MM_IOMUXC_SD1_DATA2 =3D 44, + MX8MM_IOMUXC_SD1_DATA3 =3D 45, + MX8MM_IOMUXC_SD1_DATA4 =3D 46, + MX8MM_IOMUXC_SD1_DATA5 =3D 47, + MX8MM_IOMUXC_SD1_DATA6 =3D 48, + MX8MM_IOMUXC_SD1_DATA7 =3D 49, + MX8MM_IOMUXC_SD1_RESET_B =3D 50, + MX8MM_IOMUXC_SD1_STROBE =3D 51, + MX8MM_IOMUXC_SD2_CD_B =3D 52, + MX8MM_IOMUXC_SD2_CLK =3D 53, + MX8MM_IOMUXC_SD2_CMD =3D 54, + MX8MM_IOMUXC_SD2_DATA0 =3D 55, + MX8MM_IOMUXC_SD2_DATA1 =3D 56, + MX8MM_IOMUXC_SD2_DATA2 =3D 57, + MX8MM_IOMUXC_SD2_DATA3 =3D 58, + MX8MM_IOMUXC_SD2_RESET_B =3D 59, + MX8MM_IOMUXC_SD2_WP =3D 60, + MX8MM_IOMUXC_NAND_ALE =3D 61, + MX8MM_IOMUXC_NAND_CE0 =3D 62, + MX8MM_IOMUXC_NAND_CE1 =3D 63, + MX8MM_IOMUXC_NAND_CE2 =3D 64, + MX8MM_IOMUXC_NAND_CE3 =3D 65, + MX8MM_IOMUXC_NAND_CLE =3D 66, + MX8MM_IOMUXC_NAND_DATA00 =3D 67, + MX8MM_IOMUXC_NAND_DATA01 =3D 68, + MX8MM_IOMUXC_NAND_DATA02 =3D 69, + MX8MM_IOMUXC_NAND_DATA03 =3D 70, + MX8MM_IOMUXC_NAND_DATA04 =3D 71, + MX8MM_IOMUXC_NAND_DATA05 =3D 72, + MX8MM_IOMUXC_NAND_DATA06 =3D 73, + MX8MM_IOMUXC_NAND_DATA07 =3D 74, + MX8MM_IOMUXC_NAND_DQS =3D 75, + MX8MM_IOMUXC_NAND_RE_B =3D 76, + MX8MM_IOMUXC_NAND_READY_B =3D 77, + MX8MM_IOMUXC_NAND_WE_B =3D 78, + MX8MM_IOMUXC_NAND_WP_B =3D 79, + MX8MM_IOMUXC_SAI5_RXFS =3D 80, + MX8MM_IOMUXC_SAI5_RXC =3D 81, + MX8MM_IOMUXC_SAI5_RXD0 =3D 82, + MX8MM_IOMUXC_SAI5_RXD1 =3D 83, + MX8MM_IOMUXC_SAI5_RXD2 =3D 84, + MX8MM_IOMUXC_SAI5_RXD3 =3D 85, + MX8MM_IOMUXC_SAI5_MCLK =3D 86, + MX8MM_IOMUXC_SAI1_RXFS =3D 87, + MX8MM_IOMUXC_SAI1_RXC =3D 88, + MX8MM_IOMUXC_SAI1_RXD0 =3D 89, + MX8MM_IOMUXC_SAI1_RXD1 =3D 90, + MX8MM_IOMUXC_SAI1_RXD2 =3D 91, + MX8MM_IOMUXC_SAI1_RXD3 =3D 92, + MX8MM_IOMUXC_SAI1_RXD4 =3D 93, + MX8MM_IOMUXC_SAI1_RXD5 =3D 94, + MX8MM_IOMUXC_SAI1_RXD6 =3D 95, + MX8MM_IOMUXC_SAI1_RXD7 =3D 96, + MX8MM_IOMUXC_SAI1_TXFS =3D 97, + MX8MM_IOMUXC_SAI1_TXC =3D 98, + MX8MM_IOMUXC_SAI1_TXD0 =3D 99, + MX8MM_IOMUXC_SAI1_TXD1 =3D 100, + MX8MM_IOMUXC_SAI1_TXD2 =3D 101, + MX8MM_IOMUXC_SAI1_TXD3 =3D 102, + MX8MM_IOMUXC_SAI1_TXD4 =3D 103, + MX8MM_IOMUXC_SAI1_TXD5 =3D 104, + MX8MM_IOMUXC_SAI1_TXD6 =3D 105, + MX8MM_IOMUXC_SAI1_TXD7 =3D 106, + MX8MM_IOMUXC_SAI1_MCLK =3D 107, + MX8MM_IOMUXC_SAI2_RXFS =3D 108, + MX8MM_IOMUXC_SAI2_RXC =3D 109, + MX8MM_IOMUXC_SAI2_RXD0 =3D 110, + MX8MM_IOMUXC_SAI2_TXFS =3D 111, + MX8MM_IOMUXC_SAI2_TXC =3D 112, + MX8MM_IOMUXC_SAI2_TXD0 =3D 113, + MX8MM_IOMUXC_SAI2_MCLK =3D 114, + MX8MM_IOMUXC_SAI3_RXFS =3D 115, + MX8MM_IOMUXC_SAI3_RXC =3D 116, + MX8MM_IOMUXC_SAI3_RXD =3D 117, + MX8MM_IOMUXC_SAI3_TXFS =3D 118, + MX8MM_IOMUXC_SAI3_TXC =3D 119, + MX8MM_IOMUXC_SAI3_TXD =3D 120, + MX8MM_IOMUXC_SAI3_MCLK =3D 121, + MX8MM_IOMUXC_SPDIF_TX =3D 122, + MX8MM_IOMUXC_SPDIF_RX =3D 123, + MX8MM_IOMUXC_SPDIF_EXT_CLK =3D 124, + MX8MM_IOMUXC_ECSPI1_SCLK =3D 125, + MX8MM_IOMUXC_ECSPI1_MOSI =3D 126, + MX8MM_IOMUXC_ECSPI1_MISO =3D 127, + MX8MM_IOMUXC_ECSPI1_SS0 =3D 128, + MX8MM_IOMUXC_ECSPI2_SCLK =3D 129, + MX8MM_IOMUXC_ECSPI2_MOSI =3D 130, + MX8MM_IOMUXC_ECSPI2_MISO =3D 131, + MX8MM_IOMUXC_ECSPI2_SS0 =3D 132, + MX8MM_IOMUXC_I2C1_SCL =3D 133, + MX8MM_IOMUXC_I2C1_SDA =3D 134, + MX8MM_IOMUXC_I2C2_SCL =3D 135, + MX8MM_IOMUXC_I2C2_SDA =3D 136, + MX8MM_IOMUXC_I2C3_SCL =3D 137, + MX8MM_IOMUXC_I2C3_SDA =3D 138, + MX8MM_IOMUXC_I2C4_SCL =3D 139, + MX8MM_IOMUXC_I2C4_SDA =3D 140, + MX8MM_IOMUXC_UART1_RXD =3D 141, + MX8MM_IOMUXC_UART1_TXD =3D 142, + MX8MM_IOMUXC_UART2_RXD =3D 143, + MX8MM_IOMUXC_UART2_TXD =3D 144, + MX8MM_IOMUXC_UART3_RXD =3D 145, + MX8MM_IOMUXC_UART3_TXD =3D 146, + MX8MM_IOMUXC_UART4_RXD =3D 147, + MX8MM_IOMUXC_UART4_TXD =3D 148, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx8mm_pinctrl_pads[] =3D { + IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO00), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO01), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO02), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO03), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO04), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO05), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO06), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO07), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO08), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO09), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO10), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO11), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO12), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO13), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO14), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO15), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDC), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDIO), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD3), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD2), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD1), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD0), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TX_CTL), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TXC), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RX_CTL), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RXC), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD0), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD1), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD2), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD3), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CLK), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CMD), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA0), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA1), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA2), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA3), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA4), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA5), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA6), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA7), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_RESET_B), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_STROBE), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CD_B), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CLK), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CMD), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA0), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA1), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA2), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA3), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_RESET_B), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_WP), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_ALE), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE0), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE1), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE2), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE3), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CLE), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA00), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA01), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA02), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA03), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA04), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA05), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA06), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA07), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DQS), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_RE_B), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_READY_B), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WE_B), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WP_B), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXFS), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXC), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD0), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD1), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD2), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD3), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_MCLK), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXFS), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXC), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD0), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD1), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD2), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD3), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD4), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD5), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD6), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD7), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXFS), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXC), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD0), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD1), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD2), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD3), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD4), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD5), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD6), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD7), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_MCLK), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXFS), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXC), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXD0), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXFS), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXC), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXD0), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_MCLK), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXFS), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXC), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXD), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXFS), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXC), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXD), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_MCLK), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_TX), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_RX), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SCLK), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MOSI), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MISO), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SS0), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SCLK), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MOSI), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MISO), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SS0), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SCL), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SDA), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SCL), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SDA), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SCL), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SDA), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SCL), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SDA), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_RXD), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_TXD), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_RXD), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_TXD), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_RXD), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_TXD), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_RXD), + IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_TXD), +}; + +static const struct imx_pinctrl_soc_info imx8mm_pinctrl_info =3D { + .pins =3D imx8mm_pinctrl_pads, + .npins =3D ARRAY_SIZE(imx8mm_pinctrl_pads), + .gpr_compatible =3D "fsl,imx8mm-iomuxc-gpr", +}; + +static const struct of_device_id imx8mm_pinctrl_of_match[] =3D { + { .compatible =3D "fsl,imx8mm-iomuxc", .data =3D &imx8mm_pinctrl_info, }, + { /* sentinel */ } +}; + +static int imx8mm_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx8mm_pinctrl_info); +} + +static struct platform_driver imx8mm_pinctrl_driver =3D { + .driver =3D { + .name =3D "imx8mm-pinctrl", + .of_match_table =3D of_match_ptr(imx8mm_pinctrl_of_match), + .suppress_bind_attrs =3D true, + }, + .probe =3D imx8mm_pinctrl_probe, +}; + +static int __init imx8mm_pinctrl_init(void) +{ + return platform_driver_register(&imx8mm_pinctrl_driver); +} +arch_initcall(imx8mm_pinctrl_init); --=20 1.9.1