From: Patrick Delaunay <patrick.delaunay@st.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 7/7] clk: stm32mp1: correctly handle Clock Spreading Generator
Date: Wed, 30 Jan 2019 13:07:06 +0100 [thread overview]
Message-ID: <1548850026-31746-8-git-send-email-patrick.delaunay@st.com> (raw)
In-Reply-To: <1548850026-31746-1-git-send-email-patrick.delaunay@st.com>
To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
---
doc/device-tree-bindings/clock/st,stm32mp1.txt | 10 +++++-----
drivers/clk/clk_stm32mp1.c | 8 +++++++-
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt
index 6a9397e..ffcf8cd 100644
--- a/doc/device-tree-bindings/clock/st,stm32mp1.txt
+++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt
@@ -132,15 +132,15 @@ Optional Properties:
frac = < 0x810 >;
};
st,pll at 1 {
- cfg = < 1 43 1 0 0 PQR(0,1,1)>;
- csg = <10 20 1>;
+ cfg = < 1 43 1 0 0 PQR(0,1,1) >;
+ csg = < 10 20 1 >;
};
st,pll at 2 {
- cfg = < 2 85 3 13 3 0>;
- csg = <10 20 SSCG_MODE_CENTER_SPREAD>;
+ cfg = < 2 85 3 13 3 0 >;
+ csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
};
st,pll at 3 {
- cfg = < 2 78 4 7 9 3>;
+ cfg = < 2 78 4 7 9 3 >;
};
st,pkcs = <
CLK_STGEN_HSE
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 76b7b5a..24859fd 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -167,6 +167,7 @@
/* used for ALL PLLNCR registers */
#define RCC_PLLNCR_PLLON BIT(0)
#define RCC_PLLNCR_PLLRDY BIT(1)
+#define RCC_PLLNCR_SSCG_CTRL BIT(2)
#define RCC_PLLNCR_DIVPEN BIT(4)
#define RCC_PLLNCR_DIVQEN BIT(5)
#define RCC_PLLNCR_DIVREN BIT(6)
@@ -1321,7 +1322,10 @@ static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
{
const struct stm32mp1_clk_pll *pll = priv->data->pll;
- writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
+ clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
+ RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
+ RCC_PLLNCR_DIVREN,
+ RCC_PLLNCR_PLLON);
}
static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
@@ -1440,6 +1444,8 @@ static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
RCC_PLLNCSGR_SSCG_MODE_MASK);
writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
+
+ setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
}
static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
--
2.7.4
next prev parent reply other threads:[~2019-01-30 12:07 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-30 12:06 [U-Boot] [PATCH 0/7] stm32mp1: update clock driver Patrick Delaunay
2019-01-30 12:07 ` [U-Boot] [PATCH 1/7] clk: stm32mp1: no more get ck_usbo_48m in device tree Patrick Delaunay
2019-02-10 13:08 ` [U-Boot] [U-Boot, " Tom Rini
2019-01-30 12:07 ` [U-Boot] [PATCH 2/7] clk: stm32mp1: add IPCC clock Patrick Delaunay
2019-02-10 13:08 ` [U-Boot] [U-Boot,2/7] " Tom Rini
2019-01-30 12:07 ` [U-Boot] [PATCH 3/7] clk: stm32mp1: correct access to RCC_OCENSETR/RCC_OCENCLRR Patrick Delaunay
2019-02-10 13:09 ` [U-Boot] [U-Boot, " Tom Rini
2019-02-10 13:09 ` Tom Rini
2019-01-30 12:07 ` [U-Boot] [PATCH 4/7] clk: stm32mp1: recalculate counter when switching freq Patrick Delaunay
2019-02-10 13:09 ` [U-Boot] [U-Boot, " Tom Rini
2019-01-30 12:07 ` [U-Boot] [PATCH 5/7] clk: stm32mp1: add debug information Patrick Delaunay
2019-02-10 13:09 ` [U-Boot] [U-Boot,5/7] " Tom Rini
2019-01-30 12:07 ` [U-Boot] [PATCH 6/7] dts: stm32mp1: clock tree update Patrick Delaunay
2019-02-10 13:09 ` [U-Boot] [U-Boot,6/7] " Tom Rini
2019-01-30 12:07 ` Patrick Delaunay [this message]
2019-02-10 13:09 ` [U-Boot] [U-Boot, 7/7] clk: stm32mp1: correctly handle Clock Spreading Generator Tom Rini
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