From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17779C10F02 for ; Mon, 18 Feb 2019 06:11:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CFDA52147C for ; Mon, 18 Feb 2019 06:11:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727024AbfBRGLI (ORCPT ); Mon, 18 Feb 2019 01:11:08 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:28091 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725802AbfBRGLI (ORCPT ); Mon, 18 Feb 2019 01:11:08 -0500 X-UUID: 29095882f26f41a6b518ab04a4a70584-20190218 X-UUID: 29095882f26f41a6b518ab04a4a70584-20190218 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2059400189; Mon, 18 Feb 2019 14:10:58 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 18 Feb 2019 14:10:57 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 18 Feb 2019 14:10:57 +0800 Message-ID: <1550470257.19053.1.camel@mtksdaap41> Subject: Re: [PATCH v7 4/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile From: Erin Lo To: Linus Walleij CC: Matthias Brugger , Rob Herring , Mark Rutland , Thomas Gleixner , Jason Cooper , Marc Zyngier , Greg Kroah-Hartman , Stephen Boyd , , srv_heupstream , , , , , , , , , Ben Ho , Seiya Wang , Weiyi Lu , Zhiyong Tao , Hsin-Hsiung Wang Date: Mon, 18 Feb 2019 14:10:57 +0800 In-Reply-To: <1550210558-30516-5-git-send-email-erin.lo@mediatek.com> References: <1550210558-30516-1-git-send-email-erin.lo@mediatek.com> <1550210558-30516-5-git-send-email-erin.lo@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2019-02-15 at 14:02 +0800, Erin Lo wrote: > From: Ben Ho > > Add basic chip support for Mediatek 8183, include > uart node with correct uart clocks, pwrap device > > Add clock controller nodes, include topckgen, infracfg, > apmixedsys and subsystem. > > Signed-off-by: Ben Ho > Signed-off-by: Erin Lo > Signed-off-by: Seiya Wang > Signed-off-by: Weiyi Lu > Signed-off-by: Zhiyong Tao > Signed-off-by: Hsin-Hsiung Wang > Signed-off-by: Eddie Huang > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 31 +++ > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 336 ++++++++++++++++++++++++++++ > 3 files changed, 368 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index e8f952f..458bbc4 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > new file mode 100644 > index 0000000..9b52559 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Ben Ho > + * Erin Lo > + */ > + > +/dts-v1/; > +#include "mt8183.dtsi" > + > +/ { > + model = "MediaTek MT8183 evaluation board"; > + compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0x80000000>; > + }; > + > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > new file mode 100644 > index 0000000..1bd1399 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -0,0 +1,336 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Ben Ho > + * Erin Lo > + */ > + > +#include > +#include > +#include > + > +/ { > + compatible = "mediatek,mt8183"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x000>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x001>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x002>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x003>; > + enable-method = "psci"; > + }; > + > + cpu4: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x100>; > + enable-method = "psci"; > + }; > + > + cpu5: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x101>; > + enable-method = "psci"; > + }; > + > + cpu6: cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x102>; > + enable-method = "psci"; > + }; > + > + cpu7: cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x103>; > + enable-method = "psci"; > + }; > + }; > + > + pmu-a53 { > + compatible = "arm,cortex-a53-pmu"; > + interrupt-parent = <&gic>; > + interrupts = ; > + }; > + > + pmu-a73 { > + compatible = "arm,cortex-a73-pmu"; > + interrupt-parent = <&gic>; > + interrupts = ; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + clk26m: oscillator { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + clock-output-names = "clk26m"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + ; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <4>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x40000>, /* GICD */ > + <0 0x0c100000 0 0x200000>, /* GICR */ > + <0 0x0c400000 0 0x2000>, /* GICC */ > + <0 0x0c410000 0 0x1000>, /* GICH */ > + <0 0x0c420000 0 0x2000>; /* GICV */ > + > + interrupts = ; > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > + }; > + ppi_cluster1: interrupt-partition-1 { > + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; > + }; > + }; > + }; > + > + mcucfg: syscon@c530000 { > + compatible = "mediatek,mt8183-mcucfg", "syscon"; > + reg = <0 0x0c530000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + sysirq: interrupt-controller@c530a80 { > + compatible = "mediatek,mt8183-sysirq", > + "mediatek,mt6577-sysirq"; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + reg = <0 0x0c530a80 0 0x50>; > + }; > + > + topckgen: syscon@10000000 { > + compatible = "mediatek,mt8183-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg: syscon@10001000 { > + compatible = "mediatek,mt8183-infracfg", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pio: pinctrl@10005000 { > + compatible = "mediatek,mt8183-pinctrl"; > + reg = <0 0x10005000 0 0x1000>, > + <0 0x11f20000 0 0x1000>, > + <0 0x11e80000 0 0x1000>, > + <0 0x11e70000 0 0x1000>, > + <0 0x11e90000 0 0x1000>, > + <0 0x11d30000 0 0x1000>, > + <0 0x11d20000 0 0x1000>, > + <0 0x11c50000 0 0x1000>, > + <0 0x11f30000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "iocfg0", "iocfg1", "iocfg2", > + "iocfg3", "iocfg4", "iocfg5", > + "iocfg6", "iocfg7", "iocfg8", > + "eint"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 192>; > + interrupt-controller; > + interrupts = ; > + interrupt-parent = <&gic>; interrupt-parent should be sysirq not gic We will remove it in next version. Best Regards, Erin > + #interrupt-cells = <4>; > + }; > + > + apmixedsys: syscon@1000c000 { > + compatible = "mediatek,mt8183-apmixedsys", "syscon"; > + reg = <0 0x1000c000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pwrap: pwrap@1000d000 { > + compatible = "mediatek,mt8183-pwrap"; > + reg = <0 0x1000d000 0 0x1000>; > + reg-names = "pwrap"; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, > + <&infracfg CLK_INFRA_PMIC_AP>; > + clock-names = "spi", "wrap"; > + }; > + > + uart0: serial@11002000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11002000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart1: serial@11003000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11003000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart2: serial@11004000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11004000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + audiosys: syscon@11220000 { > + compatible = "mediatek,mt8183-audiosys", "syscon"; > + reg = <0 0x11220000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mfgcfg: syscon@13000000 { > + compatible = "mediatek,mt8183-mfgcfg", "syscon"; > + reg = <0 0x13000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mmsys: syscon@14000000 { > + compatible = "mediatek,mt8183-mmsys", "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + imgsys: syscon@15020000 { > + compatible = "mediatek,mt8183-imgsys", "syscon"; > + reg = <0 0x15020000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vdecsys: syscon@16000000 { > + compatible = "mediatek,mt8183-vdecsys", "syscon"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vencsys: syscon@17000000 { > + compatible = "mediatek,mt8183-vencsys", "syscon"; > + reg = <0 0x17000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_conn: syscon@19000000 { > + compatible = "mediatek,mt8183-ipu_conn", "syscon"; > + reg = <0 0x19000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_adl: syscon@19010000 { > + compatible = "mediatek,mt8183-ipu_adl", "syscon"; > + reg = <0 0x19010000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_core0: syscon@19180000 { > + compatible = "mediatek,mt8183-ipu_core0", "syscon"; > + reg = <0 0x19180000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_core1: syscon@19280000 { > + compatible = "mediatek,mt8183-ipu_core1", "syscon"; > + reg = <0 0x19280000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + camsys: syscon@1a000000 { > + compatible = "mediatek,mt8183-camsys", "syscon"; > + reg = <0 0x1a000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + }; > +}; From mboxrd@z Thu Jan 1 00:00:00 1970 From: Erin Lo Subject: Re: [PATCH v7 4/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile Date: Mon, 18 Feb 2019 14:10:57 +0800 Message-ID: <1550470257.19053.1.camel@mtksdaap41> References: <1550210558-30516-1-git-send-email-erin.lo@mediatek.com> <1550210558-30516-5-git-send-email-erin.lo@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1550210558-30516-5-git-send-email-erin.lo@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org To: Linus Walleij Cc: Matthias Brugger , Rob Herring , Mark Rutland , Thomas Gleixner , Jason Cooper , Marc Zyngier , Greg Kroah-Hartman , Stephen Boyd , devicetree@vger.kernel.org, srv_heupstream , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, yingjoe.chen@mediatek.com, mars.cheng@mediatek.com, eddie.huang@mediatek.com, linux-clk@vger.kernel.org, Ben Ho , Seiya Wang , Weiyi Lu , Zhiyong List-Id: devicetree@vger.kernel.org On Fri, 2019-02-15 at 14:02 +0800, Erin Lo wrote: > From: Ben Ho > > Add basic chip support for Mediatek 8183, include > uart node with correct uart clocks, pwrap device > > Add clock controller nodes, include topckgen, infracfg, > apmixedsys and subsystem. > > Signed-off-by: Ben Ho > Signed-off-by: Erin Lo > Signed-off-by: Seiya Wang > Signed-off-by: Weiyi Lu > Signed-off-by: Zhiyong Tao > Signed-off-by: Hsin-Hsiung Wang > Signed-off-by: Eddie Huang > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 31 +++ > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 336 ++++++++++++++++++++++++++++ > 3 files changed, 368 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index e8f952f..458bbc4 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > new file mode 100644 > index 0000000..9b52559 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Ben Ho > + * Erin Lo > + */ > + > +/dts-v1/; > +#include "mt8183.dtsi" > + > +/ { > + model = "MediaTek MT8183 evaluation board"; > + compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0x80000000>; > + }; > + > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > new file mode 100644 > index 0000000..1bd1399 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -0,0 +1,336 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Ben Ho > + * Erin Lo > + */ > + > +#include > +#include > +#include > + > +/ { > + compatible = "mediatek,mt8183"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x000>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x001>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x002>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x003>; > + enable-method = "psci"; > + }; > + > + cpu4: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x100>; > + enable-method = "psci"; > + }; > + > + cpu5: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x101>; > + enable-method = "psci"; > + }; > + > + cpu6: cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x102>; > + enable-method = "psci"; > + }; > + > + cpu7: cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x103>; > + enable-method = "psci"; > + }; > + }; > + > + pmu-a53 { > + compatible = "arm,cortex-a53-pmu"; > + interrupt-parent = <&gic>; > + interrupts = ; > + }; > + > + pmu-a73 { > + compatible = "arm,cortex-a73-pmu"; > + interrupt-parent = <&gic>; > + interrupts = ; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + clk26m: oscillator { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + clock-output-names = "clk26m"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + ; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <4>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x40000>, /* GICD */ > + <0 0x0c100000 0 0x200000>, /* GICR */ > + <0 0x0c400000 0 0x2000>, /* GICC */ > + <0 0x0c410000 0 0x1000>, /* GICH */ > + <0 0x0c420000 0 0x2000>; /* GICV */ > + > + interrupts = ; > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > + }; > + ppi_cluster1: interrupt-partition-1 { > + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; > + }; > + }; > + }; > + > + mcucfg: syscon@c530000 { > + compatible = "mediatek,mt8183-mcucfg", "syscon"; > + reg = <0 0x0c530000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + sysirq: interrupt-controller@c530a80 { > + compatible = "mediatek,mt8183-sysirq", > + "mediatek,mt6577-sysirq"; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + reg = <0 0x0c530a80 0 0x50>; > + }; > + > + topckgen: syscon@10000000 { > + compatible = "mediatek,mt8183-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg: syscon@10001000 { > + compatible = "mediatek,mt8183-infracfg", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pio: pinctrl@10005000 { > + compatible = "mediatek,mt8183-pinctrl"; > + reg = <0 0x10005000 0 0x1000>, > + <0 0x11f20000 0 0x1000>, > + <0 0x11e80000 0 0x1000>, > + <0 0x11e70000 0 0x1000>, > + <0 0x11e90000 0 0x1000>, > + <0 0x11d30000 0 0x1000>, > + <0 0x11d20000 0 0x1000>, > + <0 0x11c50000 0 0x1000>, > + <0 0x11f30000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "iocfg0", "iocfg1", "iocfg2", > + "iocfg3", "iocfg4", "iocfg5", > + "iocfg6", "iocfg7", "iocfg8", > + "eint"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 192>; > + interrupt-controller; > + interrupts = ; > + interrupt-parent = <&gic>; interrupt-parent should be sysirq not gic We will remove it in next version. Best Regards, Erin > + #interrupt-cells = <4>; > + }; > + > + apmixedsys: syscon@1000c000 { > + compatible = "mediatek,mt8183-apmixedsys", "syscon"; > + reg = <0 0x1000c000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pwrap: pwrap@1000d000 { > + compatible = "mediatek,mt8183-pwrap"; > + reg = <0 0x1000d000 0 0x1000>; > + reg-names = "pwrap"; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, > + <&infracfg CLK_INFRA_PMIC_AP>; > + clock-names = "spi", "wrap"; > + }; > + > + uart0: serial@11002000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11002000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart1: serial@11003000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11003000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart2: serial@11004000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11004000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + audiosys: syscon@11220000 { > + compatible = "mediatek,mt8183-audiosys", "syscon"; > + reg = <0 0x11220000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mfgcfg: syscon@13000000 { > + compatible = "mediatek,mt8183-mfgcfg", "syscon"; > + reg = <0 0x13000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mmsys: syscon@14000000 { > + compatible = "mediatek,mt8183-mmsys", "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + imgsys: syscon@15020000 { > + compatible = "mediatek,mt8183-imgsys", "syscon"; > + reg = <0 0x15020000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vdecsys: syscon@16000000 { > + compatible = "mediatek,mt8183-vdecsys", "syscon"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vencsys: syscon@17000000 { > + compatible = "mediatek,mt8183-vencsys", "syscon"; > + reg = <0 0x17000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_conn: syscon@19000000 { > + compatible = "mediatek,mt8183-ipu_conn", "syscon"; > + reg = <0 0x19000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_adl: syscon@19010000 { > + compatible = "mediatek,mt8183-ipu_adl", "syscon"; > + reg = <0 0x19010000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_core0: syscon@19180000 { > + compatible = "mediatek,mt8183-ipu_core0", "syscon"; > + reg = <0 0x19180000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_core1: syscon@19280000 { > + compatible = "mediatek,mt8183-ipu_core1", "syscon"; > + reg = <0 0x19280000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + camsys: syscon@1a000000 { > + compatible = "mediatek,mt8183-camsys", "syscon"; > + reg = <0 0x1a000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + }; > +}; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7228DC43381 for ; Mon, 18 Feb 2019 06:11:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 42D3A2147C for ; Mon, 18 Feb 2019 06:11:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="hBUyChHN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 42D3A2147C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WXs3KuPD2ZAWJ4RA6ldEP15Dxir+1eEM5E//saN1TLY=; b=hBUyChHNV4oA1C iDuZOx5e/atvpVfZtjlRlNISZFkDGf6XbHBhTCdJylztxZxvEyKNQ6Ug0YutjNEjhPX5ODL28yAyK appljjnKMOyoL0zgOaItUh6l7K0axZ8NSvynBAvtEcKzxldwWLm3ZZamImIiyh0o424gWmzLQk4/r tFvI/sv/sRnXVEjdEnxYp8wtZsFvz0CnXm2QwWgLM6qdb1Adhm3du3Sz9+jsKy9FK36ZoH+iYtJxj 5n0eOfHjvhDtq+hjk4f1CqqH88WT2L0lu2UL9wt8TQCDpwrIiE0JAdg+XpggnQ7+dFOGWc30hHeEz 8de2o+7XwH6Cu4EtTUFQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gvc9C-0003yp-BU; Mon, 18 Feb 2019 06:11:22 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gvc98-0003xx-Jn; Mon, 18 Feb 2019 06:11:20 +0000 X-UUID: 0be1bc53ac184a8cae04fbcb10459f4a-20190217 X-UUID: 0be1bc53ac184a8cae04fbcb10459f4a-20190217 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1729726922; Sun, 17 Feb 2019 22:11:13 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 17 Feb 2019 22:11:10 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 18 Feb 2019 14:10:57 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 18 Feb 2019 14:10:57 +0800 Message-ID: <1550470257.19053.1.camel@mtksdaap41> Subject: Re: [PATCH v7 4/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile From: Erin Lo To: Linus Walleij Date: Mon, 18 Feb 2019 14:10:57 +0800 In-Reply-To: <1550210558-30516-5-git-send-email-erin.lo@mediatek.com> References: <1550210558-30516-1-git-send-email-erin.lo@mediatek.com> <1550210558-30516-5-git-send-email-erin.lo@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190217_221118_659748_D3E10B22 X-CRM114-Status: GOOD ( 17.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Ben Ho , mars.cheng@mediatek.com, linux-clk@vger.kernel.org, Hsin-Hsiung Wang , Weiyi Lu , Seiya Wang , linux-serial@vger.kernel.org, yingjoe.chen@mediatek.com, devicetree@vger.kernel.org, Jason Cooper , Marc Zyngier , Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , Thomas Gleixner , eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org, srv_heupstream , Greg Kroah-Hartman , Stephen Boyd , linux-kernel@vger.kernel.org, Zhiyong Tao Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 2019-02-15 at 14:02 +0800, Erin Lo wrote: > From: Ben Ho > > Add basic chip support for Mediatek 8183, include > uart node with correct uart clocks, pwrap device > > Add clock controller nodes, include topckgen, infracfg, > apmixedsys and subsystem. > > Signed-off-by: Ben Ho > Signed-off-by: Erin Lo > Signed-off-by: Seiya Wang > Signed-off-by: Weiyi Lu > Signed-off-by: Zhiyong Tao > Signed-off-by: Hsin-Hsiung Wang > Signed-off-by: Eddie Huang > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 31 +++ > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 336 ++++++++++++++++++++++++++++ > 3 files changed, 368 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index e8f952f..458bbc4 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > new file mode 100644 > index 0000000..9b52559 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Ben Ho > + * Erin Lo > + */ > + > +/dts-v1/; > +#include "mt8183.dtsi" > + > +/ { > + model = "MediaTek MT8183 evaluation board"; > + compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0x80000000>; > + }; > + > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > new file mode 100644 > index 0000000..1bd1399 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -0,0 +1,336 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Ben Ho > + * Erin Lo > + */ > + > +#include > +#include > +#include > + > +/ { > + compatible = "mediatek,mt8183"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x000>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x001>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x002>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x003>; > + enable-method = "psci"; > + }; > + > + cpu4: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x100>; > + enable-method = "psci"; > + }; > + > + cpu5: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x101>; > + enable-method = "psci"; > + }; > + > + cpu6: cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x102>; > + enable-method = "psci"; > + }; > + > + cpu7: cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x103>; > + enable-method = "psci"; > + }; > + }; > + > + pmu-a53 { > + compatible = "arm,cortex-a53-pmu"; > + interrupt-parent = <&gic>; > + interrupts = ; > + }; > + > + pmu-a73 { > + compatible = "arm,cortex-a73-pmu"; > + interrupt-parent = <&gic>; > + interrupts = ; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + clk26m: oscillator { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + clock-output-names = "clk26m"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + ; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <4>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x40000>, /* GICD */ > + <0 0x0c100000 0 0x200000>, /* GICR */ > + <0 0x0c400000 0 0x2000>, /* GICC */ > + <0 0x0c410000 0 0x1000>, /* GICH */ > + <0 0x0c420000 0 0x2000>; /* GICV */ > + > + interrupts = ; > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > + }; > + ppi_cluster1: interrupt-partition-1 { > + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; > + }; > + }; > + }; > + > + mcucfg: syscon@c530000 { > + compatible = "mediatek,mt8183-mcucfg", "syscon"; > + reg = <0 0x0c530000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + sysirq: interrupt-controller@c530a80 { > + compatible = "mediatek,mt8183-sysirq", > + "mediatek,mt6577-sysirq"; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + reg = <0 0x0c530a80 0 0x50>; > + }; > + > + topckgen: syscon@10000000 { > + compatible = "mediatek,mt8183-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg: syscon@10001000 { > + compatible = "mediatek,mt8183-infracfg", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pio: pinctrl@10005000 { > + compatible = "mediatek,mt8183-pinctrl"; > + reg = <0 0x10005000 0 0x1000>, > + <0 0x11f20000 0 0x1000>, > + <0 0x11e80000 0 0x1000>, > + <0 0x11e70000 0 0x1000>, > + <0 0x11e90000 0 0x1000>, > + <0 0x11d30000 0 0x1000>, > + <0 0x11d20000 0 0x1000>, > + <0 0x11c50000 0 0x1000>, > + <0 0x11f30000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "iocfg0", "iocfg1", "iocfg2", > + "iocfg3", "iocfg4", "iocfg5", > + "iocfg6", "iocfg7", "iocfg8", > + "eint"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 192>; > + interrupt-controller; > + interrupts = ; > + interrupt-parent = <&gic>; interrupt-parent should be sysirq not gic We will remove it in next version. Best Regards, Erin > + #interrupt-cells = <4>; > + }; > + > + apmixedsys: syscon@1000c000 { > + compatible = "mediatek,mt8183-apmixedsys", "syscon"; > + reg = <0 0x1000c000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pwrap: pwrap@1000d000 { > + compatible = "mediatek,mt8183-pwrap"; > + reg = <0 0x1000d000 0 0x1000>; > + reg-names = "pwrap"; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, > + <&infracfg CLK_INFRA_PMIC_AP>; > + clock-names = "spi", "wrap"; > + }; > + > + uart0: serial@11002000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11002000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart1: serial@11003000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11003000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart2: serial@11004000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11004000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + audiosys: syscon@11220000 { > + compatible = "mediatek,mt8183-audiosys", "syscon"; > + reg = <0 0x11220000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mfgcfg: syscon@13000000 { > + compatible = "mediatek,mt8183-mfgcfg", "syscon"; > + reg = <0 0x13000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mmsys: syscon@14000000 { > + compatible = "mediatek,mt8183-mmsys", "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + imgsys: syscon@15020000 { > + compatible = "mediatek,mt8183-imgsys", "syscon"; > + reg = <0 0x15020000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vdecsys: syscon@16000000 { > + compatible = "mediatek,mt8183-vdecsys", "syscon"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vencsys: syscon@17000000 { > + compatible = "mediatek,mt8183-vencsys", "syscon"; > + reg = <0 0x17000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_conn: syscon@19000000 { > + compatible = "mediatek,mt8183-ipu_conn", "syscon"; > + reg = <0 0x19000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_adl: syscon@19010000 { > + compatible = "mediatek,mt8183-ipu_adl", "syscon"; > + reg = <0 0x19010000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_core0: syscon@19180000 { > + compatible = "mediatek,mt8183-ipu_core0", "syscon"; > + reg = <0 0x19180000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_core1: syscon@19280000 { > + compatible = "mediatek,mt8183-ipu_core1", "syscon"; > + reg = <0 0x19280000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + camsys: syscon@1a000000 { > + compatible = "mediatek,mt8183-camsys", "syscon"; > + reg = <0 0x1a000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + }; > +}; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel