[PATCH 00/26] Updates for SW SMU driver

[PATCH 00/26] Updates for SW SMU driver

[Huang Rui]

Hi all,

These series are the updates for SW SMU driver. It adds more interfaces for
sysfs and hwmon and fix some coding errors. And add suspend/resume function, for
now, it already passed S3 test with SW SMU.

Thanks,
Ray

Chengming Gui (7):
  drm/amd/powerplay: implement power1_cap and power1_cap_max interface
    for SMU11.
  drm/amd/powerplay: add STABLE_PSTATE_SCLK and STABLE_PSTATE_MCLK when
    read sensor for SMU11
  drm/amd/powerplay: implement pwm1 hwmon interface for SMU11
  drm/amd/powerplay: implement pwm1_enable hwmon interface for SMU11
  drm/amd/powerplay: implement fan1_enable hwmon interface for SMU11
    (v2)
  drm/amd/powerplay: add smu_late_init for SMU11.
  drm/amd/powerplay: add is_dpm_running for SMU11

Huang Rui (5):
  drm/amd/powerplay: fix smc messsage index report
  drm/amd/powerplay: fix byte alignment issue of smu11 pptable
  drm/amd/powerplay: move setting allowed mask and feature enabling
    together
  drm/amd/powerplay: fix the issue of checking on message mapping
  drm/amd/powerplay: use REG32_PCIE wrapper instead for sw smu

Kevin Wang (1):
  drm/amd/powerplay: debugfs don't check powerplay when SW SMU is
    enabled.

Likun Gao (13):
  drm/amd/powerplay: add fan rpm limit interface for hwmon
  drm/amd/powerplay: add fan input interface for hwmon
  drm/amd/powerplay: set fan target interface for hwmon
  drm/amd/powerplay: get eclk/vclk/dclk for smu11
  drm/amd/powerplay: set dpm table of vclk/dclk/eclk for smu11 (v2)
  drm/amd/powerplay: add limit of pp_feature for smu
  drm/amd/powerplay: add od condition for power limit
  drm/amd/powerplay: add suspend and resume function for smu
  drm/amd/powerplay: add condition for smc table hw init
  drm/amd/powerplay: support sysfs to get socclk, fclk, dcefclk
  drm/amd/powerplay: support sysfs to set socclk, fclk, dcefclk
  drm/amd/powerplay: add override pcie parameters
  drm/amd/powerplay: support sysfs to set/get pcie

 drivers/gpu/drm/amd/amdgpu/amdgpu.h                |   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c         |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c            |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c             | 143 ++++++---
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c                |   2 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c                 |   2 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |   2 +-
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c         | 262 +++++++++------
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h     |  61 +++-
 .../gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h  |   6 +-
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c          | 357 +++++++++++++++++----
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c         | 317 ++++++++++++++++--
 12 files changed, 914 insertions(+), 246 deletions(-)

-- 
2.7.4

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[PATCH 01/26] drm/amd/powerplay: debugfs don't check powerplay when SW SMU is enabled.

[Huang Rui]

From: Kevin Wang <kevin1.wang@amd.com>

when sw smu is enabled, the powerplay interface isn't implemented.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 47d2ba5..ccdb0f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2746,7 +2746,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
 	if  ((adev->flags & AMD_IS_PX) &&
 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
 		seq_printf(m, "PX asic powered off\n");
-	} else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
+	} else if (!is_support_sw_smu(adev) && adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
 		mutex_lock(&adev->pm.mutex);
 		if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
 			adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
-- 
2.7.4

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[PATCH 02/26] drm/amd/powerplay: add fan rpm limit interface for hwmon

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

Add fan1_min and fan2_max function for hwmon.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 48174df..8d25318 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1092,6 +1092,8 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
 				 enum amd_pp_sensors sensor,
 				 void *data, uint32_t *size)
 {
+	struct smu_table_context *table_context = &smu->smu_table;
+	PPTable_t *pptable = table_context->driver_pptable;
 	int ret = 0;
 	switch (sensor) {
 	case AMDGPU_PP_SENSOR_GPU_LOAD:
@@ -1127,6 +1129,14 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
 		*(uint32_t *)data = smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT) ? 1 : 0;
 		*size = 4;
 		break;
+	case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
+		*(uint32_t *)data = 0;
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
+		*(uint32_t *)data = pptable->FanMaximumRpm;
+		*size = 4;
+		break;
 	default:
 		ret = smu_common_read_sensor(smu, sensor, data, size);
 		break;
-- 
2.7.4

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[PATCH 03/26] drm/amd/powerplay: add fan input interface for hwmon

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

Add fan1_input and fan1_target interface to get fan speed info for hwmon.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 12 ++++++++++--
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  3 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 19 ++++++++++++++++++-
 3 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index ccdb0f6..d140b3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1503,7 +1503,11 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
 	     (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return -EINVAL;
 
-	if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
+	if (is_support_sw_smu(adev)) {
+		err = smu_get_current_rpm(&adev->smu, &speed);
+		if (err)
+			return err;
+	} else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
 		err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
 		if (err)
 			return err;
@@ -1559,7 +1563,11 @@ static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
 	     (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return -EINVAL;
 
-	if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
+	if (is_support_sw_smu(adev)) {
+		err = smu_get_current_rpm(&adev->smu, &rpm);
+		if (err)
+			return err;
+	} else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
 		err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
 		if (err)
 			return err;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index d7f26e1..2cc7129 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -530,6 +530,7 @@ struct smu_funcs
 	int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
 	uint32_t (*get_sclk)(struct smu_context *smu, bool low);
 	uint32_t (*get_mclk)(struct smu_context *smu, bool low);
+	int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
 };
 
 #define smu_init_microcode(smu) \
@@ -580,6 +581,8 @@ struct smu_funcs
 	((smu)->funcs->set_od8_default_settings ? (smu)->funcs->set_od8_default_settings((smu)) : 0)
 #define smu_update_od8_settings(smu, index, value) \
 	((smu)->funcs->update_od8_settings ? (smu)->funcs->update_od8_settings((smu), (index), (value)) : 0)
+#define smu_get_current_rpm(smu, speed) \
+	((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu), (speed)) : 0)
 #define smu_send_smc_msg(smu, msg) \
 	((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
 #define smu_send_smc_msg_with_param(smu, msg, param) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 8d25318..6333c18 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1712,6 +1712,23 @@ static int smu_v11_0_dpm_set_vce_enable(struct smu_context *smu, bool enable)
 	return smu_feature_set_enabled(smu, FEATURE_DPM_UVD_BIT, enable);
 }
 
+static int smu_v11_0_get_current_rpm(struct smu_context *smu,
+				     uint32_t *current_rpm)
+{
+	int ret;
+
+	ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
+
+	if (ret) {
+		pr_err("Attempt to get current RPM from SMC Failed!\n");
+		return ret;
+	}
+
+	smu_read_smc_arg(smu, current_rpm);
+
+	return 0;
+}
+
 static const struct smu_funcs smu_v11_0_funcs = {
 	.init_microcode = smu_v11_0_init_microcode,
 	.load_microcode = smu_v11_0_load_microcode,
@@ -1761,7 +1778,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
 	.update_od8_settings = smu_v11_0_update_od8_settings,
 	.dpm_set_uvd_enable = smu_v11_0_dpm_set_uvd_enable,
 	.dpm_set_vce_enable = smu_v11_0_dpm_set_vce_enable,
-
+	.get_current_rpm = smu_v11_0_get_current_rpm,
 };
 
 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
-- 
2.7.4

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[PATCH 04/26] drm/amd/powerplay: implement power1_cap and power1_cap_max interface for SMU11.

[Huang Rui]

From: Chengming Gui <Jack.Gui@amd.com>

add get_power_limit and set_power_limit functions
to support hwmon for SMU11.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 15 ++++++++--
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     |  2 +-
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  9 ++++--
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 41 +++++++++++++++++++-------
 4 files changed, 49 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index d140b3d..92d0fb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1761,7 +1761,11 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
 	struct amdgpu_device *adev = dev_get_drvdata(dev);
 	uint32_t limit = 0;
 
-	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
+	if (is_support_sw_smu(adev)) {
+		smu_get_power_limit(&adev->smu, &limit, true);
+		return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
+	}
+	else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
 		adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
 		return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
 	} else {
@@ -1776,7 +1780,10 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
 	struct amdgpu_device *adev = dev_get_drvdata(dev);
 	uint32_t limit = 0;
 
-	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
+	if (is_support_sw_smu(adev)) {
+		smu_get_power_limit(&adev->smu, &limit, false);
+		return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
+	} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
 		adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
 		return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
 	} else {
@@ -1799,7 +1806,9 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
 		return err;
 
 	value = value / 1000000; /* convert to Watt */
-	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
+	if (is_support_sw_smu(adev))
+		adev->smu.funcs->set_power_limit(&adev->smu, value);
+	else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
 		err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
 		if (err)
 			return err;
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index ed2f7cc..ed2d199 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -619,7 +619,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
 	if (ret)
 		return ret;
 
-	ret = smu_get_power_limit(smu);
+	ret = smu_get_power_limit(smu, &smu->default_power_limit, false);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 2cc7129..d49bdee 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -484,7 +484,8 @@ struct smu_funcs
 	int (*disable_all_mask)(struct smu_context *smu);
 	int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
 	int (*notify_display_change)(struct smu_context *smu);
-	int (*get_power_limit)(struct smu_context *smu);
+	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
+	int (*set_power_limit)(struct smu_context *smu, uint32_t n);
 	int (*get_current_clk_freq)(struct smu_context *smu, uint32_t clk_id, uint32_t *value);
 	int (*init_max_sustainable_clocks)(struct smu_context *smu);
 	int (*start_thermal_control)(struct smu_context *smu);
@@ -619,8 +620,10 @@ struct smu_funcs
 	((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
 #define smu_update_specified_od8_value(smu, index, value) \
 	((smu)->ppt_funcs->update_specified_od8_value ? (smu)->ppt_funcs->update_specified_od8_value((smu), (index), (value)) : 0)
-#define smu_get_power_limit(smu) \
-	((smu)->funcs->get_power_limit? (smu)->funcs->get_power_limit((smu)) : 0)
+#define smu_get_power_limit(smu, limit, def) \
+	((smu)->funcs->get_power_limit ? (smu)->funcs->get_power_limit((smu), (limit), (def)) : 0)
+#define smu_set_power_limit(smu, limit) \
+	((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
 #define smu_get_current_clk_freq(smu, clk_id, value) \
 	((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
 #define smu_print_clk_levels(smu, type, buf) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 6333c18..7397a63 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -873,23 +873,41 @@ static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 	return 0;
 }
 
-static int smu_v11_0_get_power_limit(struct smu_context *smu)
+static int smu_v11_0_get_power_limit(struct smu_context *smu,
+				     uint32_t *limit,
+				     bool get_default)
 {
-	int ret;
-	uint32_t power_limit_value;
+	int ret = 0;
 
-	ret = smu_send_smc_msg_with_param(smu,
-			SMU_MSG_GetPptLimit,
-			POWER_SOURCE_AC << 16);
+	if (get_default) {
+		mutex_lock(&smu->mutex);
+		*limit = smu->default_power_limit;
+		mutex_unlock(&smu->mutex);
+	} else {
+			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
+							  POWER_SOURCE_AC << 16);
+			if (ret) {
+				pr_err("[%s] get PPT limit failed!", __func__);
+				return ret;
+			}
+			smu_read_smc_arg(smu, limit);
+			smu->power_limit = *limit;
+	}
+
+	return ret;
+}
+
+static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
+{
+	int ret = 0;
+		if (smu_feature_is_enabled(smu, FEATURE_PPT_BIT))
+			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
 	if (ret) {
-		pr_err("[GetPptLimit] get default PPT limit failed!");
+		pr_err("[%s] Set power limit Failed!", __func__);
 		return ret;
 	}
 
-	smu_read_smc_arg(smu, &power_limit_value);
-	smu->power_limit = smu->default_power_limit = power_limit_value;
-
-	return 0;
+	return ret;
 }
 
 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu, uint32_t clk_id, uint32_t *value)
@@ -1760,6 +1778,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
 	.update_feature_enable_state = smu_v11_0_update_feature_enable_state,
 	.notify_display_change = smu_v11_0_notify_display_change,
 	.get_power_limit = smu_v11_0_get_power_limit,
+	.set_power_limit = smu_v11_0_set_power_limit,
 	.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
 	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
 	.start_thermal_control = smu_v11_0_start_thermal_control,
-- 
2.7.4

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[PATCH 05/26] drm/amd/powerplay: add STABLE_PSTATE_SCLK and STABLE_PSTATE_MCLK when read sensor for SMU11

[Huang Rui]

From: Chengming Gui <Jack.Gui@amd.com>

add AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK and
AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK to support
read sensor for SMU11.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Kevin Wang <kevink1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index ed2d199..60491d1 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -73,6 +73,14 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 	int ret = 0;
 
 	switch (sensor) {
+	case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
+		*((uint32_t *)data) = smu->pstate_sclk;
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
+		*((uint32_t *)data) = smu->pstate_mclk;
+		*size = 4;
+		break;
 	case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 		ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 		*size = 8;
-- 
2.7.4

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[PATCH 06/26] drm/amd/powerplay: implement pwm1 hwmon interface for SMU11

[Huang Rui]

From: Chengming Gui <Jack.Gui@amd.com>

added main functions:
	get_fan_speed_percent
	set_fan_speed_percent.
added dependent functions:
	smc_fan_control
	set_fan_static_mode
	get_fan_speed_percent

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 18 ++++--
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  9 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 89 ++++++++++++++++++++++++++
 3 files changed, 112 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 92d0fb3..d40aa39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1444,8 +1444,10 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 	if  ((adev->flags & AMD_IS_PX) &&
 	     (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return -EINVAL;
-
-	pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+	if (is_support_sw_smu(adev))
+		pwm_mode = smu_get_fan_control_mode(&adev->smu);
+	else
+		pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 	if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
 		pr_info("manual fan speed control should be enabled first\n");
 		return -EINVAL;
@@ -1457,7 +1459,11 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 
 	value = (value * 100) / 255;
 
-	if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
+	if (is_support_sw_smu(adev)) {
+		err = smu_set_fan_speed_percent(&adev->smu, value);
+		if (err)
+			return err;
+	} else if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
 		err = amdgpu_dpm_set_fan_speed_percent(adev, value);
 		if (err)
 			return err;
@@ -1479,7 +1485,11 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
 	     (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return -EINVAL;
 
-	if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
+	if (is_support_sw_smu(adev)) {
+		err = smu_get_fan_speed_percent(&adev->smu, &speed);
+		if (err)
+			return err;
+	} else if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
 		err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
 		if (err)
 			return err;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index d49bdee..f94d09d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -532,6 +532,9 @@ struct smu_funcs
 	uint32_t (*get_sclk)(struct smu_context *smu, bool low);
 	uint32_t (*get_mclk)(struct smu_context *smu, bool low);
 	int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
+	uint32_t (*get_fan_control_mode)(struct smu_context *smu);
+	int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
+	int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
 };
 
 #define smu_init_microcode(smu) \
@@ -664,6 +667,12 @@ struct smu_funcs
 	((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
 #define smu_set_cpu_power_state(smu) \
 	((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
+#define smu_get_fan_control_mode(smu) \
+	((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
+#define smu_get_fan_speed_percent(smu, speed) \
+	((smu)->funcs->get_fan_speed_percent ? (smu)->funcs->get_fan_speed_percent((smu), (speed)) : 0)
+#define smu_set_fan_speed_percent(smu, speed) \
+	((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
 
 #define smu_msg_get_index(smu, msg) \
 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 7397a63..d8917b2 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1747,6 +1747,92 @@ static int smu_v11_0_get_current_rpm(struct smu_context *smu,
 	return 0;
 }
 
+static uint32_t
+smu_v11_0_get_fan_control_mode(struct smu_context *smu)
+{
+	if (!smu_feature_is_enabled(smu, FEATURE_FAN_CONTROL_BIT))
+		return AMD_FAN_CTRL_MANUAL;
+	else
+		return AMD_FAN_CTRL_AUTO;
+}
+
+static int
+smu_v11_0_get_fan_speed_percent(struct smu_context * smu,
+					   uint32_t *speed)
+{
+	int ret = 0;
+	uint32_t percent = 0;
+	uint32_t current_rpm;
+
+	PPTable_t *pptable = smu->smu_table.driver_pptable;
+	ret =  smu_v11_0_get_current_rpm(smu, &current_rpm);
+	percent = current_rpm * 100 / pptable->FanMaximumRpm;
+	*speed = percent > 100 ? 100 : percent;
+
+	return ret;
+}
+
+static int
+smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
+{
+	int ret = 0;
+
+	if (smu_feature_is_supported(smu, FEATURE_FAN_CONTROL_BIT))
+		return 0;
+
+	ret = smu_feature_set_enabled(smu, FEATURE_FAN_CONTROL_BIT, start);
+	if (ret)
+		pr_err("[%s]%s smc FAN CONTROL feature failed!",
+		       __func__, (start ? "Start" : "Stop"));
+
+	return ret;
+}
+
+static int
+smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
+{
+	struct amdgpu_device *adev = smu->adev;
+
+	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
+		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
+				   CG_FDO_CTRL2, TMIN, 0));
+	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
+		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
+				   CG_FDO_CTRL2, FDO_PWM_MODE, mode));
+
+	return 0;
+}
+
+static int
+smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
+{
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t duty100;
+	uint32_t duty;
+	uint64_t tmp64;
+	bool stop = 0;
+
+	if (speed > 100)
+		speed = 100;
+
+	if (smu_v11_0_smc_fan_control(smu, stop))
+		return -EINVAL;
+	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
+				CG_FDO_CTRL1, FMAX_DUTY100);
+	if (!duty100)
+		return -EINVAL;
+
+	tmp64 = (uint64_t)speed * duty100;
+	do_div(tmp64, 100);
+	duty = (uint32_t)tmp64;
+
+	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
+		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
+				   CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
+
+	return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
+}
+
 static const struct smu_funcs smu_v11_0_funcs = {
 	.init_microcode = smu_v11_0_init_microcode,
 	.load_microcode = smu_v11_0_load_microcode,
@@ -1798,6 +1884,9 @@ static const struct smu_funcs smu_v11_0_funcs = {
 	.dpm_set_uvd_enable = smu_v11_0_dpm_set_uvd_enable,
 	.dpm_set_vce_enable = smu_v11_0_dpm_set_vce_enable,
 	.get_current_rpm = smu_v11_0_get_current_rpm,
+	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+	.get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
+	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
 };
 
 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
-- 
2.7.4

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[PATCH 07/26] drm/amd/powerplay: implement pwm1_enable hwmon interface for SMU11

[Huang Rui]

From: Chengming Gui <Jack.Gui@amd.com>

1, set get_pwm1_enable and set_pwm1_enable functions to call
smu_get_fan_control_mode and smu_set_fan_control_mode for SMU11
2, implement set_fan_control_mode function

v2: add return value in set_fan_control_mode function

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 31 +++++++++++++++++---------
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  3 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 31 ++++++++++++++++++++++++++
 3 files changed, 55 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index d40aa39..ac991f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1382,11 +1382,14 @@ static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 {
 	struct amdgpu_device *adev = dev_get_drvdata(dev);
 	u32 pwm_mode = 0;
+	if (is_support_sw_smu(adev))
+		pwm_mode = smu_get_fan_control_mode(&adev->smu);
+	else {
+		if (!adev->powerplay.pp_funcs->get_fan_control_mode)
+			return -EINVAL;
 
-	if (!adev->powerplay.pp_funcs->get_fan_control_mode)
-		return -EINVAL;
-
-	pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+		pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+	}
 
 	return sprintf(buf, "%i\n", pwm_mode);
 }
@@ -1405,14 +1408,22 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 	     (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return -EINVAL;
 
-	if (!adev->powerplay.pp_funcs->set_fan_control_mode)
-		return -EINVAL;
+	if (is_support_sw_smu(adev)) {
+		err = kstrtoint(buf, 10, &value);
+		if (err)
+			return err;
 
-	err = kstrtoint(buf, 10, &value);
-	if (err)
-		return err;
+		smu_set_fan_control_mode(&adev->smu, value);
+	} else {
+		if (!adev->powerplay.pp_funcs->set_fan_control_mode)
+			return -EINVAL;
+
+		err = kstrtoint(buf, 10, &value);
+		if (err)
+			return err;
 
-	amdgpu_dpm_set_fan_control_mode(adev, value);
+		amdgpu_dpm_set_fan_control_mode(adev, value);
+	}
 
 	return count;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index f94d09d..ef2b807 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -533,6 +533,7 @@ struct smu_funcs
 	uint32_t (*get_mclk)(struct smu_context *smu, bool low);
 	int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
 	uint32_t (*get_fan_control_mode)(struct smu_context *smu);
+	int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
 	int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
 	int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
 };
@@ -669,6 +670,8 @@ struct smu_funcs
 	((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
 #define smu_get_fan_control_mode(smu) \
 	((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
+#define smu_set_fan_control_mode(smu, value) \
+	((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
 #define smu_get_fan_speed_percent(smu, speed) \
 	((smu)->funcs->get_fan_speed_percent ? (smu)->funcs->get_fan_speed_percent((smu), (speed)) : 0)
 #define smu_set_fan_speed_percent(smu, speed) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index d8917b2..aaa1bd8 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1833,6 +1833,36 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
 	return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
 }
 
+static int
+smu_v11_0_set_fan_control_mode(struct smu_context *smu,
+			       uint32_t mode)
+{
+	int ret = 0;
+	bool start = 1;
+	bool stop  = 0;
+
+	switch (mode) {
+	case AMD_FAN_CTRL_NONE:
+		ret = smu_v11_0_set_fan_speed_percent(smu, 100);
+		break;
+	case AMD_FAN_CTRL_MANUAL:
+		ret = smu_v11_0_smc_fan_control(smu, stop);
+		break;
+	case AMD_FAN_CTRL_AUTO:
+		ret = smu_v11_0_smc_fan_control(smu, start);
+		break;
+	default:
+		break;
+	}
+
+	if (ret) {
+		pr_err("[%s]Set fan control mode failed!");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
 static const struct smu_funcs smu_v11_0_funcs = {
 	.init_microcode = smu_v11_0_init_microcode,
 	.load_microcode = smu_v11_0_load_microcode,
@@ -1885,6 +1915,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
 	.dpm_set_vce_enable = smu_v11_0_dpm_set_vce_enable,
 	.get_current_rpm = smu_v11_0_get_current_rpm,
 	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
 	.get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
 	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
 };
-- 
2.7.4

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[PATCH 08/26] drm/amd/powerplay: implement fan1_enable hwmon interface for SMU11 (v2)

[Huang Rui]

From: Chengming Gui <Jack.Gui@amd.com>

set the fan1_enable hwmon interface to call
smu_get_fan_control_mode and smu_set_fan_control_mode.

v2: fix print value.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c    | 23 +++++++++++++++--------
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c |  2 +-
 2 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index ac991f9..9413c39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1635,12 +1635,15 @@ static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
 	struct amdgpu_device *adev = dev_get_drvdata(dev);
 	u32 pwm_mode = 0;
 
-	if (!adev->powerplay.pp_funcs->get_fan_control_mode)
-		return -EINVAL;
-
-	pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+	if (is_support_sw_smu(adev)) {
+		pwm_mode = smu_get_fan_control_mode(&adev->smu);
+	} else {
+		if (!adev->powerplay.pp_funcs->get_fan_control_mode)
+			return -EINVAL;
 
-	return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
+		pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+	}
+		return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
 }
 
 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
@@ -1658,8 +1661,6 @@ static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
 	     (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return -EINVAL;
 
-	if (!adev->powerplay.pp_funcs->set_fan_control_mode)
-		return -EINVAL;
 
 	err = kstrtoint(buf, 10, &value);
 	if (err)
@@ -1672,7 +1673,13 @@ static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
 	else
 		return -EINVAL;
 
-	amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
+	if (is_support_sw_smu(adev)) {
+		smu_set_fan_control_mode(&adev->smu, pwm_mode);
+	} else {
+		if (!adev->powerplay.pp_funcs->set_fan_control_mode)
+			return -EINVAL;
+		amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
+	}
 
 	return count;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index aaa1bd8..c0bc4f4 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1856,7 +1856,7 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
 	}
 
 	if (ret) {
-		pr_err("[%s]Set fan control mode failed!");
+		pr_err("[%s]Set fan control mode failed!", __func__);
 		return -EINVAL;
 	}
 
-- 
2.7.4

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[PATCH 09/26] drm/amd/powerplay: set fan target interface for hwmon

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

Add fan1_target set interface to set fan speed for hwmon.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 12 ++++++++--
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  3 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 31 ++++++++++++++++++++++++++
 3 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 9413c39..6bc80c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1606,7 +1606,11 @@ static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
 	u32 value;
 	u32 pwm_mode;
 
-	pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+	if (is_support_sw_smu(adev))
+		pwm_mode = smu_get_fan_control_mode(&adev->smu);
+	else
+		pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+
 	if (pwm_mode != AMD_FAN_CTRL_MANUAL)
 		return -ENODATA;
 
@@ -1619,7 +1623,11 @@ static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
 	if (err)
 		return err;
 
-	if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
+	if (is_support_sw_smu(adev)) {
+		err = smu_set_fan_speed_rpm(&adev->smu, value);
+		if (err)
+			return err;
+	} else if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
 		err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
 		if (err)
 			return err;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ef2b807..8464fdb 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -536,6 +536,7 @@ struct smu_funcs
 	int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
 	int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
 	int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
+	int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
 };
 
 #define smu_init_microcode(smu) \
@@ -588,6 +589,8 @@ struct smu_funcs
 	((smu)->funcs->update_od8_settings ? (smu)->funcs->update_od8_settings((smu), (index), (value)) : 0)
 #define smu_get_current_rpm(smu, speed) \
 	((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu), (speed)) : 0)
+#define smu_set_fan_speed_rpm(smu, speed) \
+	((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
 #define smu_send_smc_msg(smu, msg) \
 	((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
 #define smu_send_smc_msg_with_param(smu, msg, param) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index c0bc4f4..4864de4 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1863,6 +1863,36 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
 	return ret;
 }
 
+static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+				       uint32_t speed)
+{
+	struct amdgpu_device *adev = smu->adev;
+	int ret;
+	uint32_t tach_period, crystal_clock_freq;
+	bool stop = 0;
+
+	if (!speed)
+		return -EINVAL;
+
+	mutex_lock(&(smu->mutex));
+	ret = smu_v11_0_smc_fan_control(smu, stop);
+	if (ret)
+		goto set_fan_speed_rpm_failed;
+
+	crystal_clock_freq = amdgpu_asic_get_xclk(adev);
+	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
+	WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
+		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
+				   CG_TACH_CTRL, TARGET_PERIOD,
+				   tach_period));
+
+	ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
+
+set_fan_speed_rpm_failed:
+	mutex_unlock(&(smu->mutex));
+	return ret;
+}
+
 static const struct smu_funcs smu_v11_0_funcs = {
 	.init_microcode = smu_v11_0_init_microcode,
 	.load_microcode = smu_v11_0_load_microcode,
@@ -1918,6 +1948,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
 	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
 	.get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
 	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+	.set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
 };
 
 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
-- 
2.7.4

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[PATCH 10/26] drm/amd/powerplay: get eclk/vclk/dclk for smu11

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

Get eclk, vclk and dclk info from vbios when hw init for smu11.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  3 ++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 42 ++++++++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8464fdb..00ef6f1 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -282,6 +282,9 @@ struct smu_bios_boot_up_values
 	uint32_t			uclk;
 	uint32_t			socclk;
 	uint32_t			dcefclk;
+	uint32_t			eclk;
+	uint32_t			vclk;
+	uint32_t			dclk;
 	uint16_t			vddc;
 	uint16_t			vddci;
 	uint16_t			mvddc;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 4864de4..2932734 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -462,6 +462,48 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 	smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 
+	memset(&input, 0, sizeof(input));
+	input.clk_id = SMU11_SYSPLL0_ECLK_ID;
+	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+					    getsmuclockinfo);
+
+	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+					(uint32_t *)&input);
+	if (ret)
+		return -EINVAL;
+
+	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+	smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+
+	memset(&input, 0, sizeof(input));
+	input.clk_id = SMU11_SYSPLL0_VCLK_ID;
+	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+					    getsmuclockinfo);
+
+	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+					(uint32_t *)&input);
+	if (ret)
+		return -EINVAL;
+
+	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+	smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+
+	memset(&input, 0, sizeof(input));
+	input.clk_id = SMU11_SYSPLL0_DCLK_ID;
+	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+					    getsmuclockinfo);
+
+	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+					(uint32_t *)&input);
+	if (ret)
+		return -EINVAL;
+
+	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+	smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+
 	return 0;
 }
 
-- 
2.7.4

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[PATCH 11/26] drm/amd/powerplay: set dpm table of vclk/dclk/eclk for smu11 (v2)

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

Set default dpm table fo vclk, dclk and eclk.
Open clk adjust rules for vclk, dclk.

v2: Open clk adjust rules for eclk.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 300462a..6aa94ee 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -542,11 +542,10 @@ static int vega20_set_default_dpm_table(struct smu_context *smu)
 	}
 	vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 
-#if 0
 	/* eclk */
 	single_dpm_table = &(dpm_table->eclk_table);
 
-	if (feature->fea_enabled[FEATURE_DPM_VCE_BIT]) {
+	if (smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT)) {
 		ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
 		if (ret) {
 			pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
@@ -554,14 +553,14 @@ static int vega20_set_default_dpm_table(struct smu_context *smu)
 		}
 	} else {
 		single_dpm_table->count = 1;
-		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclock / 100;
+		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
 	}
 	vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 
 	/* vclk */
 	single_dpm_table = &(dpm_table->vclk_table);
 
-	if (feature->fea_enabled[FEATURE_DPM_UVD_BIT]) {
+	if (smu_feature_is_enabled(smu, FEATURE_DPM_UVD_BIT)) {
 		ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
 		if (ret) {
 			pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
@@ -569,14 +568,14 @@ static int vega20_set_default_dpm_table(struct smu_context *smu)
 		}
 	} else {
 		single_dpm_table->count = 1;
-		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclock / 100;
+		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 	}
 	vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 
 	/* dclk */
 	single_dpm_table = &(dpm_table->dclk_table);
 
-	if (feature->fea_enabled[FEATURE_DPM_UVD_BIT]) {
+	if (smu_feature_is_enabled(smu, FEATURE_DPM_UVD_BIT)) {
 		ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
 		if (ret) {
 			pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
@@ -584,10 +583,9 @@ static int vega20_set_default_dpm_table(struct smu_context *smu)
 		}
 	} else {
 		single_dpm_table->count = 1;
-		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclock / 100;
+		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 	}
 	vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
-#endif
 
 	/* dcefclk */
 	single_dpm_table = &(dpm_table->dcef_table);
@@ -1483,7 +1481,6 @@ static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
 	if (smu->display_config->nb_pstate_switch_disable)
 		dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
 
-#if 0
 	/* vclk */
 	dpm_table = &(dpm_ctx->vclk_table);
 	dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
@@ -1517,7 +1514,6 @@ static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
 		}
-#endif
 
 	/* socclk */
 	dpm_table = &(dpm_ctx->soc_table);
@@ -1536,7 +1532,6 @@ static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
 		}
 
-#if 0
 	/* eclk */
 	dpm_table = &(dpm_ctx->eclk_table);
 	dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
@@ -1553,7 +1548,6 @@ static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
 		}
-#endif
 	return 0;
 }
 
-- 
2.7.4

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[PATCH 12/26] drm/amd/powerplay: add smu_late_init for SMU11.

[Huang Rui]

From: Chengming Gui <Jack.Gui@amd.com>

add smu_late_init to complete smu init sequence for SMU11.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 60491d1..9cb45fe 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -310,6 +310,19 @@ static int smu_early_init(void *handle)
 	return smu_set_funcs(adev);
 }
 
+static int smu_late_init(void *handle)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	struct smu_context *smu = &adev->smu;
+	mutex_lock(&smu->mutex);
+	smu_handle_task(&adev->smu,
+			smu->smu_dpm.dpm_level,
+			AMD_PP_TASK_COMPLETE_INIT);
+	mutex_unlock(&smu->mutex);
+
+	return 0;
+}
+
 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 			    uint16_t *size, uint8_t *frev, uint8_t *crev,
 			    uint8_t **addr)
@@ -1181,7 +1194,7 @@ int smu_handle_task(struct smu_context *smu,
 const struct amd_ip_funcs smu_ip_funcs = {
 	.name = "smu",
 	.early_init = smu_early_init,
-	.late_init = NULL,
+	.late_init = smu_late_init,
 	.sw_init = smu_sw_init,
 	.sw_fini = smu_sw_fini,
 	.hw_init = smu_hw_init,
-- 
2.7.4

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[PATCH 13/26] drm/amd/powerplay: add limit of pp_feature for smu

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

Move pp_feature from the struct of amd_powerplay to amdgpu_device.
Add pp_feature limit for overdrive interface.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h            | 4 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c     | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c        | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 6 ++++--
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c            | 2 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c             | 2 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 2 +-
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 4 ++++
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
 9 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d1c02fa..f96b6e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -706,7 +706,6 @@ enum amd_hw_ip_block_type {
 struct amd_powerplay {
 	void *pp_handle;
 	const struct amd_pm_funcs *pp_funcs;
-	uint32_t pp_feature;
 };
 
 #define AMDGPU_RESET_MAGIC_NUM 64
@@ -842,6 +841,9 @@ struct amdgpu_device {
 	/* interrupts */
 	struct amdgpu_irq		irq;
 
+	/* powerplay feature */
+	uint32_t pp_feature;
+
 	/* powerplay */
 	struct amd_powerplay		powerplay;
 	bool				pp_force_state_enabled;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fcab1fe..c8fe5e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1506,7 +1506,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
 			return -EAGAIN;
 	}
 
-	adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
+	adev->pp_feature = amdgpu_pp_feature_mask;
 
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 		if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 97a60da..bcc732d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -390,7 +390,7 @@ void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev)
 
 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 {
-	if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK))
+	if (!(adev->pp_feature & PP_GFXOFF_MASK))
 		return;
 
 	if (!adev->powerplay.pp_funcs || !adev->powerplay.pp_funcs->set_powergating_by_smu)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 6bc80c1..fe1b0c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2558,7 +2558,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 				"pp_power_profile_mode\n");
 		return ret;
 	}
-	if (is_support_sw_smu(adev) || hwmgr->od_enabled) {
+	if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
+	    (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
 		ret = device_create_file(adev->dev,
 				&dev_attr_pp_od_clk_voltage);
 		if (ret) {
@@ -2634,7 +2635,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 	device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
 	device_remove_file(adev->dev,
 			&dev_attr_pp_power_profile_mode);
-	if (hwmgr->od_enabled)
+	if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
+	    (!is_support_sw_smu(adev) && hwmgr->od_enabled))
 		device_remove_file(adev->dev,
 				&dev_attr_pp_od_clk_voltage);
 	device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 0c9a2c0..9022f42 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2824,7 +2824,7 @@ static int kv_dpm_init(struct amdgpu_device *adev)
 		pi->caps_tcp_ramping = true;
 	}
 
-	if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
+	if (adev->pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 		pi->caps_sclk_ds = true;
 	else
 		pi->caps_sclk_ds = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 9f6ce6e..c296f6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -933,7 +933,7 @@ static int soc15_common_early_init(void *handle)
 			adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
 		}
 
-		if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
+		if (adev->pp_feature & PP_GFXOFF_MASK)
 			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
 				AMD_PG_SUPPORT_CP |
 				AMD_PG_SUPPORT_RLC_SMU_HS;
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 3f73f7c..ea5689a 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -53,7 +53,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
 	mutex_init(&hwmgr->smu_lock);
 	hwmgr->chip_family = adev->family;
 	hwmgr->chip_id = adev->asic_type;
-	hwmgr->feature_mask = adev->powerplay.pp_feature;
+	hwmgr->feature_mask = adev->pp_feature;
 	hwmgr->display_config = &adev->pm.pm_display_cfg;
 	adev->powerplay.pp_handle = hwmgr;
 	adev->powerplay.pp_funcs = &pp_dpm_funcs;
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 9cb45fe..fa0af71 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -290,6 +290,9 @@ static int smu_set_funcs(struct amdgpu_device *adev)
 
 	switch (adev->asic_type) {
 	case CHIP_VEGA20:
+		smu->feature_mask &= ~PP_GFXOFF_MASK;
+		if (smu->feature_mask & PP_OVERDRIVE_MASK)
+			smu->od_enabled = true;
 		smu_v11_0_set_smu_funcs(smu);
 		break;
 	default:
@@ -306,6 +309,7 @@ static int smu_early_init(void *handle)
 
 	smu->adev = adev;
 	mutex_init(&smu->mutex);
+	smu->feature_mask = adev->pp_feature;
 
 	return smu_set_funcs(adev);
 }
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 00ef6f1..8c7eac9 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -384,6 +384,7 @@ struct smu_context
 	uint32_t pstate_sclk;
 	uint32_t pstate_mclk;
 
+	bool od_enabled;
 	uint32_t power_limit;
 	uint32_t default_power_limit;
 
@@ -399,6 +400,8 @@ struct smu_context
 	uint32_t workload_setting[WORKLOAD_POLICY_MAX];
 	uint32_t power_profile_mode;
 	uint32_t default_power_profile_mode;
+
+	uint32_t feature_mask;
 };
 
 struct pptable_funcs {
-- 
2.7.4

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[PATCH 14/26] drm/amd/powerplay: add od condition for power limit

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

Add condition to judge whether overdrive is enabled and correct power
limit value for overdrive used by power limit interface.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  1 +
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 20 ++++++++++++++++++--
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c     |  1 +
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8c7eac9..594965c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -307,6 +307,7 @@ struct smu_table_context
 	struct smu_table		memory_pool;
 	uint16_t                        software_shutdown_temp;
 	uint8_t                         thermal_controller_type;
+	uint16_t			TDPODLimit;
 
 	uint8_t				*od_feature_capabilities;
 	uint32_t			*od_settings_max;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 2932734..5531cd1 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -924,6 +924,10 @@ static int smu_v11_0_get_power_limit(struct smu_context *smu,
 	if (get_default) {
 		mutex_lock(&smu->mutex);
 		*limit = smu->default_power_limit;
+		if (smu->od_enabled) {
+			*limit *= (100 + smu->smu_table.TDPODLimit);
+			*limit /= 100;
+		}
 		mutex_unlock(&smu->mutex);
 	} else {
 			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
@@ -941,9 +945,21 @@ static int smu_v11_0_get_power_limit(struct smu_context *smu,
 
 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
 {
+	uint32_t max_power_limit;
 	int ret = 0;
-		if (smu_feature_is_enabled(smu, FEATURE_PPT_BIT))
-			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
+
+	if (n == 0)
+		n = smu->default_power_limit;
+
+	max_power_limit = smu->default_power_limit;
+
+	if (smu->od_enabled) {
+		max_power_limit *= (100 + smu->smu_table.TDPODLimit);
+		max_power_limit /= 100;
+	}
+
+	if (smu_feature_is_enabled(smu, FEATURE_PPT_BIT))
+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
 	if (ret) {
 		pr_err("[%s] Set power limit Failed!", __func__);
 		return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 6aa94ee..f97b60a 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -265,6 +265,7 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
 
 	table_context->software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
 	table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
+	table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
 
 	ret = vega20_setup_od8_information(smu);
 
-- 
2.7.4

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[PATCH 15/26] drm/amd/powerplay: add is_dpm_running for SMU11

[Huang Rui]

From: Chengming Gui <Jack.Gui@amd.com>

add is_dpm_running function to support smu s3 case.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  4 ++++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 12 ++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 594965c..dde3c93 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -337,6 +337,7 @@ struct smu_power_context {
 };
 
 
+#define SMC_DPM_FEATURES 0x30F
 #define SMU_FEATURE_MAX	(64)
 struct smu_feature
 {
@@ -487,6 +488,7 @@ struct smu_funcs
 	int (*init_display)(struct smu_context *smu);
 	int (*set_allowed_mask)(struct smu_context *smu);
 	int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
+	bool (*is_dpm_running)(struct smu_context *smu);
 	int (*enable_all_mask)(struct smu_context *smu);
 	int (*disable_all_mask)(struct smu_context *smu);
 	int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
@@ -612,6 +614,8 @@ struct smu_funcs
 	((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
 #define smu_feature_get_enabled_mask(smu, mask, num) \
 	((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
+#define smu_is_dpm_running(smu) \
+	((smu)->funcs->is_dpm_running? (smu)->funcs->is_dpm_running((smu)) : 0)
 #define smu_feature_enable_all(smu) \
 	((smu)->funcs->enable_all_mask? (smu)->funcs->enable_all_mask((smu)) : 0)
 #define smu_feature_disable_all(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 5531cd1..ea5de6e 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -750,6 +750,17 @@ static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 	return ret;
 }
 
+static bool smu_v11_0_is_dpm_running(struct smu_context *smu)
+{
+	int ret = 0;
+	uint32_t feature_mask[2];
+	unsigned long feature_enabled;
+	ret = smu_v11_0_get_enabled_mask(smu, feature_mask, 2);
+	feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
+			   ((uint64_t)feature_mask[1] << 32));
+	return !!(feature_enabled & SMC_DPM_FEATURES);
+}
+
 static int smu_v11_0_enable_all_mask(struct smu_context *smu)
 {
 	struct smu_feature *feature = &smu->smu_feature;
@@ -1977,6 +1988,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
 	.init_display = smu_v11_0_init_display,
 	.set_allowed_mask = smu_v11_0_set_allowed_mask,
 	.get_enabled_mask = smu_v11_0_get_enabled_mask,
+	.is_dpm_running = smu_v11_0_is_dpm_running,
 	.enable_all_mask = smu_v11_0_enable_all_mask,
 	.disable_all_mask = smu_v11_0_disable_all_mask,
 	.update_feature_enable_state = smu_v11_0_update_feature_enable_state,
-- 
2.7.4

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[PATCH 16/26] drm/amd/powerplay: add suspend and resume function for smu

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

Functional the function of smu suspend and resume.
Modified the function of smu_smc_table_hw_init to make it useful for smu
resume.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 156 ++++++++++++-------------
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |   7 +-
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c      |  27 +++--
 3 files changed, 93 insertions(+), 97 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index fa0af71..f6e659e 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -533,7 +533,8 @@ static int smu_fini_fb_allocations(struct smu_context *smu)
 	return 0;
 }
 
-static int smu_smc_table_hw_init(struct smu_context *smu)
+static int smu_smc_table_hw_init(struct smu_context *smu,
+				 bool initialize)
 {
 	int ret;
 
@@ -545,54 +546,56 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
 	if (ret)
 		return ret;
 
-	ret = smu_read_pptable_from_vbios(smu);
-	if (ret)
-		return ret;
+	if (initialize) {
+		ret = smu_read_pptable_from_vbios(smu);
+		if (ret)
+			return ret;
 
-	/* get boot_values from vbios to set revision, gfxclk, and etc. */
-	ret = smu_get_vbios_bootup_values(smu);
-	if (ret)
-		return ret;
+		/* get boot_values from vbios to set revision, gfxclk, and etc. */
+		ret = smu_get_vbios_bootup_values(smu);
+		if (ret)
+			return ret;
 
-	ret = smu_get_clk_info_from_vbios(smu);
-	if (ret)
-		return ret;
+		ret = smu_get_clk_info_from_vbios(smu);
+		if (ret)
+			return ret;
 
-	/*
-	 * check if the format_revision in vbios is up to pptable header
-	 * version, and the structure size is not 0.
-	 */
-	ret = smu_get_clk_info_from_vbios(smu);
-	if (ret)
-		return ret;
+		/*
+		 * check if the format_revision in vbios is up to pptable header
+		 * version, and the structure size is not 0.
+		 */
+		ret = smu_get_clk_info_from_vbios(smu);
+		if (ret)
+			return ret;
 
-	ret = smu_check_pptable(smu);
-	if (ret)
-		return ret;
+		ret = smu_check_pptable(smu);
+		if (ret)
+			return ret;
 
-	/*
-	 * allocate vram bos to store smc table contents.
-	 */
-	ret = smu_init_fb_allocations(smu);
-	if (ret)
-		return ret;
+		/*
+		 * allocate vram bos to store smc table contents.
+		 */
+		ret = smu_init_fb_allocations(smu);
+		if (ret)
+			return ret;
 
-	/*
-	 * Parse pptable format and fill PPTable_t smc_pptable to
-	 * smu_table_context structure. And read the smc_dpm_table from vbios,
-	 * then fill it into smc_pptable.
-	 */
-	ret = smu_parse_pptable(smu);
-	if (ret)
-		return ret;
+		/*
+		 * Parse pptable format and fill PPTable_t smc_pptable to
+		 * smu_table_context structure. And read the smc_dpm_table from vbios,
+		 * then fill it into smc_pptable.
+		 */
+		ret = smu_parse_pptable(smu);
+		if (ret)
+			return ret;
 
-	/*
-	 * Send msg GetDriverIfVersion to check if the return value is equal
-	 * with DRIVER_IF_VERSION of smc header.
-	 */
-	ret = smu_check_fw_version(smu);
-	if (ret)
-		return ret;
+		/*
+		 * Send msg GetDriverIfVersion to check if the return value is equal
+		 * with DRIVER_IF_VERSION of smc header.
+		 */
+		ret = smu_check_fw_version(smu);
+		if (ret)
+			return ret;
+	}
 
 	/*
 	 * Copy pptable bo in the vram to smc with SMU MSGs such as
@@ -628,25 +631,29 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
 	 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 	 * type of clks.
 	 */
-	ret = smu_populate_smc_pptable(smu);
-	if (ret)
-		return ret;
+	if (initialize) {
+		ret = smu_populate_smc_pptable(smu);
+		if (ret)
+			return ret;
 
-	ret = smu_init_max_sustainable_clocks(smu);
-	if (ret)
-		return ret;
+		ret = smu_init_max_sustainable_clocks(smu);
+		if (ret)
+			return ret;
+	}
 
-	ret = smu_set_od8_default_settings(smu);
+	ret = smu_set_od8_default_settings(smu, initialize);
 	if (ret)
 		return ret;
 
-	ret = smu_populate_umd_state_clk(smu);
-	if (ret)
-		return ret;
+	if (initialize) {
+		ret = smu_populate_umd_state_clk(smu);
+		if (ret)
+			return ret;
 
-	ret = smu_get_power_limit(smu, &smu->default_power_limit, false);
-	if (ret)
-		return ret;
+		ret = smu_get_power_limit(smu, &smu->default_power_limit, false);
+		if (ret)
+			return ret;
+	}
 
 	/*
 	 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
@@ -718,6 +725,7 @@ static int smu_free_memory_pool(struct smu_context *smu)
 
 	return ret;
 }
+
 static int smu_hw_init(void *handle)
 {
 	int ret;
@@ -745,7 +753,7 @@ static int smu_hw_init(void *handle)
 	if (ret)
 		goto failed;
 
-	ret = smu_smc_table_hw_init(smu);
+	ret = smu_smc_table_hw_init(smu, true);
 	if (ret)
 		goto failed;
 
@@ -838,11 +846,19 @@ int smu_reset(struct smu_context *smu)
 
 static int smu_suspend(void *handle)
 {
+	int ret;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	struct smu_context *smu = &adev->smu;
 
 	if (!is_support_sw_smu(adev))
 		return -EINVAL;
 
+	ret = smu_feature_disable_all(smu);
+	if (ret)
+		return ret;
+
+	smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
+
 	return 0;
 }
 
@@ -857,37 +873,13 @@ static int smu_resume(void *handle)
 
 	pr_info("SMU is resuming...\n");
 
-	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
-		ret = smu_load_microcode(smu);
-		if (ret)
-			return ret;
-	}
-
-	ret = smu_check_fw_status(smu);
-	if (ret) {
-		pr_err("SMC firmware status is not correct\n");
-		return ret;
-	}
-
 	mutex_lock(&smu->mutex);
 
-	ret = smu_set_tool_table_location(smu);
-	if (ret)
-		goto failed;
-
-	ret = smu_write_pptable(smu);
+	ret = smu_smc_table_hw_init(smu, false);
 	if (ret)
 		goto failed;
 
-	ret = smu_write_watermarks_table(smu);
-	if (ret)
-		goto failed;
-
-	ret = smu_set_last_dcef_min_deep_sleep_clk(smu);
-	if (ret)
-		goto failed;
-
-	ret = smu_system_features_control(smu, true);
+	ret = smu_start_thermal_control(smu);
 	if (ret)
 		goto failed;
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index dde3c93..87d3320 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -523,7 +523,8 @@ struct smu_funcs
 	int (*notify_smu_enable_pwe)(struct smu_context *smu);
 	int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
 					       struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
-	int (*set_od8_default_settings)(struct smu_context *smu);
+	int (*set_od8_default_settings)(struct smu_context *smu,
+					bool initialize);
 	int (*get_activity_monitor_coeff)(struct smu_context *smu,
 				      uint8_t *table,
 				      uint16_t workload_type);
@@ -592,8 +593,8 @@ struct smu_funcs
 	((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
 #define smu_init_max_sustainable_clocks(smu) \
 	((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
-#define smu_set_od8_default_settings(smu) \
-	((smu)->funcs->set_od8_default_settings ? (smu)->funcs->set_od8_default_settings((smu)) : 0)
+#define smu_set_od8_default_settings(smu, initialize) \
+	((smu)->funcs->set_od8_default_settings ? (smu)->funcs->set_od8_default_settings((smu), (initialize)) : 0)
 #define smu_update_od8_settings(smu, index, value) \
 	((smu)->funcs->update_od8_settings ? (smu)->funcs->update_od8_settings((smu), (index), (value)) : 0)
 #define smu_get_current_rpm(smu, speed) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index ea5de6e..3faf8fa 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1437,26 +1437,29 @@ static uint32_t smu_v11_0_dpm_get_mclk(struct smu_context *smu, bool low)
 	return (mem_clk * 100);
 }
 
-static int smu_v11_0_set_od8_default_settings(struct smu_context *smu)
+static int smu_v11_0_set_od8_default_settings(struct smu_context *smu,
+					      bool initialize)
 {
 	struct smu_table_context *table_context = &smu->smu_table;
 	int ret;
 
-	if (table_context->overdrive_table)
-		 return -EINVAL;
+	if (initialize) {
+		if (table_context->overdrive_table)
+			return -EINVAL;
 
-	table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
+		table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
 
-	if (!table_context->overdrive_table)
-		return -ENOMEM;
+		if (!table_context->overdrive_table)
+			return -ENOMEM;
 
-	ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, false);
-	if (ret) {
-		pr_err("Failed to export over drive table!\n");
-		return ret;
-	}
+		ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, false);
+		if (ret) {
+			pr_err("Failed to export over drive table!\n");
+			return ret;
+		}
 
-	smu_set_default_od8_settings(smu);
+		smu_set_default_od8_settings(smu);
+	}
 
 	ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, true);
 	if (ret) {
-- 
2.7.4

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[PATCH 17/26] drm/amd/powerplay: add condition for smc table hw init

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

Smc table hw init should be skipped for suspend/resume when dpm running.
Unified feature enable and disable function into smu_system_features_control.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 10 +++++++--
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  6 ------
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 30 +++++---------------------
 3 files changed, 13 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f6e659e..a5c672a 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -536,8 +536,14 @@ static int smu_fini_fb_allocations(struct smu_context *smu)
 static int smu_smc_table_hw_init(struct smu_context *smu,
 				 bool initialize)
 {
+	struct amdgpu_device *adev = smu->adev;
 	int ret;
 
+	if (smu_is_dpm_running(smu) && adev->in_suspend) {
+		pr_info("dpm has been enabled\n");
+		return 0;
+	}
+
 	ret = smu_init_display(smu);
 	if (ret)
 		return ret;
@@ -610,7 +616,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
 	if (ret)
 		return ret;
 
-	ret = smu_feature_enable_all(smu);
+	ret = smu_system_features_control(smu, true);
 	if (ret)
 		return ret;
 
@@ -853,7 +859,7 @@ static int smu_suspend(void *handle)
 	if (!is_support_sw_smu(adev))
 		return -EINVAL;
 
-	ret = smu_feature_disable_all(smu);
+	ret = smu_system_features_control(smu, false);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 87d3320..b7313a9 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -489,8 +489,6 @@ struct smu_funcs
 	int (*set_allowed_mask)(struct smu_context *smu);
 	int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
 	bool (*is_dpm_running)(struct smu_context *smu);
-	int (*enable_all_mask)(struct smu_context *smu);
-	int (*disable_all_mask)(struct smu_context *smu);
 	int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
 	int (*notify_display_change)(struct smu_context *smu);
 	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
@@ -617,10 +615,6 @@ struct smu_funcs
 	((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
 #define smu_is_dpm_running(smu) \
 	((smu)->funcs->is_dpm_running? (smu)->funcs->is_dpm_running((smu)) : 0)
-#define smu_feature_enable_all(smu) \
-	((smu)->funcs->enable_all_mask? (smu)->funcs->enable_all_mask((smu)) : 0)
-#define smu_feature_disable_all(smu) \
-	((smu)->funcs->disable_all_mask? (smu)->funcs->disable_all_mask((smu)) : 0)
 #define smu_feature_update_enable_state(smu, feature_id, enabled) \
 	((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
 #define smu_notify_display_change(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 3faf8fa..ffd71aa 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -761,34 +761,15 @@ static bool smu_v11_0_is_dpm_running(struct smu_context *smu)
 	return !!(feature_enabled & SMC_DPM_FEATURES);
 }
 
-static int smu_v11_0_enable_all_mask(struct smu_context *smu)
+static int smu_v11_0_system_features_control(struct smu_context *smu,
+					     bool en)
 {
 	struct smu_feature *feature = &smu->smu_feature;
 	uint32_t feature_mask[2];
 	int ret = 0;
 
-	ret = smu_send_smc_msg(smu, SMU_MSG_EnableAllSmuFeatures);
-	if (ret)
-		return ret;
-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-	if (ret)
-		return ret;
-
-	bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
-		    feature->feature_num);
-	bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
-		    feature->feature_num);
-
-	return ret;
-}
-
-static int smu_v11_0_disable_all_mask(struct smu_context *smu)
-{
-	struct smu_feature *feature = &smu->smu_feature;
-	uint32_t feature_mask[2];
-	int ret = 0;
-
-	ret = smu_send_smc_msg(smu, SMU_MSG_DisableAllSmuFeatures);
+	ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
+				     SMU_MSG_DisableAllSmuFeatures));
 	if (ret)
 		return ret;
 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
@@ -1992,8 +1973,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
 	.set_allowed_mask = smu_v11_0_set_allowed_mask,
 	.get_enabled_mask = smu_v11_0_get_enabled_mask,
 	.is_dpm_running = smu_v11_0_is_dpm_running,
-	.enable_all_mask = smu_v11_0_enable_all_mask,
-	.disable_all_mask = smu_v11_0_disable_all_mask,
+	.system_features_control = smu_v11_0_system_features_control,
 	.update_feature_enable_state = smu_v11_0_update_feature_enable_state,
 	.notify_display_change = smu_v11_0_notify_display_change,
 	.get_power_limit = smu_v11_0_get_power_limit,
-- 
2.7.4

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[PATCH 18/26] drm/amd/powerplay: support sysfs to get socclk, fclk, dcefclk

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

Add sys interface to get socclk, fclk and dcefclk for smu.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Gui Chengming <Jack.Gui@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 12 +++++--
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 56 ++++++++++++++++++++++++++++++
 2 files changed, 65 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index fe1b0c4..2a55d8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -906,7 +906,9 @@ static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct amdgpu_device *adev = ddev->dev_private;
 
-	if (adev->powerplay.pp_funcs->print_clock_levels)
+	if (is_support_sw_smu(adev))
+		return smu_print_clk_levels(&adev->smu, PP_SOCCLK, buf);
+	else if (adev->powerplay.pp_funcs->print_clock_levels)
 		return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 	else
 		return snprintf(buf, PAGE_SIZE, "\n");
@@ -942,7 +944,9 @@ static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct amdgpu_device *adev = ddev->dev_private;
 
-	if (adev->powerplay.pp_funcs->print_clock_levels)
+	if (is_support_sw_smu(adev))
+		return smu_print_clk_levels(&adev->smu, PP_FCLK, buf);
+	else if (adev->powerplay.pp_funcs->print_clock_levels)
 		return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
 	else
 		return snprintf(buf, PAGE_SIZE, "\n");
@@ -978,7 +982,9 @@ static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct amdgpu_device *adev = ddev->dev_private;
 
-	if (adev->powerplay.pp_funcs->print_clock_levels)
+	if (is_support_sw_smu(adev))
+		return smu_print_clk_levels(&adev->smu, PP_DCEFCLK, buf);
+	else if (adev->powerplay.pp_funcs->print_clock_levels)
 		return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
 	else
 		return snprintf(buf, PAGE_SIZE, "\n");
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index f97b60a..53b2b5f 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -774,6 +774,62 @@ static int vega20_print_clk_levels(struct smu_context *smu,
 				? "*" : "");
 		break;
 
+	case PP_SOCCLK:
+		ret = smu_get_current_clk_freq(smu, PPCLK_SOCCLK, &now);
+		if (ret) {
+			pr_err("Attempt to get current socclk Failed!");
+			return ret;
+		}
+
+		single_dpm_table = &(dpm_table->soc_table);
+		ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
+		if (ret) {
+			pr_err("Attempt to get socclk levels Failed!");
+			return ret;
+		}
+
+		for (i = 0; i < clocks.num_levels; i++)
+			size += sprintf(buf + size, "%d: %uMhz %s\n",
+				i, clocks.data[i].clocks_in_khz / 1000,
+				(clocks.data[i].clocks_in_khz == now * 10)
+				? "*" : "");
+		break;
+
+	case PP_FCLK:
+		ret = smu_get_current_clk_freq(smu, PPCLK_FCLK, &now);
+		if (ret) {
+			pr_err("Attempt to get current fclk Failed!");
+			return ret;
+		}
+
+		single_dpm_table = &(dpm_table->fclk_table);
+		for (i = 0; i < single_dpm_table->count; i++)
+			size += sprintf(buf + size, "%d: %uMhz %s\n",
+				i, single_dpm_table->dpm_levels[i].value,
+				(single_dpm_table->dpm_levels[i].value == now / 100)
+				? "*" : "");
+		break;
+
+	case PP_DCEFCLK:
+		ret = smu_get_current_clk_freq(smu, PPCLK_DCEFCLK, &now);
+		if (ret) {
+			pr_err("Attempt to get current dcefclk Failed!");
+			return ret;
+		}
+
+		single_dpm_table = &(dpm_table->dcef_table);
+		ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
+		if (ret) {
+			pr_err("Attempt to get dcefclk levels Failed!");
+			return ret;
+		}
+
+		for (i = 0; i < clocks.num_levels; i++)
+			size += sprintf(buf + size, "%d: %uMhz %s\n",
+				i, clocks.data[i].clocks_in_khz / 1000,
+				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
+		break;
+
 	case PP_PCIE:
 		break;
 
-- 
2.7.4

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[PATCH 19/26] drm/amd/powerplay: support sysfs to set socclk, fclk, dcefclk

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

Add sys interface to set socclk, fclk and dcefclk for smu.
Add feature_mask parameter for smu_upload_dpm_level as socclk, fclk and
dcefclk have dependency, without feature_mask to point out specific clk
will make it fail to set some clk.
Fix the function of smu_unforce_dpm_levels.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Gui Chengming <Jack.Gui@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         |  12 +-
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     |  19 ---
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  10 +-
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c     | 195 +++++++++++++++++++++++--
 4 files changed, 201 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 2a55d8b..771146f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -928,7 +928,9 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 	if (ret)
 		return ret;
 
-	if (adev->powerplay.pp_funcs->force_clock_level)
+	if (is_support_sw_smu(adev))
+		ret = smu_force_clk_levels(&adev->smu, PP_SOCCLK, mask);
+	else if (adev->powerplay.pp_funcs->force_clock_level)
 		ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
 
 	if (ret)
@@ -966,7 +968,9 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
 	if (ret)
 		return ret;
 
-	if (adev->powerplay.pp_funcs->force_clock_level)
+	if (is_support_sw_smu(adev))
+		ret = smu_force_clk_levels(&adev->smu, PP_FCLK, mask);
+	else if (adev->powerplay.pp_funcs->force_clock_level)
 		ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
 
 	if (ret)
@@ -1004,7 +1008,9 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
 	if (ret)
 		return ret;
 
-	if (adev->powerplay.pp_funcs->force_clock_level)
+	if (is_support_sw_smu(adev))
+		ret = smu_force_clk_levels(&adev->smu, PP_DCEFCLK, mask);
+	else if (adev->powerplay.pp_funcs->force_clock_level)
 		ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
 
 	if (ret)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index a5c672a..118347c 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1066,25 +1066,6 @@ static int smu_enable_umd_pstate(void *handle,
 	return 0;
 }
 
-int smu_unforce_dpm_levels(struct smu_context *smu)
-{
-	int ret = 0;
-
-	ret = smu_upload_dpm_level(smu, false);
-	if (ret) {
-		pr_err("Failed to upload DPM Bootup Levels!");
-		return ret;
-	}
-
-	ret = smu_upload_dpm_level(smu, true);
-	if (ret) {
-		pr_err("Failed to upload DPM Max Levels!");
-		return ret;
-	}
-
-	return ret;
-}
-
 int smu_adjust_power_state_dynamic(struct smu_context *smu,
 				   enum amd_dpm_forced_level level,
 				   bool skip_display_settings)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index b7313a9..6ed4f58 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -450,7 +450,9 @@ struct pptable_funcs {
 	int (*apply_clocks_adjust_rules)(struct smu_context *smu);
 	int (*notify_smc_dispaly_config)(struct smu_context *smu);
 	int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
-	int (*upload_dpm_level)(struct smu_context *smu, bool max);
+	int (*unforce_dpm_levels)(struct smu_context *smu);
+	int (*upload_dpm_level)(struct smu_context *smu, bool max,
+				uint32_t feature_mask);
 	int (*get_profiling_clk_mask)(struct smu_context *smu,
 				      enum amd_dpm_forced_level level,
 				      uint32_t *sclk_mask,
@@ -671,8 +673,10 @@ struct smu_funcs
 	((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
 #define smu_force_dpm_limit_value(smu, highest) \
 	((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
-#define smu_upload_dpm_level(smu, max) \
-	((smu)->ppt_funcs->upload_dpm_level ? (smu)->ppt_funcs->upload_dpm_level((smu), (max)) : 0)
+#define smu_unforce_dpm_levels(smu) \
+	((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
+#define smu_upload_dpm_level(smu, max, feature_mask) \
+	((smu)->ppt_funcs->upload_dpm_level ? (smu)->ppt_funcs->upload_dpm_level((smu), (max), (feature_mask)) : 0)
 #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
 	((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
 #define smu_set_cpu_power_state(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 53b2b5f..e564948 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -932,7 +932,8 @@ static int vega20_print_clk_levels(struct smu_context *smu,
 	return size;
 }
 
-static int vega20_upload_dpm_level(struct smu_context *smu, bool max)
+static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
+				   uint32_t feature_mask)
 {
 	struct vega20_dpm_table *dpm_table;
 	struct vega20_single_dpm_table *single_dpm_table;
@@ -941,7 +942,8 @@ static int vega20_upload_dpm_level(struct smu_context *smu, bool max)
 
 	dpm_table = smu->smu_dpm.dpm_context;
 
-	if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
+	if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT) &&
+	    (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 		single_dpm_table = &(dpm_table->gfx_table);
 		freq = max ? single_dpm_table->dpm_state.soft_max_level :
 			single_dpm_table->dpm_state.soft_min_level;
@@ -955,7 +957,8 @@ static int vega20_upload_dpm_level(struct smu_context *smu, bool max)
 		}
 	}
 
-	if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
+	if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT) &&
+	    (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 		single_dpm_table = &(dpm_table->mem_table);
 		freq = max ? single_dpm_table->dpm_state.soft_max_level :
 			single_dpm_table->dpm_state.soft_min_level;
@@ -969,6 +972,51 @@ static int vega20_upload_dpm_level(struct smu_context *smu, bool max)
 		}
 	}
 
+	if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT) &&
+	    (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
+		single_dpm_table = &(dpm_table->soc_table);
+		freq = max ? single_dpm_table->dpm_state.soft_max_level :
+			single_dpm_table->dpm_state.soft_min_level;
+		ret = smu_send_smc_msg_with_param(smu,
+			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
+			(PPCLK_SOCCLK << 16) | (freq & 0xffff));
+		if (ret) {
+			pr_err("Failed to set soft %s socclk !\n",
+						max ? "max" : "min");
+			return ret;
+		}
+	}
+
+	if (smu_feature_is_enabled(smu, FEATURE_DPM_FCLK_BIT) &&
+	    (feature_mask & FEATURE_DPM_FCLK_MASK)) {
+		single_dpm_table = &(dpm_table->fclk_table);
+		freq = max ? single_dpm_table->dpm_state.soft_max_level :
+			single_dpm_table->dpm_state.soft_min_level;
+		ret = smu_send_smc_msg_with_param(smu,
+			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
+			(PPCLK_FCLK << 16) | (freq & 0xffff));
+		if (ret) {
+			pr_err("Failed to set soft %s fclk !\n",
+						max ? "max" : "min");
+			return ret;
+		}
+	}
+
+	if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT) &&
+	    (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
+		single_dpm_table = &(dpm_table->dcef_table);
+		freq = single_dpm_table->dpm_state.hard_min_level;
+		if (!max) {
+			ret = smu_send_smc_msg_with_param(smu,
+				SMU_MSG_SetHardMinByFreq,
+				(PPCLK_DCEFCLK << 16) | (freq & 0xffff));
+			if (ret) {
+				pr_err("Failed to set hard min dcefclk !\n");
+				return ret;
+			}
+		}
+	}
+
 	return ret;
 }
 
@@ -977,7 +1025,7 @@ static int vega20_force_clk_levels(struct smu_context *smu,
 {
 	struct vega20_dpm_table *dpm_table;
 	struct vega20_single_dpm_table *single_dpm_table;
-	uint32_t soft_min_level, soft_max_level;
+	uint32_t soft_min_level, soft_max_level, hard_min_level;
 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 	int ret = 0;
 
@@ -1009,13 +1057,13 @@ static int vega20_force_clk_levels(struct smu_context *smu,
 		single_dpm_table->dpm_state.soft_max_level =
 			single_dpm_table->dpm_levels[soft_max_level].value;
 
-		ret = vega20_upload_dpm_level(smu, false);
+		ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
 		if (ret) {
 			pr_err("Failed to upload boot level to lowest!\n");
 			break;
 		}
 
-		ret = vega20_upload_dpm_level(smu, true);
+		ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
 		if (ret)
 			pr_err("Failed to upload dpm max level to highest!\n");
 
@@ -1036,18 +1084,92 @@ static int vega20_force_clk_levels(struct smu_context *smu,
 		single_dpm_table->dpm_state.soft_max_level =
 			single_dpm_table->dpm_levels[soft_max_level].value;
 
-		ret = vega20_upload_dpm_level(smu, false);
+		ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
+		if (ret) {
+			pr_err("Failed to upload boot level to lowest!\n");
+			break;
+		}
+
+		ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
+		if (ret)
+			pr_err("Failed to upload dpm max level to highest!\n");
+
+		break;
+
+	case PP_SOCCLK:
+		single_dpm_table = &(dpm_table->soc_table);
+
+		if (soft_max_level >= single_dpm_table->count) {
+			pr_err("Clock level specified %d is over max allowed %d\n",
+					soft_max_level, single_dpm_table->count - 1);
+			ret = -EINVAL;
+			break;
+		}
+
+		single_dpm_table->dpm_state.soft_min_level =
+			single_dpm_table->dpm_levels[soft_min_level].value;
+		single_dpm_table->dpm_state.soft_max_level =
+			single_dpm_table->dpm_levels[soft_max_level].value;
+
+		ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
 		if (ret) {
 			pr_err("Failed to upload boot level to lowest!\n");
 			break;
 		}
 
-		ret = vega20_upload_dpm_level(smu, true);
+		ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
 		if (ret)
 			pr_err("Failed to upload dpm max level to highest!\n");
 
 		break;
 
+	case PP_FCLK:
+		single_dpm_table = &(dpm_table->fclk_table);
+
+		if (soft_max_level >= single_dpm_table->count) {
+			pr_err("Clock level specified %d is over max allowed %d\n",
+					soft_max_level, single_dpm_table->count - 1);
+			ret = -EINVAL;
+			break;
+		}
+
+		single_dpm_table->dpm_state.soft_min_level =
+			single_dpm_table->dpm_levels[soft_min_level].value;
+		single_dpm_table->dpm_state.soft_max_level =
+			single_dpm_table->dpm_levels[soft_max_level].value;
+
+		ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
+		if (ret) {
+			pr_err("Failed to upload boot level to lowest!\n");
+			break;
+		}
+
+		ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
+		if (ret)
+			pr_err("Failed to upload dpm max level to highest!\n");
+
+		break;
+
+	case PP_DCEFCLK:
+		hard_min_level = soft_min_level;
+		single_dpm_table = &(dpm_table->dcef_table);
+
+		if (hard_min_level >= single_dpm_table->count) {
+			pr_err("Clock level specified %d is over max allowed %d\n",
+					hard_min_level, single_dpm_table->count - 1);
+			ret = -EINVAL;
+			break;
+		}
+
+		single_dpm_table->dpm_state.hard_min_level =
+			single_dpm_table->dpm_levels[hard_min_level].value;
+
+		ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
+		if (ret)
+			pr_err("Failed to upload boot level to lowest!\n");
+
+		break;
+
 	case PP_PCIE:
 		break;
 
@@ -1723,14 +1845,23 @@ static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
 		dpm_table->mem_table.dpm_state.soft_max_level =
 		dpm_table->mem_table.dpm_levels[soft_level].value;
 
-	ret = vega20_upload_dpm_level(smu, false);
+	if (highest)
+		soft_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
+	else
+		soft_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
+
+	dpm_table->soc_table.dpm_state.soft_min_level =
+		dpm_table->soc_table.dpm_state.soft_max_level =
+		dpm_table->soc_table.dpm_levels[soft_level].value;
+
+	ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
 	if (ret) {
 		pr_err("Failed to upload boot level to %s!\n",
 				highest ? "highest" : "lowest");
 		return ret;
 	}
 
-	ret = vega20_upload_dpm_level(smu, true);
+	ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
 	if (ret) {
 		pr_err("Failed to upload dpm max level to %s!\n!",
 				highest ? "highest" : "lowest");
@@ -1740,6 +1871,49 @@ static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
 	return ret;
 }
 
+static int vega20_unforce_dpm_levels(struct smu_context *smu)
+{
+	uint32_t soft_min_level, soft_max_level;
+	int ret = 0;
+	struct vega20_dpm_table *dpm_table =
+		(struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
+
+	soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
+	soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
+	dpm_table->gfx_table.dpm_state.soft_min_level =
+		dpm_table->gfx_table.dpm_levels[soft_min_level].value;
+	dpm_table->gfx_table.dpm_state.soft_max_level =
+		dpm_table->gfx_table.dpm_levels[soft_max_level].value;
+
+	soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
+	soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
+	dpm_table->mem_table.dpm_state.soft_min_level =
+		dpm_table->gfx_table.dpm_levels[soft_min_level].value;
+	dpm_table->mem_table.dpm_state.soft_max_level =
+		dpm_table->gfx_table.dpm_levels[soft_max_level].value;
+
+	soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
+	soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
+	dpm_table->soc_table.dpm_state.soft_min_level =
+		dpm_table->soc_table.dpm_levels[soft_min_level].value;
+	dpm_table->soc_table.dpm_state.soft_max_level =
+		dpm_table->soc_table.dpm_levels[soft_max_level].value;
+
+	ret = smu_upload_dpm_level(smu, false, 0xFFFFFFFF);
+	if (ret) {
+		pr_err("Failed to upload DPM Bootup Levels!");
+		return ret;
+	}
+
+	ret = smu_upload_dpm_level(smu, true, 0xFFFFFFFF);
+	if (ret) {
+		pr_err("Failed to upload DPM Max Levels!");
+		return ret;
+	}
+
+	return ret;
+}
+
 static enum amd_dpm_forced_level vega20_get_performance_level(struct smu_context *smu)
 {
 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
@@ -2187,6 +2361,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
 	.apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
 	.notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
 	.force_dpm_limit_value = vega20_force_dpm_limit_value,
+	.unforce_dpm_levels = vega20_unforce_dpm_levels,
 	.upload_dpm_level = vega20_upload_dpm_level,
 	.get_profiling_clk_mask = vega20_get_profiling_clk_mask,
 };
-- 
2.7.4

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[PATCH 20/26] drm/amd/powerplay: add override pcie parameters

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

PCIE parameters should be override to fix the conflict between the ASIC
capabilities and the system capabilities.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Gui Chengming <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 46 ++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 118347c..876b688 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -28,6 +28,7 @@
 #include "soc15_common.h"
 #include "smu_v11_0.h"
 #include "atom.h"
+#include "amd_pcie.h"
 
 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 			   bool gate)
@@ -533,6 +534,47 @@ static int smu_fini_fb_allocations(struct smu_context *smu)
 	return 0;
 }
 
+static int smu_override_pcie_parameters(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
+	int ret;
+
+	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
+		pcie_gen = 3;
+	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
+		pcie_gen = 2;
+	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
+		pcie_gen = 1;
+	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
+		pcie_gen = 0;
+
+	/* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
+	 * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
+	 * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
+	 */
+	if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
+		pcie_width = 6;
+	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
+		pcie_width = 5;
+	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
+		pcie_width = 4;
+	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
+		pcie_width = 3;
+	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
+		pcie_width = 2;
+	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
+		pcie_width = 1;
+
+	smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
+	ret = smu_send_smc_msg_with_param(smu,
+					  SMU_MSG_OverridePcieParameters,
+					  smu_pcie_arg);
+	if (ret)
+		pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
+	return ret;
+}
+
 static int smu_smc_table_hw_init(struct smu_context *smu,
 				 bool initialize)
 {
@@ -620,6 +662,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
 	if (ret)
 		return ret;
 
+	ret = smu_override_pcie_parameters(smu);
+	if (ret)
+		return ret;
+
 	ret = smu_notify_display_change(smu);
 	if (ret)
 		return ret;
-- 
2.7.4

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[PATCH 21/26] drm/amd/powerplay: support sysfs to set/get pcie

[Huang Rui]

From: Likun Gao <Likun.Gao@amd.com>

Add sys interface to set and get pcie info for smu.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Gui Chengming <Jack.Gui@amd.com>
---
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 38 ++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index e564948..8ea44b7 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -35,6 +35,10 @@
 #include "vega20_ppt.h"
 #include "vega20_pptable.h"
 #include "vega20_ppsmc.h"
+#include "nbio/nbio_7_4_sh_mask.h"
+
+#define smnPCIE_LC_SPEED_CNTL			0x11140290
+#define smnPCIE_LC_LINK_WIDTH_CNTL		0x11140288
 
 #define MSG_MAP(msg, index) \
 	[SMU_MSG_##msg] = index
@@ -719,6 +723,8 @@ static int vega20_print_clk_levels(struct smu_context *smu,
 {
 	int i, now, size = 0;
 	int ret = 0;
+	uint32_t gen_speed, lane_width;
+	struct amdgpu_device *adev = smu->adev;
 	struct pp_clock_levels_with_latency clocks;
 	struct vega20_single_dpm_table *single_dpm_table;
 	struct smu_table_context *table_context = &smu->smu_table;
@@ -728,6 +734,7 @@ static int vega20_print_clk_levels(struct smu_context *smu,
 		(struct vega20_od8_settings *)table_context->od8_settings;
 	OverDriveTable_t *od_table =
 		(OverDriveTable_t *)(table_context->overdrive_table);
+	PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 
 	dpm_table = smu_dpm->dpm_context;
 
@@ -831,6 +838,28 @@ static int vega20_print_clk_levels(struct smu_context *smu,
 		break;
 
 	case PP_PCIE:
+		gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
+			     PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
+			>> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
+		lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
+			      PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
+			>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
+		for (i = 0; i < NUM_LINK_LEVELS; i++)
+			size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
+					(pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
+					(pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
+					(pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
+					(pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
+					(pptable->PcieLaneCount[i] == 1) ? "x1" :
+					(pptable->PcieLaneCount[i] == 2) ? "x2" :
+					(pptable->PcieLaneCount[i] == 3) ? "x4" :
+					(pptable->PcieLaneCount[i] == 4) ? "x8" :
+					(pptable->PcieLaneCount[i] == 5) ? "x12" :
+					(pptable->PcieLaneCount[i] == 6) ? "x16" : "",
+					pptable->LclkFreq[i],
+					(gen_speed == pptable->PcieGenSpeed[i]) &&
+					(lane_width == pptable->PcieLaneCount[i]) ?
+					"*" : "");
 		break;
 
 	case OD_SCLK:
@@ -1171,6 +1200,15 @@ static int vega20_force_clk_levels(struct smu_context *smu,
 		break;
 
 	case PP_PCIE:
+		if (soft_min_level >= NUM_LINK_LEVELS ||
+		    soft_max_level >= NUM_LINK_LEVELS)
+			return -EINVAL;
+
+		ret = smu_send_smc_msg_with_param(smu,
+				SMU_MSG_SetMinLinkDpmByIndex, soft_min_level);
+		if (ret)
+			pr_err("Failed to set min link dpm level!\n");
+
 		break;
 
 	default:
-- 
2.7.4

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[PATCH 22/26] drm/amd/powerplay: fix smc messsage index report

[Huang Rui]

We actually want to know the index of PPSMC_MSG.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index ffd71aa..3d29afd 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -103,7 +103,7 @@ static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
 	ret = smu_v11_0_wait_for_response(smu);
 
 	if (ret)
-		pr_err("Failed to send message 0x%x, response 0x%x\n", msg,
+		pr_err("Failed to send message 0x%x, response 0x%x\n", index,
 		       ret);
 
 	return ret;
@@ -124,8 +124,8 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 
 	ret = smu_v11_0_wait_for_response(smu);
 	if (ret)
-		pr_err("Failed to send message 0x%x, response 0x%x\n", msg,
-		       ret);
+		pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
+		       index, ret, param);
 
 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 
@@ -135,8 +135,8 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 
 	ret = smu_v11_0_wait_for_response(smu);
 	if (ret)
-		pr_err("Failed to send message 0x%x, response 0x%x\n", msg,
-		       ret);
+		pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
+		       index, ret, param);
 
 	return ret;
 }
-- 
2.7.4

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[PATCH 23/26] drm/amd/powerplay: fix byte alignment issue of smu11 pptable

[Huang Rui]

The smu_11_0_powerplay_table, smu_11_0_power_saving_clock_table, and
smu_11_0_overdrive_table need byte alignment. So we must add packed attribute
in the definitions.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
---
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
index e8a654b..92c65b8 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
@@ -91,7 +91,7 @@ struct smu_11_0_overdrive_table
     uint8_t  cap[SMU_11_0_MAX_ODFEATURE];                     //OD feature support flags
     uint32_t max[SMU_11_0_MAX_ODSETTING];                     //default maximum settings
     uint32_t min[SMU_11_0_MAX_ODSETTING];                     //default minimum settings
-};
+} __attribute__((packed));
 
 enum SMU_11_0_PPCLOCK_ID {
     SMU_11_0_PPCLOCK_GFXCLK = 0,
@@ -115,7 +115,7 @@ struct smu_11_0_power_saving_clock_table
     uint32_t count;                                           //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT
     uint32_t max[SMU_11_0_MAX_PPCLOCK];                       //PowerSavingClock Mode Clock Maximum array In MHz
     uint32_t min[SMU_11_0_MAX_PPCLOCK];                       //PowerSavingClock Mode Clock Minimum array In MHz
-};
+} __attribute__((packed));
 
 struct smu_11_0_powerplay_table
 {
@@ -142,6 +142,6 @@ struct smu_11_0_powerplay_table
       struct smu_11_0_overdrive_table               overdrive_table;
 
       PPTable_t smc_pptable;                        //PPTable_t in smu11_driver_if.h
-};
+} __attribute__((packed));
 
 #endif
-- 
2.7.4

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[PATCH 24/26] drm/amd/powerplay: move setting allowed mask and feature enabling together

[Huang Rui]

This patch moves setting allowed mask and feature enabling together to refine
the programming sequence.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 876b688..5e7e988 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -590,10 +590,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
 	if (ret)
 		return ret;
 
-	ret = smu_feature_set_allowed_mask(smu);
-	if (ret)
-		return ret;
-
 	if (initialize) {
 		ret = smu_read_pptable_from_vbios(smu);
 		if (ret)
@@ -658,6 +654,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
 	if (ret)
 		return ret;
 
+	ret = smu_feature_set_allowed_mask(smu);
+	if (ret)
+		return ret;
+
 	ret = smu_system_features_control(smu, true);
 	if (ret)
 		return ret;
-- 
2.7.4

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[PATCH 25/26] drm/amd/powerplay: fix the issue of checking on message mapping

[Huang Rui]

The vega20_message_map[index] scope should be in PPSMC_Message_Count not in
SMU_MSG_MAX_COUNT.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 8ea44b7..f7188a7 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -131,10 +131,15 @@ static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
 
 static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 {
-	if (index > SMU_MSG_MAX_COUNT || index > PPSMC_Message_Count)
+	int val;
+	if (index > SMU_MSG_MAX_COUNT)
 		return -EINVAL;
-	return vega20_message_map[index];
 
+	val = vega20_message_map[index];
+	if (val > PPSMC_Message_Count)
+		return -EINVAL;
+
+	return val;
 }
 
 static int vega20_allocate_dpm_context(struct smu_context *smu)
-- 
2.7.4

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[PATCH 26/26] drm/amd/powerplay: use REG32_PCIE wrapper instead for sw smu

[Huang Rui]

This patch uses REG32_PCIE wrapper instead of writting pci_index2 and reading
pci_data2. This sequence should be protected by pcie_idx_lock.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 3d29afd..ef25884 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -201,14 +201,13 @@ static int smu_v11_0_check_fw_status(struct smu_context *smu)
 	struct amdgpu_device *adev = smu->adev;
 	uint32_t mp1_fw_flags;
 
-	WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2,
-		     (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
-
-	mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2);
+	mp1_fw_flags = RREG32_PCIE(MP1_Public |
+				   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 
 	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 	    MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 		return 0;
+
 	return -EIO;
 }
 
-- 
2.7.4

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Re: [PATCH 04/26] drm/amd/powerplay: implement power1_cap and power1_cap_max interface for SMU11.

[Alex Deucher]

On Mon, Feb 25, 2019 at 7:13 AM Huang Rui <ray.huang@amd.com> wrote:
>
> From: Chengming Gui <Jack.Gui@amd.com>
>
> add get_power_limit and set_power_limit functions
> to support hwmon for SMU11.
>
> Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
> Reviewed-by: Huang Rui <ray.huang@amd.com>
> Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 15 ++++++++--
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     |  2 +-
>  drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  9 ++++--
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 41 +++++++++++++++++++-------
>  4 files changed, 49 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index d140b3d..92d0fb3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1761,7 +1761,11 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
>         struct amdgpu_device *adev = dev_get_drvdata(dev);
>         uint32_t limit = 0;
>
> -       if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
> +       if (is_support_sw_smu(adev)) {
> +               smu_get_power_limit(&adev->smu, &limit, true);
> +               return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
> +       }
> +       else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {

The } should be on the same line as the else.  e.g.,
} else if (...
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>


Alex

>                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
>                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
>         } else {
> @@ -1776,7 +1780,10 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
>         struct amdgpu_device *adev = dev_get_drvdata(dev);
>         uint32_t limit = 0;
>
> -       if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
> +       if (is_support_sw_smu(adev)) {
> +               smu_get_power_limit(&adev->smu, &limit, false);
> +               return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
> +       } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
>                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
>                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
>         } else {
> @@ -1799,7 +1806,9 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
>                 return err;
>
>         value = value / 1000000; /* convert to Watt */
> -       if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
> +       if (is_support_sw_smu(adev))
> +               adev->smu.funcs->set_power_limit(&adev->smu, value);
> +       else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
>                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
>                 if (err)
>                         return err;
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index ed2f7cc..ed2d199 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -619,7 +619,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
>         if (ret)
>                 return ret;
>
> -       ret = smu_get_power_limit(smu);
> +       ret = smu_get_power_limit(smu, &smu->default_power_limit, false);
>         if (ret)
>                 return ret;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 2cc7129..d49bdee 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -484,7 +484,8 @@ struct smu_funcs
>         int (*disable_all_mask)(struct smu_context *smu);
>         int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
>         int (*notify_display_change)(struct smu_context *smu);
> -       int (*get_power_limit)(struct smu_context *smu);
> +       int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
> +       int (*set_power_limit)(struct smu_context *smu, uint32_t n);
>         int (*get_current_clk_freq)(struct smu_context *smu, uint32_t clk_id, uint32_t *value);
>         int (*init_max_sustainable_clocks)(struct smu_context *smu);
>         int (*start_thermal_control)(struct smu_context *smu);
> @@ -619,8 +620,10 @@ struct smu_funcs
>         ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
>  #define smu_update_specified_od8_value(smu, index, value) \
>         ((smu)->ppt_funcs->update_specified_od8_value ? (smu)->ppt_funcs->update_specified_od8_value((smu), (index), (value)) : 0)
> -#define smu_get_power_limit(smu) \
> -       ((smu)->funcs->get_power_limit? (smu)->funcs->get_power_limit((smu)) : 0)
> +#define smu_get_power_limit(smu, limit, def) \
> +       ((smu)->funcs->get_power_limit ? (smu)->funcs->get_power_limit((smu), (limit), (def)) : 0)
> +#define smu_set_power_limit(smu, limit) \
> +       ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
>  #define smu_get_current_clk_freq(smu, clk_id, value) \
>         ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
>  #define smu_print_clk_levels(smu, type, buf) \
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index 6333c18..7397a63 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -873,23 +873,41 @@ static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
>         return 0;
>  }
>
> -static int smu_v11_0_get_power_limit(struct smu_context *smu)
> +static int smu_v11_0_get_power_limit(struct smu_context *smu,
> +                                    uint32_t *limit,
> +                                    bool get_default)
>  {
> -       int ret;
> -       uint32_t power_limit_value;
> +       int ret = 0;
>
> -       ret = smu_send_smc_msg_with_param(smu,
> -                       SMU_MSG_GetPptLimit,
> -                       POWER_SOURCE_AC << 16);
> +       if (get_default) {
> +               mutex_lock(&smu->mutex);
> +               *limit = smu->default_power_limit;
> +               mutex_unlock(&smu->mutex);
> +       } else {
> +                       ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
> +                                                         POWER_SOURCE_AC << 16);
> +                       if (ret) {
> +                               pr_err("[%s] get PPT limit failed!", __func__);
> +                               return ret;
> +                       }
> +                       smu_read_smc_arg(smu, limit);
> +                       smu->power_limit = *limit;
> +       }
> +
> +       return ret;
> +}
> +
> +static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
> +{
> +       int ret = 0;
> +               if (smu_feature_is_enabled(smu, FEATURE_PPT_BIT))
> +                       ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
>         if (ret) {
> -               pr_err("[GetPptLimit] get default PPT limit failed!");
> +               pr_err("[%s] Set power limit Failed!", __func__);
>                 return ret;
>         }
>
> -       smu_read_smc_arg(smu, &power_limit_value);
> -       smu->power_limit = smu->default_power_limit = power_limit_value;
> -
> -       return 0;
> +       return ret;
>  }
>
>  static int smu_v11_0_get_current_clk_freq(struct smu_context *smu, uint32_t clk_id, uint32_t *value)
> @@ -1760,6 +1778,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
>         .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
>         .notify_display_change = smu_v11_0_notify_display_change,
>         .get_power_limit = smu_v11_0_get_power_limit,
> +       .set_power_limit = smu_v11_0_set_power_limit,
>         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
>         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
>         .start_thermal_control = smu_v11_0_start_thermal_control,
> --
> 2.7.4
>
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Re: [PATCH 07/26] drm/amd/powerplay: implement pwm1_enable hwmon interface for SMU11

[Alex Deucher]

On Mon, Feb 25, 2019 at 7:13 AM Huang Rui <ray.huang@amd.com> wrote:
>
> From: Chengming Gui <Jack.Gui@amd.com>
>
> 1, set get_pwm1_enable and set_pwm1_enable functions to call
> smu_get_fan_control_mode and smu_set_fan_control_mode for SMU11
> 2, implement set_fan_control_mode function
>
> v2: add return value in set_fan_control_mode function
>
> Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
> Reviewed-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 31 +++++++++++++++++---------
>  drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  3 +++
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 31 ++++++++++++++++++++++++++
>  3 files changed, 55 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index d40aa39..ac991f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1382,11 +1382,14 @@ static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
>  {
>         struct amdgpu_device *adev = dev_get_drvdata(dev);
>         u32 pwm_mode = 0;
> +       if (is_support_sw_smu(adev))
> +               pwm_mode = smu_get_fan_control_mode(&adev->smu);
> +       else {

If either clause has { }, both should.  E.g.,

if () {
    ...
} else {
    ...
}
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>


> +               if (!adev->powerplay.pp_funcs->get_fan_control_mode)
> +                       return -EINVAL;
>
> -       if (!adev->powerplay.pp_funcs->get_fan_control_mode)
> -               return -EINVAL;
> -
> -       pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
> +               pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
> +       }
>
>         return sprintf(buf, "%i\n", pwm_mode);
>  }
> @@ -1405,14 +1408,22 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
>              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
>                 return -EINVAL;
>
> -       if (!adev->powerplay.pp_funcs->set_fan_control_mode)
> -               return -EINVAL;
> +       if (is_support_sw_smu(adev)) {
> +               err = kstrtoint(buf, 10, &value);
> +               if (err)
> +                       return err;
>
> -       err = kstrtoint(buf, 10, &value);
> -       if (err)
> -               return err;
> +               smu_set_fan_control_mode(&adev->smu, value);
> +       } else {
> +               if (!adev->powerplay.pp_funcs->set_fan_control_mode)
> +                       return -EINVAL;
> +
> +               err = kstrtoint(buf, 10, &value);
> +               if (err)
> +                       return err;
>
> -       amdgpu_dpm_set_fan_control_mode(adev, value);
> +               amdgpu_dpm_set_fan_control_mode(adev, value);
> +       }
>
>         return count;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index f94d09d..ef2b807 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -533,6 +533,7 @@ struct smu_funcs
>         uint32_t (*get_mclk)(struct smu_context *smu, bool low);
>         int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
>         uint32_t (*get_fan_control_mode)(struct smu_context *smu);
> +       int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
>         int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
>         int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
>  };
> @@ -669,6 +670,8 @@ struct smu_funcs
>         ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
>  #define smu_get_fan_control_mode(smu) \
>         ((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
> +#define smu_set_fan_control_mode(smu, value) \
> +       ((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
>  #define smu_get_fan_speed_percent(smu, speed) \
>         ((smu)->funcs->get_fan_speed_percent ? (smu)->funcs->get_fan_speed_percent((smu), (speed)) : 0)
>  #define smu_set_fan_speed_percent(smu, speed) \
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index d8917b2..aaa1bd8 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1833,6 +1833,36 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
>         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
>  }
>
> +static int
> +smu_v11_0_set_fan_control_mode(struct smu_context *smu,
> +                              uint32_t mode)
> +{
> +       int ret = 0;
> +       bool start = 1;
> +       bool stop  = 0;
> +
> +       switch (mode) {
> +       case AMD_FAN_CTRL_NONE:
> +               ret = smu_v11_0_set_fan_speed_percent(smu, 100);
> +               break;
> +       case AMD_FAN_CTRL_MANUAL:
> +               ret = smu_v11_0_smc_fan_control(smu, stop);
> +               break;
> +       case AMD_FAN_CTRL_AUTO:
> +               ret = smu_v11_0_smc_fan_control(smu, start);
> +               break;
> +       default:
> +               break;
> +       }
> +
> +       if (ret) {
> +               pr_err("[%s]Set fan control mode failed!");
> +               return -EINVAL;
> +       }
> +
> +       return ret;
> +}
> +
>  static const struct smu_funcs smu_v11_0_funcs = {
>         .init_microcode = smu_v11_0_init_microcode,
>         .load_microcode = smu_v11_0_load_microcode,
> @@ -1885,6 +1915,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
>         .dpm_set_vce_enable = smu_v11_0_dpm_set_vce_enable,
>         .get_current_rpm = smu_v11_0_get_current_rpm,
>         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
> +       .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
>         .get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
>         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
>  };
> --
> 2.7.4
>
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Re: [PATCH 08/26] drm/amd/powerplay: implement fan1_enable hwmon interface for SMU11 (v2)

[Alex Deucher]

On Mon, Feb 25, 2019 at 7:13 AM Huang Rui <ray.huang@amd.com> wrote:
>
> From: Chengming Gui <Jack.Gui@amd.com>
>
> set the fan1_enable hwmon interface to call
> smu_get_fan_control_mode and smu_set_fan_control_mode.
>
> v2: fix print value.
>
> Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
> Reviewed-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c    | 23 +++++++++++++++--------
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c |  2 +-
>  2 files changed, 16 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index ac991f9..9413c39 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1635,12 +1635,15 @@ static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
>         struct amdgpu_device *adev = dev_get_drvdata(dev);
>         u32 pwm_mode = 0;
>
> -       if (!adev->powerplay.pp_funcs->get_fan_control_mode)
> -               return -EINVAL;
> -
> -       pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
> +       if (is_support_sw_smu(adev)) {
> +               pwm_mode = smu_get_fan_control_mode(&adev->smu);
> +       } else {
> +               if (!adev->powerplay.pp_funcs->get_fan_control_mode)
> +                       return -EINVAL;
>
> -       return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
> +               pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
> +       }
> +               return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);

indentation looks wrong here.
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>


>  }
>
>  static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
> @@ -1658,8 +1661,6 @@ static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
>              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
>                 return -EINVAL;
>
> -       if (!adev->powerplay.pp_funcs->set_fan_control_mode)
> -               return -EINVAL;
>
>         err = kstrtoint(buf, 10, &value);
>         if (err)
> @@ -1672,7 +1673,13 @@ static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
>         else
>                 return -EINVAL;
>
> -       amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
> +       if (is_support_sw_smu(adev)) {
> +               smu_set_fan_control_mode(&adev->smu, pwm_mode);
> +       } else {
> +               if (!adev->powerplay.pp_funcs->set_fan_control_mode)
> +                       return -EINVAL;
> +               amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
> +       }
>
>         return count;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index aaa1bd8..c0bc4f4 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1856,7 +1856,7 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
>         }
>
>         if (ret) {
> -               pr_err("[%s]Set fan control mode failed!");
> +               pr_err("[%s]Set fan control mode failed!", __func__);
>                 return -EINVAL;
>         }
>
> --
> 2.7.4
>
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Re: [PATCH 13/26] drm/amd/powerplay: add limit of pp_feature for smu

[Alex Deucher]

On Mon, Feb 25, 2019 at 7:13 AM Huang Rui <ray.huang@amd.com> wrote:
>
> From: Likun Gao <Likun.Gao@amd.com>
>
> Move pp_feature from the struct of amd_powerplay to amdgpu_device.

I think we can probably drop this change.  If you do want to move it
out of powerplay, maybe put it in struct amdgpu_pm?  I don't like
adding random stuff to amdgpu_device.

> Add pp_feature limit for overdrive interface.
>
> Signed-off-by: Likun Gao <Likun.Gao@amd.com>
> Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h            | 4 +++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c     | 2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c        | 2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 6 ++++--
>  drivers/gpu/drm/amd/amdgpu/kv_dpm.c            | 2 +-
>  drivers/gpu/drm/amd/amdgpu/soc15.c             | 2 +-
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 2 +-
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 4 ++++
>  drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
>  9 files changed, 19 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index d1c02fa..f96b6e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -706,7 +706,6 @@ enum amd_hw_ip_block_type {
>  struct amd_powerplay {
>         void *pp_handle;
>         const struct amd_pm_funcs *pp_funcs;
> -       uint32_t pp_feature;
>  };
>
>  #define AMDGPU_RESET_MAGIC_NUM 64
> @@ -842,6 +841,9 @@ struct amdgpu_device {
>         /* interrupts */
>         struct amdgpu_irq               irq;
>
> +       /* powerplay feature */
> +       uint32_t pp_feature;
> +
>         /* powerplay */
>         struct amd_powerplay            powerplay;
>         bool                            pp_force_state_enabled;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index fcab1fe..c8fe5e5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1506,7 +1506,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
>                         return -EAGAIN;
>         }
>
> -       adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
> +       adev->pp_feature = amdgpu_pp_feature_mask;
>
>         for (i = 0; i < adev->num_ip_blocks; i++) {
>                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 97a60da..bcc732d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -390,7 +390,7 @@ void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev)
>
>  void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
>  {
> -       if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK))
> +       if (!(adev->pp_feature & PP_GFXOFF_MASK))
>                 return;
>
>         if (!adev->powerplay.pp_funcs || !adev->powerplay.pp_funcs->set_powergating_by_smu)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 6bc80c1..fe1b0c4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -2558,7 +2558,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
>                                 "pp_power_profile_mode\n");
>                 return ret;
>         }
> -       if (is_support_sw_smu(adev) || hwmgr->od_enabled) {
> +       if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
> +           (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
>                 ret = device_create_file(adev->dev,
>                                 &dev_attr_pp_od_clk_voltage);
>                 if (ret) {
> @@ -2634,7 +2635,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
>         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
>         device_remove_file(adev->dev,
>                         &dev_attr_pp_power_profile_mode);
> -       if (hwmgr->od_enabled)
> +       if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
> +           (!is_support_sw_smu(adev) && hwmgr->od_enabled))
>                 device_remove_file(adev->dev,
>                                 &dev_attr_pp_od_clk_voltage);
>         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
> diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> index 0c9a2c0..9022f42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> @@ -2824,7 +2824,7 @@ static int kv_dpm_init(struct amdgpu_device *adev)
>                 pi->caps_tcp_ramping = true;
>         }
>
> -       if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
> +       if (adev->pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
>                 pi->caps_sclk_ds = true;
>         else
>                 pi->caps_sclk_ds = false;
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 9f6ce6e..c296f6c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -933,7 +933,7 @@ static int soc15_common_early_init(void *handle)
>                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
>                 }
>
> -               if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
> +               if (adev->pp_feature & PP_GFXOFF_MASK)
>                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
>                                 AMD_PG_SUPPORT_CP |
>                                 AMD_PG_SUPPORT_RLC_SMU_HS;
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 3f73f7c..ea5689a 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -53,7 +53,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
>         mutex_init(&hwmgr->smu_lock);
>         hwmgr->chip_family = adev->family;
>         hwmgr->chip_id = adev->asic_type;
> -       hwmgr->feature_mask = adev->powerplay.pp_feature;
> +       hwmgr->feature_mask = adev->pp_feature;
>         hwmgr->display_config = &adev->pm.pm_display_cfg;
>         adev->powerplay.pp_handle = hwmgr;
>         adev->powerplay.pp_funcs = &pp_dpm_funcs;
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 9cb45fe..fa0af71 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -290,6 +290,9 @@ static int smu_set_funcs(struct amdgpu_device *adev)
>
>         switch (adev->asic_type) {
>         case CHIP_VEGA20:
> +               smu->feature_mask &= ~PP_GFXOFF_MASK;
> +               if (smu->feature_mask & PP_OVERDRIVE_MASK)
> +                       smu->od_enabled = true;
>                 smu_v11_0_set_smu_funcs(smu);
>                 break;
>         default:
> @@ -306,6 +309,7 @@ static int smu_early_init(void *handle)
>
>         smu->adev = adev;
>         mutex_init(&smu->mutex);
> +       smu->feature_mask = adev->pp_feature;
>
>         return smu_set_funcs(adev);
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 00ef6f1..8c7eac9 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -384,6 +384,7 @@ struct smu_context
>         uint32_t pstate_sclk;
>         uint32_t pstate_mclk;
>
> +       bool od_enabled;
>         uint32_t power_limit;
>         uint32_t default_power_limit;
>
> @@ -399,6 +400,8 @@ struct smu_context
>         uint32_t workload_setting[WORKLOAD_POLICY_MAX];
>         uint32_t power_profile_mode;
>         uint32_t default_power_profile_mode;
> +
> +       uint32_t feature_mask;
>  };
>
>  struct pptable_funcs {
> --
> 2.7.4
>
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Re: [PATCH 26/26] drm/amd/powerplay: use REG32_PCIE wrapper instead for sw smu

[Alex Deucher]

On Mon, Feb 25, 2019 at 7:14 AM Huang Rui <ray.huang@amd.com> wrote:
>
> This patch uses REG32_PCIE wrapper instead of writting pci_index2 and reading
> pci_data2. This sequence should be protected by pcie_idx_lock.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

I left comments on a few patches.  The rest are:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>


> ---
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 +++----
>  1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index 3d29afd..ef25884 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -201,14 +201,13 @@ static int smu_v11_0_check_fw_status(struct smu_context *smu)
>         struct amdgpu_device *adev = smu->adev;
>         uint32_t mp1_fw_flags;
>
> -       WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2,
> -                    (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
> -
> -       mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2);
> +       mp1_fw_flags = RREG32_PCIE(MP1_Public |
> +                                  (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
>
>         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
>             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
>                 return 0;
> +
>         return -EIO;
>  }
>
> --
> 2.7.4
>
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RE: [PATCH 07/26] drm/amd/powerplay: implement pwm1_enable hwmon interface for SMU11

[Huang, Ray]

> -----Original Message-----
> From: Alex Deucher [mailto:alexdeucher@gmail.com]
> Sent: Tuesday, February 26, 2019 11:59 AM
> To: Huang, Ray <Ray.Huang@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Gao, Likun
> <Likun.Gao@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com>; Gui,
> Jack <Jack.Gui@amd.com>
> Subject: Re: [PATCH 07/26] drm/amd/powerplay: implement pwm1_enable
> hwmon interface for SMU11
> 
> On Mon, Feb 25, 2019 at 7:13 AM Huang Rui <ray.huang@amd.com> wrote:
> >
> > From: Chengming Gui <Jack.Gui@amd.com>
> >
> > 1, set get_pwm1_enable and set_pwm1_enable functions to call
> > smu_get_fan_control_mode and smu_set_fan_control_mode for SMU11
> 2,
> > implement set_fan_control_mode function
> >
> > v2: add return value in set_fan_control_mode function
> >
> > Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
> > Reviewed-by: Huang Rui <ray.huang@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 31
> +++++++++++++++++---------
> >  drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  3 +++
> >  drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 31
> ++++++++++++++++++++++++++
> >  3 files changed, 55 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > index d40aa39..ac991f9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > @@ -1382,11 +1382,14 @@ static ssize_t
> > amdgpu_hwmon_get_pwm1_enable(struct device *dev,  {
> >         struct amdgpu_device *adev = dev_get_drvdata(dev);
> >         u32 pwm_mode = 0;
> > +       if (is_support_sw_smu(adev))
> > +               pwm_mode = smu_get_fan_control_mode(&adev->smu);
> > +       else {
> 
> If either clause has { }, both should.  E.g.,
> 
> if () {
>     ...
> } else {
>     ...
> }

Yes, will fix it.

Thanks,
Ray

> With that fixed:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> 
> 
> > +               if (!adev->powerplay.pp_funcs->get_fan_control_mode)
> > +                       return -EINVAL;
> >
> > -       if (!adev->powerplay.pp_funcs->get_fan_control_mode)
> > -               return -EINVAL;
> > -
> > -       pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
> > +               pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
> > +       }
> >
> >         return sprintf(buf, "%i\n", pwm_mode);  } @@ -1405,14 +1408,22
> > @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
> >              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
> >                 return -EINVAL;
> >
> > -       if (!adev->powerplay.pp_funcs->set_fan_control_mode)
> > -               return -EINVAL;
> > +       if (is_support_sw_smu(adev)) {
> > +               err = kstrtoint(buf, 10, &value);
> > +               if (err)
> > +                       return err;
> >
> > -       err = kstrtoint(buf, 10, &value);
> > -       if (err)
> > -               return err;
> > +               smu_set_fan_control_mode(&adev->smu, value);
> > +       } else {
> > +               if (!adev->powerplay.pp_funcs->set_fan_control_mode)
> > +                       return -EINVAL;
> > +
> > +               err = kstrtoint(buf, 10, &value);
> > +               if (err)
> > +                       return err;
> >
> > -       amdgpu_dpm_set_fan_control_mode(adev, value);
> > +               amdgpu_dpm_set_fan_control_mode(adev, value);
> > +       }
> >
> >         return count;
> >  }
> > diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> > b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> > index f94d09d..ef2b807 100644
> > --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> > +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> > @@ -533,6 +533,7 @@ struct smu_funcs
> >         uint32_t (*get_mclk)(struct smu_context *smu, bool low);
> >         int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
> >         uint32_t (*get_fan_control_mode)(struct smu_context *smu);
> > +       int (*set_fan_control_mode)(struct smu_context *smu, uint32_t
> > + mode);
> >         int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t
> *speed);
> >         int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t
> > speed);  }; @@ -669,6 +670,8 @@ struct smu_funcs
> >         ((smu)->ppt_funcs->set_cpu_power_state ?
> > (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)  #define
> smu_get_fan_control_mode(smu) \
> >         ((smu)->funcs->get_fan_control_mode ?
> > (smu)->funcs->get_fan_control_mode((smu)) : 0)
> > +#define smu_set_fan_control_mode(smu, value) \
> > +       ((smu)->funcs->set_fan_control_mode ?
> > +(smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
> >  #define smu_get_fan_speed_percent(smu, speed) \
> >         ((smu)->funcs->get_fan_speed_percent ?
> > (smu)->funcs->get_fan_speed_percent((smu), (speed)) : 0)  #define
> > smu_set_fan_speed_percent(smu, speed) \ diff --git
> > a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> > b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> > index d8917b2..aaa1bd8 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> > @@ -1833,6 +1833,36 @@ smu_v11_0_set_fan_speed_percent(struct
> smu_context *smu, uint32_t speed)
> >         return smu_v11_0_set_fan_static_mode(smu,
> > FDO_PWM_MODE_STATIC);  }
> >
> > +static int
> > +smu_v11_0_set_fan_control_mode(struct smu_context *smu,
> > +                              uint32_t mode) {
> > +       int ret = 0;
> > +       bool start = 1;
> > +       bool stop  = 0;
> > +
> > +       switch (mode) {
> > +       case AMD_FAN_CTRL_NONE:
> > +               ret = smu_v11_0_set_fan_speed_percent(smu, 100);
> > +               break;
> > +       case AMD_FAN_CTRL_MANUAL:
> > +               ret = smu_v11_0_smc_fan_control(smu, stop);
> > +               break;
> > +       case AMD_FAN_CTRL_AUTO:
> > +               ret = smu_v11_0_smc_fan_control(smu, start);
> > +               break;
> > +       default:
> > +               break;
> > +       }
> > +
> > +       if (ret) {
> > +               pr_err("[%s]Set fan control mode failed!");
> > +               return -EINVAL;
> > +       }
> > +
> > +       return ret;
> > +}
> > +
> >  static const struct smu_funcs smu_v11_0_funcs = {
> >         .init_microcode = smu_v11_0_init_microcode,
> >         .load_microcode = smu_v11_0_load_microcode, @@ -1885,6 +1915,7
> > @@ static const struct smu_funcs smu_v11_0_funcs = {
> >         .dpm_set_vce_enable = smu_v11_0_dpm_set_vce_enable,
> >         .get_current_rpm = smu_v11_0_get_current_rpm,
> >         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
> > +       .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
> >         .get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
> >         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,  };
> > --
> > 2.7.4
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 13/26] drm/amd/powerplay: add limit of pp_feature for smu

[Huang, Ray]

> -----Original Message-----
> From: Alex Deucher [mailto:alexdeucher@gmail.com]
> Sent: Tuesday, February 26, 2019 12:08 PM
> To: Huang, Ray <Ray.Huang@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Gao, Likun
> <Likun.Gao@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com>; Gui,
> Jack <Jack.Gui@amd.com>
> Subject: Re: [PATCH 13/26] drm/amd/powerplay: add limit of pp_feature for
> smu
> 
> On Mon, Feb 25, 2019 at 7:13 AM Huang Rui <ray.huang@amd.com> wrote:
> >
> > From: Likun Gao <Likun.Gao@amd.com>
> >
> > Move pp_feature from the struct of amd_powerplay to amdgpu_device.
> 
> I think we can probably drop this change.  If you do want to move it out of
> powerplay, maybe put it in struct amdgpu_pm?  I don't like adding random
> stuff to amdgpu_device.

While we init sw smu, the powerplay structure won't be initialized. So we move the pp_feature out of powerplay.
And yes, putting it in struct amdgpu_pm is better than in struct amdgpu_device.

Thanks,
Ray

> 
> > Add pp_feature limit for overdrive interface.
> >
> > Signed-off-by: Likun Gao <Likun.Gao@amd.com>
> > Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu.h            | 4 +++-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c     | 2 +-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c        | 2 +-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 6 ++++--
> >  drivers/gpu/drm/amd/amdgpu/kv_dpm.c            | 2 +-
> >  drivers/gpu/drm/amd/amdgpu/soc15.c             | 2 +-
> >  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 2 +-
> >  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 4 ++++
> >  drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
> >  9 files changed, 19 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index d1c02fa..f96b6e9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -706,7 +706,6 @@ enum amd_hw_ip_block_type {  struct
> amd_powerplay
> > {
> >         void *pp_handle;
> >         const struct amd_pm_funcs *pp_funcs;
> > -       uint32_t pp_feature;
> >  };
> >
> >  #define AMDGPU_RESET_MAGIC_NUM 64
> > @@ -842,6 +841,9 @@ struct amdgpu_device {
> >         /* interrupts */
> >         struct amdgpu_irq               irq;
> >
> > +       /* powerplay feature */
> > +       uint32_t pp_feature;
> > +
> >         /* powerplay */
> >         struct amd_powerplay            powerplay;
> >         bool                            pp_force_state_enabled;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index fcab1fe..c8fe5e5 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -1506,7 +1506,7 @@ static int amdgpu_device_ip_early_init(struct
> amdgpu_device *adev)
> >                         return -EAGAIN;
> >         }
> >
> > -       adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
> > +       adev->pp_feature = amdgpu_pp_feature_mask;
> >
> >         for (i = 0; i < adev->num_ip_blocks; i++) {
> >                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) { diff
> > --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > index 97a60da..bcc732d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > @@ -390,7 +390,7 @@ void amdgpu_gfx_compute_mqd_sw_fini(struct
> > amdgpu_device *adev)
> >
> >  void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)  {
> > -       if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK))
> > +       if (!(adev->pp_feature & PP_GFXOFF_MASK))
> >                 return;
> >
> >         if (!adev->powerplay.pp_funcs ||
> > !adev->powerplay.pp_funcs->set_powergating_by_smu)
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > index 6bc80c1..fe1b0c4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > @@ -2558,7 +2558,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device
> *adev)
> >                                 "pp_power_profile_mode\n");
> >                 return ret;
> >         }
> > -       if (is_support_sw_smu(adev) || hwmgr->od_enabled) {
> > +       if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
> > +           (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
> >                 ret = device_create_file(adev->dev,
> >                                 &dev_attr_pp_od_clk_voltage);
> >                 if (ret) {
> > @@ -2634,7 +2635,8 @@ void amdgpu_pm_sysfs_fini(struct
> amdgpu_device *adev)
> >         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
> >         device_remove_file(adev->dev,
> >                         &dev_attr_pp_power_profile_mode);
> > -       if (hwmgr->od_enabled)
> > +       if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
> > +           (!is_support_sw_smu(adev) && hwmgr->od_enabled))
> >                 device_remove_file(adev->dev,
> >                                 &dev_attr_pp_od_clk_voltage);
> >         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> > b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> > index 0c9a2c0..9022f42 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> > @@ -2824,7 +2824,7 @@ static int kv_dpm_init(struct amdgpu_device
> *adev)
> >                 pi->caps_tcp_ramping = true;
> >         }
> >
> > -       if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
> > +       if (adev->pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
> >                 pi->caps_sclk_ds = true;
> >         else
> >                 pi->caps_sclk_ds = false; diff --git
> > a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > index 9f6ce6e..c296f6c 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > @@ -933,7 +933,7 @@ static int soc15_common_early_init(void *handle)
> >                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
> AMD_PG_SUPPORT_VCN;
> >                 }
> >
> > -               if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
> > +               if (adev->pp_feature & PP_GFXOFF_MASK)
> >                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
> >                                 AMD_PG_SUPPORT_CP |
> >                                 AMD_PG_SUPPORT_RLC_SMU_HS; diff --git
> > a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > index 3f73f7c..ea5689a 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > @@ -53,7 +53,7 @@ static int amd_powerplay_create(struct
> amdgpu_device *adev)
> >         mutex_init(&hwmgr->smu_lock);
> >         hwmgr->chip_family = adev->family;
> >         hwmgr->chip_id = adev->asic_type;
> > -       hwmgr->feature_mask = adev->powerplay.pp_feature;
> > +       hwmgr->feature_mask = adev->pp_feature;
> >         hwmgr->display_config = &adev->pm.pm_display_cfg;
> >         adev->powerplay.pp_handle = hwmgr;
> >         adev->powerplay.pp_funcs = &pp_dpm_funcs; diff --git
> > a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > index 9cb45fe..fa0af71 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > @@ -290,6 +290,9 @@ static int smu_set_funcs(struct amdgpu_device
> > *adev)
> >
> >         switch (adev->asic_type) {
> >         case CHIP_VEGA20:
> > +               smu->feature_mask &= ~PP_GFXOFF_MASK;
> > +               if (smu->feature_mask & PP_OVERDRIVE_MASK)
> > +                       smu->od_enabled = true;
> >                 smu_v11_0_set_smu_funcs(smu);
> >                 break;
> >         default:
> > @@ -306,6 +309,7 @@ static int smu_early_init(void *handle)
> >
> >         smu->adev = adev;
> >         mutex_init(&smu->mutex);
> > +       smu->feature_mask = adev->pp_feature;
> >
> >         return smu_set_funcs(adev);
> >  }
> > diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> > b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> > index 00ef6f1..8c7eac9 100644
> > --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> > +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> > @@ -384,6 +384,7 @@ struct smu_context
> >         uint32_t pstate_sclk;
> >         uint32_t pstate_mclk;
> >
> > +       bool od_enabled;
> >         uint32_t power_limit;
> >         uint32_t default_power_limit;
> >
> > @@ -399,6 +400,8 @@ struct smu_context
> >         uint32_t workload_setting[WORKLOAD_POLICY_MAX];
> >         uint32_t power_profile_mode;
> >         uint32_t default_power_profile_mode;
> > +
> > +       uint32_t feature_mask;
> >  };
> >
> >  struct pptable_funcs {
> > --
> > 2.7.4
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 13/26] drm/amd/powerplay: add limit of pp_feature for smu

[Gao, Likun]

OK, thanks for the advice. I will try to put pp_feature in the struct amdgpu_pm and send out the changed patch latter.

Regards,
Likun

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Huang, Ray
Sent: Tuesday, February 26, 2019 2:02 PM
To: Alex Deucher <alexdeucher@gmail.com>
Cc: Gao, Likun <Likun.Gao@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com>; Gui, Jack <Jack.Gui@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: RE: [PATCH 13/26] drm/amd/powerplay: add limit of pp_feature for smu

> -----Original Message-----
> From: Alex Deucher [mailto:alexdeucher@gmail.com]
> Sent: Tuesday, February 26, 2019 12:08 PM
> To: Huang, Ray <Ray.Huang@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Gao, Likun 
> <Likun.Gao@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com>; Gui, 
> Jack <Jack.Gui@amd.com>
> Subject: Re: [PATCH 13/26] drm/amd/powerplay: add limit of pp_feature 
> for smu
> 
> On Mon, Feb 25, 2019 at 7:13 AM Huang Rui <ray.huang@amd.com> wrote:
> >
> > From: Likun Gao <Likun.Gao@amd.com>
> >
> > Move pp_feature from the struct of amd_powerplay to amdgpu_device.
> 
> I think we can probably drop this change.  If you do want to move it 
> out of powerplay, maybe put it in struct amdgpu_pm?  I don't like 
> adding random stuff to amdgpu_device.

While we init sw smu, the powerplay structure won't be initialized. So we move the pp_feature out of powerplay.
And yes, putting it in struct amdgpu_pm is better than in struct amdgpu_device.

Thanks,
Ray

> 
> > Add pp_feature limit for overdrive interface.
> >
> > Signed-off-by: Likun Gao <Likun.Gao@amd.com>
> > Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu.h            | 4 +++-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c     | 2 +-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c        | 2 +-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 6 ++++--
> >  drivers/gpu/drm/amd/amdgpu/kv_dpm.c            | 2 +-
> >  drivers/gpu/drm/amd/amdgpu/soc15.c             | 2 +-
> >  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 2 +-
> >  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 4 ++++
> >  drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
> >  9 files changed, 19 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index d1c02fa..f96b6e9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -706,7 +706,6 @@ enum amd_hw_ip_block_type {  struct
> amd_powerplay
> > {
> >         void *pp_handle;
> >         const struct amd_pm_funcs *pp_funcs;
> > -       uint32_t pp_feature;
> >  };
> >
> >  #define AMDGPU_RESET_MAGIC_NUM 64
> > @@ -842,6 +841,9 @@ struct amdgpu_device {
> >         /* interrupts */
> >         struct amdgpu_irq               irq;
> >
> > +       /* powerplay feature */
> > +       uint32_t pp_feature;
> > +
> >         /* powerplay */
> >         struct amd_powerplay            powerplay;
> >         bool                            pp_force_state_enabled;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index fcab1fe..c8fe5e5 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -1506,7 +1506,7 @@ static int amdgpu_device_ip_early_init(struct
> amdgpu_device *adev)
> >                         return -EAGAIN;
> >         }
> >
> > -       adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
> > +       adev->pp_feature = amdgpu_pp_feature_mask;
> >
> >         for (i = 0; i < adev->num_ip_blocks; i++) {
> >                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) { diff 
> > --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > index 97a60da..bcc732d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > @@ -390,7 +390,7 @@ void amdgpu_gfx_compute_mqd_sw_fini(struct
> > amdgpu_device *adev)
> >
> >  void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)  {
> > -       if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK))
> > +       if (!(adev->pp_feature & PP_GFXOFF_MASK))
> >                 return;
> >
> >         if (!adev->powerplay.pp_funcs ||
> > !adev->powerplay.pp_funcs->set_powergating_by_smu)
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > index 6bc80c1..fe1b0c4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > @@ -2558,7 +2558,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device
> *adev)
> >                                 "pp_power_profile_mode\n");
> >                 return ret;
> >         }
> > -       if (is_support_sw_smu(adev) || hwmgr->od_enabled) {
> > +       if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
> > +           (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
> >                 ret = device_create_file(adev->dev,
> >                                 &dev_attr_pp_od_clk_voltage);
> >                 if (ret) {
> > @@ -2634,7 +2635,8 @@ void amdgpu_pm_sysfs_fini(struct
> amdgpu_device *adev)
> >         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
> >         device_remove_file(adev->dev,
> >                         &dev_attr_pp_power_profile_mode);
> > -       if (hwmgr->od_enabled)
> > +       if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
> > +           (!is_support_sw_smu(adev) && hwmgr->od_enabled))
> >                 device_remove_file(adev->dev,
> >                                 &dev_attr_pp_od_clk_voltage);
> >         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent); 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> > b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> > index 0c9a2c0..9022f42 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> > @@ -2824,7 +2824,7 @@ static int kv_dpm_init(struct amdgpu_device
> *adev)
> >                 pi->caps_tcp_ramping = true;
> >         }
> >
> > -       if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
> > +       if (adev->pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
> >                 pi->caps_sclk_ds = true;
> >         else
> >                 pi->caps_sclk_ds = false; diff --git 
> > a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > index 9f6ce6e..c296f6c 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > @@ -933,7 +933,7 @@ static int soc15_common_early_init(void *handle)
> >                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
> AMD_PG_SUPPORT_VCN;
> >                 }
> >
> > -               if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
> > +               if (adev->pp_feature & PP_GFXOFF_MASK)
> >                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
> >                                 AMD_PG_SUPPORT_CP |
> >                                 AMD_PG_SUPPORT_RLC_SMU_HS; diff 
> > --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > index 3f73f7c..ea5689a 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > @@ -53,7 +53,7 @@ static int amd_powerplay_create(struct
> amdgpu_device *adev)
> >         mutex_init(&hwmgr->smu_lock);
> >         hwmgr->chip_family = adev->family;
> >         hwmgr->chip_id = adev->asic_type;
> > -       hwmgr->feature_mask = adev->powerplay.pp_feature;
> > +       hwmgr->feature_mask = adev->pp_feature;
> >         hwmgr->display_config = &adev->pm.pm_display_cfg;
> >         adev->powerplay.pp_handle = hwmgr;
> >         adev->powerplay.pp_funcs = &pp_dpm_funcs; diff --git 
> > a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > index 9cb45fe..fa0af71 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > @@ -290,6 +290,9 @@ static int smu_set_funcs(struct amdgpu_device
> > *adev)
> >
> >         switch (adev->asic_type) {
> >         case CHIP_VEGA20:
> > +               smu->feature_mask &= ~PP_GFXOFF_MASK;
> > +               if (smu->feature_mask & PP_OVERDRIVE_MASK)
> > +                       smu->od_enabled = true;
> >                 smu_v11_0_set_smu_funcs(smu);
> >                 break;
> >         default:
> > @@ -306,6 +309,7 @@ static int smu_early_init(void *handle)
> >
> >         smu->adev = adev;
> >         mutex_init(&smu->mutex);
> > +       smu->feature_mask = adev->pp_feature;
> >
> >         return smu_set_funcs(adev);
> >  }
> > diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> > b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> > index 00ef6f1..8c7eac9 100644
> > --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> > +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> > @@ -384,6 +384,7 @@ struct smu_context
> >         uint32_t pstate_sclk;
> >         uint32_t pstate_mclk;
> >
> > +       bool od_enabled;
> >         uint32_t power_limit;
> >         uint32_t default_power_limit;
> >
> > @@ -399,6 +400,8 @@ struct smu_context
> >         uint32_t workload_setting[WORKLOAD_POLICY_MAX];
> >         uint32_t power_profile_mode;
> >         uint32_t default_power_profile_mode;
> > +
> > +       uint32_t feature_mask;
> >  };
> >
> >  struct pptable_funcs {
> > --
> > 2.7.4
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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