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[193.116.74.175]) by smtp.gmail.com with ESMTPSA id u28sm3571864pgn.32.2019.03.02.19.34.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 02 Mar 2019 19:34:42 -0800 (PST) Date: Sun, 03 Mar 2019 13:34:36 +1000 From: Nicholas Piggin Subject: Re: [PATCH 01/20] asm-generic/mmiowb: Add generic implementation of mmiowb() tracking To: Linus Torvalds Cc: Andrea Parri , Arnd Bergmann , Benjamin Herrenschmidt , Rich Felker , David Howells , Daniel Lustig , linux-arch , Linux List Kernel Mailing , "Maciej W. Rozycki" , Ingo Molnar , Michael Ellerman , Palmer Dabbelt , Paul Burton , "Paul E. McKenney" , Peter Zijlstra , Alan Stern , Tony Luck , Will Deacon , Yoshinori Sato References: <20190301140348.25175-1-will.deacon@arm.com> <20190301140348.25175-2-will.deacon@arm.com> <1551575210.6lwpiqtg5k.astroid@bobo.none> In-Reply-To: MIME-Version: 1.0 User-Agent: astroid/0.14.0 (https://github.com/astroidmail/astroid) Message-Id: <1551583190.duzqnmfnvg.astroid@bobo.none> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Linus Torvalds's on March 3, 2019 12:18 pm: > On Sat, Mar 2, 2019 at 5:43 PM Nicholas Piggin wrote: >> >> Is there a reason to call this "mmiowb"? We already have wmb that >> orders cacheable stores vs mmio stores don't we? >=20 > Sadly no it doesn't. Not on ia64, and people tried to make that the > new rule because of the platform breakage on what some people thought > would be a major platform. Let me try this again, because I was babbling a train of thought=20 continuing from my past mails on the subject. Kill mmiowb with fire. It was added for a niche platform that hasn't been produced for 10 years for a CPU ISA that is no longer being developed. Let's make mb/wmb great again (aka actually possible for normal people to understand). If something comes along again that reorders mmios from different CPUs=20 in the IO controller like the Altix did, they implement wmb the slow and=20 correct way. They can add a new faster primitive for the few devices=20 they care about in the couple of perf critical places that matter. It doesn't have to be done all at once with this series, obviously this=20 is a big improvement on its own. But why perpetuate the nomenclature and concept for new code added now?=20 Thanks, Nick = From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nicholas Piggin Subject: Re: [PATCH 01/20] asm-generic/mmiowb: Add generic implementation of mmiowb() tracking Date: Sun, 03 Mar 2019 13:34:36 +1000 Message-ID: <1551583190.duzqnmfnvg.astroid@bobo.none> References: <20190301140348.25175-1-will.deacon@arm.com> <20190301140348.25175-2-will.deacon@arm.com> <1551575210.6lwpiqtg5k.astroid@bobo.none> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Linus Torvalds Cc: Andrea Parri , Arnd Bergmann , Benjamin Herrenschmidt , Rich Felker , David Howells , Daniel Lustig , linux-arch , Linux List Kernel Mailing , "Maciej W. Rozycki" , Ingo Molnar , Michael Ellerman , Palmer Dabbelt , Paul Burton , "Paul E. McKenney" , Peter Zijlstra , Alan Stern , Tony Luck , Will Deacon , Yoshinori Sato List-Id: linux-arch.vger.kernel.org Linus Torvalds's on March 3, 2019 12:18 pm: > On Sat, Mar 2, 2019 at 5:43 PM Nicholas Piggin wrote: >> >> Is there a reason to call this "mmiowb"? We already have wmb that >> orders cacheable stores vs mmio stores don't we? >=20 > Sadly no it doesn't. Not on ia64, and people tried to make that the > new rule because of the platform breakage on what some people thought > would be a major platform. Let me try this again, because I was babbling a train of thought=20 continuing from my past mails on the subject. Kill mmiowb with fire. It was added for a niche platform that hasn't been produced for 10 years for a CPU ISA that is no longer being developed. Let's make mb/wmb great again (aka actually possible for normal people to understand). If something comes along again that reorders mmios from different CPUs=20 in the IO controller like the Altix did, they implement wmb the slow and=20 correct way. They can add a new faster primitive for the few devices=20 they care about in the couple of perf critical places that matter. It doesn't have to be done all at once with this series, obviously this=20 is a big improvement on its own. But why perpetuate the nomenclature and concept for new code added now?=20 Thanks, Nick =