From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 061ABC4360F for ; Tue, 5 Mar 2019 06:42:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D33992075B for ; Tue, 5 Mar 2019 06:42:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726792AbfCEGmj (ORCPT ); Tue, 5 Mar 2019 01:42:39 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:53016 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725782AbfCEGmi (ORCPT ); Tue, 5 Mar 2019 01:42:38 -0500 X-UUID: 24e9eab555344d77abf5a25844de455f-20190305 X-UUID: 24e9eab555344d77abf5a25844de455f-20190305 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 112004511; Tue, 05 Mar 2019 14:42:27 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 5 Mar 2019 14:42:25 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 5 Mar 2019 14:42:25 +0800 Message-ID: <1551768145.22671.1.camel@mtksdaap41> Subject: Re: [PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate From: James Liao To: Weiyi Lu CC: Nicolas Boichat , Matthias Brugger , Stephen Boyd , Rob Herring , Fan Chen , , , , , , , Owen Chen Date: Tue, 5 Mar 2019 14:42:25 +0800 In-Reply-To: <20190305050546.23431-3-weiyi.lu@mediatek.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-3-weiyi.lu@mediatek.com> Content-Type: text/plain; charset="us-ascii" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: C84D10F38310784DA96446CFCF9CA963D6BE97A12C44D0C6035461A6235BDDC02000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote: > From: Owen Chen > > PLLs with tuner_en bit, such as APLL1, need to disable > tuner_en before apply new frequency settings, or the new frequency > settings (pcw) will not be applied. > The tuner_en bit will be disabled during changing PLL rate > and be restored after new settings applied. > > Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support) > Cc: > Signed-off-by: Owen Chen > Signed-off-by: Weiyi Lu Reviewed-by: James Liao > --- > drivers/clk/mediatek/clk-pll.c | 48 ++++++++++++++++++++++++---------- > 1 file changed, 34 insertions(+), 14 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index f54e4015b0b1..18842d660317 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c > @@ -88,6 +88,32 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, > return ((unsigned long)vco + postdiv - 1) / postdiv; > } > > +static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) > +{ > + u32 r; > + > + if (pll->tuner_en_addr) { > + r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); > + writel(r, pll->tuner_en_addr); > + } else if (pll->tuner_addr) { > + r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; > + writel(r, pll->tuner_addr); > + } > +} > + > +static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll) > +{ > + u32 r; > + > + if (pll->tuner_en_addr) { > + r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); > + writel(r, pll->tuner_en_addr); > + } else if (pll->tuner_addr) { > + r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; > + writel(r, pll->tuner_addr); > + } > +} > + > static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > int postdiv) > { > @@ -96,6 +122,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; > > + /* disable tuner */ > + __mtk_pll_tuner_disable(pll); > + > /* set postdiv */ > val = readl(pll->pd_addr); > val &= ~(POSTDIV_MASK << pll->data->pd_shift); > @@ -122,6 +151,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > if (pll->tuner_addr) > writel(con1 + 1, pll->tuner_addr); > > + /* restore tuner_en */ > + __mtk_pll_tuner_enable(pll); > + > if (pll_en) > udelay(20); > } > @@ -228,13 +260,7 @@ static int mtk_pll_prepare(struct clk_hw *hw) > r |= pll->data->en_mask; > writel(r, pll->base_addr + REG_CON0); > > - if (pll->tuner_en_addr) { > - r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); > - writel(r, pll->tuner_en_addr); > - } else if (pll->tuner_addr) { > - r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; > - writel(r, pll->tuner_addr); > - } > + __mtk_pll_tuner_enable(pll); > > udelay(20); > > @@ -258,13 +284,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw) > writel(r, pll->base_addr + REG_CON0); > } > > - if (pll->tuner_en_addr) { > - r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); > - writel(r, pll->tuner_en_addr); > - } else if (pll->tuner_addr) { > - r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; > - writel(r, pll->tuner_addr); > - } > + __mtk_pll_tuner_disable(pll); > > r = readl(pll->base_addr + REG_CON0); > r &= ~CON0_BASE_EN; From mboxrd@z Thu Jan 1 00:00:00 1970 From: James Liao Subject: Re: [PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate Date: Tue, 5 Mar 2019 14:42:25 +0800 Message-ID: <1551768145.22671.1.camel@mtksdaap41> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-3-weiyi.lu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190305050546.23431-3-weiyi.lu@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org To: Weiyi Lu Cc: Nicolas Boichat , Matthias Brugger , Stephen Boyd , Rob Herring , Fan Chen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, srv_heupstream@mediatek.com, stable@vger.kernel.org, Owen Chen List-Id: linux-mediatek@lists.infradead.org On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote: > From: Owen Chen > > PLLs with tuner_en bit, such as APLL1, need to disable > tuner_en before apply new frequency settings, or the new frequency > settings (pcw) will not be applied. > The tuner_en bit will be disabled during changing PLL rate > and be restored after new settings applied. > > Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support) > Cc: > Signed-off-by: Owen Chen > Signed-off-by: Weiyi Lu Reviewed-by: James Liao > --- > drivers/clk/mediatek/clk-pll.c | 48 ++++++++++++++++++++++++---------- > 1 file changed, 34 insertions(+), 14 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index f54e4015b0b1..18842d660317 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c > @@ -88,6 +88,32 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, > return ((unsigned long)vco + postdiv - 1) / postdiv; > } > > +static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) > +{ > + u32 r; > + > + if (pll->tuner_en_addr) { > + r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); > + writel(r, pll->tuner_en_addr); > + } else if (pll->tuner_addr) { > + r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; > + writel(r, pll->tuner_addr); > + } > +} > + > +static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll) > +{ > + u32 r; > + > + if (pll->tuner_en_addr) { > + r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); > + writel(r, pll->tuner_en_addr); > + } else if (pll->tuner_addr) { > + r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; > + writel(r, pll->tuner_addr); > + } > +} > + > static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > int postdiv) > { > @@ -96,6 +122,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; > > + /* disable tuner */ > + __mtk_pll_tuner_disable(pll); > + > /* set postdiv */ > val = readl(pll->pd_addr); > val &= ~(POSTDIV_MASK << pll->data->pd_shift); > @@ -122,6 +151,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > if (pll->tuner_addr) > writel(con1 + 1, pll->tuner_addr); > > + /* restore tuner_en */ > + __mtk_pll_tuner_enable(pll); > + > if (pll_en) > udelay(20); > } > @@ -228,13 +260,7 @@ static int mtk_pll_prepare(struct clk_hw *hw) > r |= pll->data->en_mask; > writel(r, pll->base_addr + REG_CON0); > > - if (pll->tuner_en_addr) { > - r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); > - writel(r, pll->tuner_en_addr); > - } else if (pll->tuner_addr) { > - r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; > - writel(r, pll->tuner_addr); > - } > + __mtk_pll_tuner_enable(pll); > > udelay(20); > > @@ -258,13 +284,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw) > writel(r, pll->base_addr + REG_CON0); > } > > - if (pll->tuner_en_addr) { > - r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); > - writel(r, pll->tuner_en_addr); > - } else if (pll->tuner_addr) { > - r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; > - writel(r, pll->tuner_addr); > - } > + __mtk_pll_tuner_disable(pll); > > r = readl(pll->base_addr + REG_CON0); > r &= ~CON0_BASE_EN; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD4ECC43381 for ; Tue, 5 Mar 2019 06:42:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7B6592075B for ; Tue, 5 Mar 2019 06:42:57 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Tue, 5 Mar 2019 14:42:25 +0800 Message-ID: <1551768145.22671.1.camel@mtksdaap41> Subject: Re: [PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate From: James Liao To: Weiyi Lu Date: Tue, 5 Mar 2019 14:42:25 +0800 In-Reply-To: <20190305050546.23431-3-weiyi.lu@mediatek.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-3-weiyi.lu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: C84D10F38310784DA96446CFCF9CA963D6BE97A12C44D0C6035461A6235BDDC02000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190304_224241_518768_D164AEB1 X-CRM114-Status: GOOD ( 16.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Nicolas Boichat , srv_heupstream@mediatek.com, Stephen Boyd , linux-kernel@vger.kernel.org, stable@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Matthias Brugger , Owen Chen , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote: > From: Owen Chen > > PLLs with tuner_en bit, such as APLL1, need to disable > tuner_en before apply new frequency settings, or the new frequency > settings (pcw) will not be applied. > The tuner_en bit will be disabled during changing PLL rate > and be restored after new settings applied. > > Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support) > Cc: > Signed-off-by: Owen Chen > Signed-off-by: Weiyi Lu Reviewed-by: James Liao > --- > drivers/clk/mediatek/clk-pll.c | 48 ++++++++++++++++++++++++---------- > 1 file changed, 34 insertions(+), 14 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index f54e4015b0b1..18842d660317 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c > @@ -88,6 +88,32 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, > return ((unsigned long)vco + postdiv - 1) / postdiv; > } > > +static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) > +{ > + u32 r; > + > + if (pll->tuner_en_addr) { > + r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); > + writel(r, pll->tuner_en_addr); > + } else if (pll->tuner_addr) { > + r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; > + writel(r, pll->tuner_addr); > + } > +} > + > +static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll) > +{ > + u32 r; > + > + if (pll->tuner_en_addr) { > + r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); > + writel(r, pll->tuner_en_addr); > + } else if (pll->tuner_addr) { > + r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; > + writel(r, pll->tuner_addr); > + } > +} > + > static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > int postdiv) > { > @@ -96,6 +122,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; > > + /* disable tuner */ > + __mtk_pll_tuner_disable(pll); > + > /* set postdiv */ > val = readl(pll->pd_addr); > val &= ~(POSTDIV_MASK << pll->data->pd_shift); > @@ -122,6 +151,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > if (pll->tuner_addr) > writel(con1 + 1, pll->tuner_addr); > > + /* restore tuner_en */ > + __mtk_pll_tuner_enable(pll); > + > if (pll_en) > udelay(20); > } > @@ -228,13 +260,7 @@ static int mtk_pll_prepare(struct clk_hw *hw) > r |= pll->data->en_mask; > writel(r, pll->base_addr + REG_CON0); > > - if (pll->tuner_en_addr) { > - r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); > - writel(r, pll->tuner_en_addr); > - } else if (pll->tuner_addr) { > - r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; > - writel(r, pll->tuner_addr); > - } > + __mtk_pll_tuner_enable(pll); > > udelay(20); > > @@ -258,13 +284,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw) > writel(r, pll->base_addr + REG_CON0); > } > > - if (pll->tuner_en_addr) { > - r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); > - writel(r, pll->tuner_en_addr); > - } else if (pll->tuner_addr) { > - r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; > - writel(r, pll->tuner_addr); > - } > + __mtk_pll_tuner_disable(pll); > > r = readl(pll->base_addr + REG_CON0); > r &= ~CON0_BASE_EN; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel