From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1A97C10F0C for ; Tue, 5 Mar 2019 06:43:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9144320842 for ; Tue, 5 Mar 2019 06:43:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726852AbfCEGnZ (ORCPT ); Tue, 5 Mar 2019 01:43:25 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:52931 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725782AbfCEGnZ (ORCPT ); Tue, 5 Mar 2019 01:43:25 -0500 X-UUID: a60c86442dbf4d0cb4693c6eb414b268-20190305 X-UUID: a60c86442dbf4d0cb4693c6eb414b268-20190305 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1892553686; Tue, 05 Mar 2019 14:43:03 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 5 Mar 2019 14:43:01 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 5 Mar 2019 14:43:01 +0800 Message-ID: <1551768181.22671.2.camel@mtksdaap41> Subject: Re: [PATCH v5 2/9] clk: mediatek: Add new clkmux register API From: James Liao To: Weiyi Lu CC: Nicolas Boichat , Matthias Brugger , Stephen Boyd , Rob Herring , Fan Chen , , , , , , , Owen Chen Date: Tue, 5 Mar 2019 14:43:01 +0800 In-Reply-To: <20190305050546.23431-4-weiyi.lu@mediatek.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-4-weiyi.lu@mediatek.com> Content-Type: text/plain; charset="us-ascii" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote: > From: Owen Chen > > On both MT8183 & MT6765, there add "set/clr" register for > each clkmux setting, and one update register to trigger value change. > It is designed to prevent read-modify-write racing issue. > The sw design need to add a new API to handle this hw change with > a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h". > > Signed-off-by: Owen Chen > Signed-off-by: Weiyi Lu Reviewed-by: James Liao > --- > drivers/clk/mediatek/Makefile | 3 +- > drivers/clk/mediatek/clk-mux.c | 223 +++++++++++++++++++++++++++++++++ > drivers/clk/mediatek/clk-mux.h | 89 +++++++++++++ > 3 files changed, 314 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/mediatek/clk-mux.c > create mode 100644 drivers/clk/mediatek/clk-mux.h > > diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile > index ee4410ff43ab..20cf9eea4171 100644 > --- a/drivers/clk/mediatek/Makefile > +++ b/drivers/clk/mediatek/Makefile > @@ -1,5 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > -obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o > +obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o > + > obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o > obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o > obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o > diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c > new file mode 100644 > index 000000000000..877a883fa616 > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mux.c > @@ -0,0 +1,223 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Owen Chen > + */ > + > +#include > +#include > +#include > +#include > + > +#include "clk-mtk.h" > +#include "clk-mux.h" > + > +static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw) > +{ > + return container_of(hw, struct mtk_clk_mux, hw); > +} > + > +static int mtk_clk_mux_enable(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = BIT(mux->data->gate_shift); > + > + return regmap_update_bits(mux->regmap, mux->data->mux_ofs, > + mask, ~mask); > +} > + > +static void mtk_clk_mux_disable(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = BIT(mux->data->gate_shift); > + > + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask); > +} > + > +static int mtk_clk_mux_enable_setclr(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + > + return regmap_write(mux->regmap, mux->data->clr_ofs, > + BIT(mux->data->gate_shift)); > +} > + > +static void mtk_clk_mux_disable_setclr(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + > + regmap_write(mux->regmap, mux->data->set_ofs, > + BIT(mux->data->gate_shift)); > +} > + > +static int mtk_clk_mux_is_enabled(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 val; > + > + regmap_read(mux->regmap, mux->data->mux_ofs, &val); > + > + return (val & BIT(mux->data->gate_shift)) == 0; > +} > + > +static u8 mtk_clk_mux_get_parent(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > + u32 val; > + > + regmap_read(mux->regmap, mux->data->mux_ofs, &val); > + val = (val >> mux->data->mux_shift) & mask; > + > + return val; > +} > + > +static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > + unsigned long flags; > + > + if (mux->lock) > + spin_lock_irqsave(mux->lock, flags); > + else > + __acquire(mux->lock); > + > + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, > + index << mux->data->mux_shift); > + > + if (mux->lock) > + spin_unlock_irqrestore(mux->lock, flags); > + else > + __release(mux->lock); > + > + return 0; > +} > + > +static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > + u32 val, orig; > + unsigned long flags; > + > + if (mux->lock) > + spin_lock_irqsave(mux->lock, flags); > + else > + __acquire(mux->lock); > + > + regmap_read(mux->regmap, mux->data->mux_ofs, &orig); > + val = (orig & ~(mask << mux->data->mux_shift)) > + | (index << mux->data->mux_shift); > + > + if (val != orig) { > + regmap_write(mux->regmap, mux->data->clr_ofs, > + mask << mux->data->mux_shift); > + regmap_write(mux->regmap, mux->data->set_ofs, > + index << mux->data->mux_shift); > + > + if (mux->data->upd_shift >= 0) > + regmap_write(mux->regmap, mux->data->upd_ofs, > + BIT(mux->data->upd_shift)); > + } > + > + if (mux->lock) > + spin_unlock_irqrestore(mux->lock, flags); > + else > + __release(mux->lock); > + > + return 0; > +} > + > +const struct clk_ops mtk_mux_ops = { > + .get_parent = mtk_clk_mux_get_parent, > + .set_parent = mtk_clk_mux_set_parent_lock, > +}; > + > +const struct clk_ops mtk_mux_clr_set_upd_ops = { > + .get_parent = mtk_clk_mux_get_parent, > + .set_parent = mtk_clk_mux_set_parent_setclr_lock, > +}; > + > +const struct clk_ops mtk_mux_gate_ops = { > + .enable = mtk_clk_mux_enable, > + .disable = mtk_clk_mux_disable, > + .is_enabled = mtk_clk_mux_is_enabled, > + .get_parent = mtk_clk_mux_get_parent, > + .set_parent = mtk_clk_mux_set_parent_lock, > +}; > + > +const struct clk_ops mtk_mux_gate_clr_set_upd_ops = { > + .enable = mtk_clk_mux_enable_setclr, > + .disable = mtk_clk_mux_disable_setclr, > + .is_enabled = mtk_clk_mux_is_enabled, > + .get_parent = mtk_clk_mux_get_parent, > + .set_parent = mtk_clk_mux_set_parent_setclr_lock, > +}; > + > +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, > + struct regmap *regmap, > + spinlock_t *lock) > +{ > + struct mtk_clk_mux *clk_mux; > + struct clk_init_data init; > + struct clk *clk; > + > + clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL); > + if (!clk_mux) > + return ERR_PTR(-ENOMEM); > + > + init.name = mux->name; > + init.flags = mux->flags | CLK_SET_RATE_PARENT; > + init.parent_names = mux->parent_names; > + init.num_parents = mux->num_parents; > + init.ops = mux->ops; > + > + clk_mux->regmap = regmap; > + clk_mux->data = mux; > + clk_mux->lock = lock; > + clk_mux->hw.init = &init; > + > + clk = clk_register(NULL, &clk_mux->hw); > + if (IS_ERR(clk)) { > + kfree(clk_mux); > + return clk; > + } > + > + return clk; > +} > + > +int mtk_clk_register_muxes(const struct mtk_mux *muxes, > + int num, struct device_node *node, > + spinlock_t *lock, > + struct clk_onecell_data *clk_data) > +{ > + struct regmap *regmap; > + struct clk *clk; > + int i; > + > + regmap = syscon_node_to_regmap(node); > + if (IS_ERR(regmap)) { > + pr_err("Cannot find regmap for %pOF: %ld\n", node, > + PTR_ERR(regmap)); > + return PTR_ERR(regmap); > + } > + > + for (i = 0; i < num; i++) { > + const struct mtk_mux *mux = &muxes[i]; > + > + if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) { > + clk = mtk_clk_register_mux(mux, regmap, lock); > + > + if (IS_ERR(clk)) { > + pr_err("Failed to register clk %s: %ld\n", > + mux->name, PTR_ERR(clk)); > + continue; > + } > + > + clk_data->clks[mux->id] = clk; > + } > + } > + > + return 0; > +} > diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h > new file mode 100644 > index 000000000000..f5625f4d9e6c > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mux.h > @@ -0,0 +1,89 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Owen Chen > + */ > + > +#ifndef __DRV_CLK_MTK_MUX_H > +#define __DRV_CLK_MTK_MUX_H > + > +#include > + > +struct mtk_clk_mux { > + struct clk_hw hw; > + struct regmap *regmap; > + const struct mtk_mux *data; > + spinlock_t *lock; > +}; > + > +struct mtk_mux { > + int id; > + const char *name; > + const char * const *parent_names; > + unsigned int flags; > + > + u32 mux_ofs; > + u32 set_ofs; > + u32 clr_ofs; > + u32 upd_ofs; > + > + u8 mux_shift; > + u8 mux_width; > + u8 gate_shift; > + s8 upd_shift; > + > + const struct clk_ops *ops; > + > + signed char num_parents; > +}; > + > +extern const struct clk_ops mtk_mux_ops; > +extern const struct clk_ops mtk_mux_clr_set_upd_ops; > +extern const struct clk_ops mtk_mux_gate_ops; > +extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; > + > +#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _gate, _upd_ofs, _upd, _flags, _ops) { \ > + .id = _id, \ > + .name = _name, \ > + .mux_ofs = _mux_ofs, \ > + .set_ofs = _mux_set_ofs, \ > + .clr_ofs = _mux_clr_ofs, \ > + .upd_ofs = _upd_ofs, \ > + .mux_shift = _shift, \ > + .mux_width = _width, \ > + .gate_shift = _gate, \ > + .upd_shift = _upd, \ > + .parent_names = _parents, \ > + .num_parents = ARRAY_SIZE(_parents), \ > + .flags = _flags, \ > + .ops = &_ops, \ > + } > + > +#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _gate, _upd_ofs, _upd, _flags) \ > + GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _gate, _upd_ofs, _upd, _flags, \ > + mtk_mux_gate_clr_set_upd_ops) > + > +#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _gate, _upd_ofs, _upd) \ > + MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ > + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \ > + _width, _gate, _upd_ofs, _upd, \ > + CLK_SET_RATE_PARENT) > + > +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, > + struct regmap *regmap, > + spinlock_t *lock); > + > +int mtk_clk_register_muxes(const struct mtk_mux *muxes, > + int num, struct device_node *node, > + spinlock_t *lock, > + struct clk_onecell_data *clk_data); > + > +#endif /* __DRV_CLK_MTK_MUX_H */ From mboxrd@z Thu Jan 1 00:00:00 1970 From: James Liao Subject: Re: [PATCH v5 2/9] clk: mediatek: Add new clkmux register API Date: Tue, 5 Mar 2019 14:43:01 +0800 Message-ID: <1551768181.22671.2.camel@mtksdaap41> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-4-weiyi.lu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190305050546.23431-4-weiyi.lu@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Weiyi Lu Cc: Rob Herring , Nicolas Boichat , srv_heupstream@mediatek.com, Stephen Boyd , linux-kernel@vger.kernel.org, stable@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Matthias Brugger , Owen Chen , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote: > From: Owen Chen > > On both MT8183 & MT6765, there add "set/clr" register for > each clkmux setting, and one update register to trigger value change. > It is designed to prevent read-modify-write racing issue. > The sw design need to add a new API to handle this hw change with > a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h". > > Signed-off-by: Owen Chen > Signed-off-by: Weiyi Lu Reviewed-by: James Liao > --- > drivers/clk/mediatek/Makefile | 3 +- > drivers/clk/mediatek/clk-mux.c | 223 +++++++++++++++++++++++++++++++++ > drivers/clk/mediatek/clk-mux.h | 89 +++++++++++++ > 3 files changed, 314 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/mediatek/clk-mux.c > create mode 100644 drivers/clk/mediatek/clk-mux.h > > diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile > index ee4410ff43ab..20cf9eea4171 100644 > --- a/drivers/clk/mediatek/Makefile > +++ b/drivers/clk/mediatek/Makefile > @@ -1,5 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > -obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o > +obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o > + > obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o > obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o > obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o > diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c > new file mode 100644 > index 000000000000..877a883fa616 > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mux.c > @@ -0,0 +1,223 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Owen Chen > + */ > + > +#include > +#include > +#include > +#include > + > +#include "clk-mtk.h" > +#include "clk-mux.h" > + > +static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw) > +{ > + return container_of(hw, struct mtk_clk_mux, hw); > +} > + > +static int mtk_clk_mux_enable(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = BIT(mux->data->gate_shift); > + > + return regmap_update_bits(mux->regmap, mux->data->mux_ofs, > + mask, ~mask); > +} > + > +static void mtk_clk_mux_disable(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = BIT(mux->data->gate_shift); > + > + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask); > +} > + > +static int mtk_clk_mux_enable_setclr(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + > + return regmap_write(mux->regmap, mux->data->clr_ofs, > + BIT(mux->data->gate_shift)); > +} > + > +static void mtk_clk_mux_disable_setclr(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + > + regmap_write(mux->regmap, mux->data->set_ofs, > + BIT(mux->data->gate_shift)); > +} > + > +static int mtk_clk_mux_is_enabled(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 val; > + > + regmap_read(mux->regmap, mux->data->mux_ofs, &val); > + > + return (val & BIT(mux->data->gate_shift)) == 0; > +} > + > +static u8 mtk_clk_mux_get_parent(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > + u32 val; > + > + regmap_read(mux->regmap, mux->data->mux_ofs, &val); > + val = (val >> mux->data->mux_shift) & mask; > + > + return val; > +} > + > +static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > + unsigned long flags; > + > + if (mux->lock) > + spin_lock_irqsave(mux->lock, flags); > + else > + __acquire(mux->lock); > + > + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, > + index << mux->data->mux_shift); > + > + if (mux->lock) > + spin_unlock_irqrestore(mux->lock, flags); > + else > + __release(mux->lock); > + > + return 0; > +} > + > +static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > + u32 val, orig; > + unsigned long flags; > + > + if (mux->lock) > + spin_lock_irqsave(mux->lock, flags); > + else > + __acquire(mux->lock); > + > + regmap_read(mux->regmap, mux->data->mux_ofs, &orig); > + val = (orig & ~(mask << mux->data->mux_shift)) > + | (index << mux->data->mux_shift); > + > + if (val != orig) { > + regmap_write(mux->regmap, mux->data->clr_ofs, > + mask << mux->data->mux_shift); > + regmap_write(mux->regmap, mux->data->set_ofs, > + index << mux->data->mux_shift); > + > + if (mux->data->upd_shift >= 0) > + regmap_write(mux->regmap, mux->data->upd_ofs, > + BIT(mux->data->upd_shift)); > + } > + > + if (mux->lock) > + spin_unlock_irqrestore(mux->lock, flags); > + else > + __release(mux->lock); > + > + return 0; > +} > + > +const struct clk_ops mtk_mux_ops = { > + .get_parent = mtk_clk_mux_get_parent, > + .set_parent = mtk_clk_mux_set_parent_lock, > +}; > + > +const struct clk_ops mtk_mux_clr_set_upd_ops = { > + .get_parent = mtk_clk_mux_get_parent, > + .set_parent = mtk_clk_mux_set_parent_setclr_lock, > +}; > + > +const struct clk_ops mtk_mux_gate_ops = { > + .enable = mtk_clk_mux_enable, > + .disable = mtk_clk_mux_disable, > + .is_enabled = mtk_clk_mux_is_enabled, > + .get_parent = mtk_clk_mux_get_parent, > + .set_parent = mtk_clk_mux_set_parent_lock, > +}; > + > +const struct clk_ops mtk_mux_gate_clr_set_upd_ops = { > + .enable = mtk_clk_mux_enable_setclr, > + .disable = mtk_clk_mux_disable_setclr, > + .is_enabled = mtk_clk_mux_is_enabled, > + .get_parent = mtk_clk_mux_get_parent, > + .set_parent = mtk_clk_mux_set_parent_setclr_lock, > +}; > + > +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, > + struct regmap *regmap, > + spinlock_t *lock) > +{ > + struct mtk_clk_mux *clk_mux; > + struct clk_init_data init; > + struct clk *clk; > + > + clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL); > + if (!clk_mux) > + return ERR_PTR(-ENOMEM); > + > + init.name = mux->name; > + init.flags = mux->flags | CLK_SET_RATE_PARENT; > + init.parent_names = mux->parent_names; > + init.num_parents = mux->num_parents; > + init.ops = mux->ops; > + > + clk_mux->regmap = regmap; > + clk_mux->data = mux; > + clk_mux->lock = lock; > + clk_mux->hw.init = &init; > + > + clk = clk_register(NULL, &clk_mux->hw); > + if (IS_ERR(clk)) { > + kfree(clk_mux); > + return clk; > + } > + > + return clk; > +} > + > +int mtk_clk_register_muxes(const struct mtk_mux *muxes, > + int num, struct device_node *node, > + spinlock_t *lock, > + struct clk_onecell_data *clk_data) > +{ > + struct regmap *regmap; > + struct clk *clk; > + int i; > + > + regmap = syscon_node_to_regmap(node); > + if (IS_ERR(regmap)) { > + pr_err("Cannot find regmap for %pOF: %ld\n", node, > + PTR_ERR(regmap)); > + return PTR_ERR(regmap); > + } > + > + for (i = 0; i < num; i++) { > + const struct mtk_mux *mux = &muxes[i]; > + > + if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) { > + clk = mtk_clk_register_mux(mux, regmap, lock); > + > + if (IS_ERR(clk)) { > + pr_err("Failed to register clk %s: %ld\n", > + mux->name, PTR_ERR(clk)); > + continue; > + } > + > + clk_data->clks[mux->id] = clk; > + } > + } > + > + return 0; > +} > diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h > new file mode 100644 > index 000000000000..f5625f4d9e6c > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mux.h > @@ -0,0 +1,89 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Owen Chen > + */ > + > +#ifndef __DRV_CLK_MTK_MUX_H > +#define __DRV_CLK_MTK_MUX_H > + > +#include > + > +struct mtk_clk_mux { > + struct clk_hw hw; > + struct regmap *regmap; > + const struct mtk_mux *data; > + spinlock_t *lock; > +}; > + > +struct mtk_mux { > + int id; > + const char *name; > + const char * const *parent_names; > + unsigned int flags; > + > + u32 mux_ofs; > + u32 set_ofs; > + u32 clr_ofs; > + u32 upd_ofs; > + > + u8 mux_shift; > + u8 mux_width; > + u8 gate_shift; > + s8 upd_shift; > + > + const struct clk_ops *ops; > + > + signed char num_parents; > +}; > + > +extern const struct clk_ops mtk_mux_ops; > +extern const struct clk_ops mtk_mux_clr_set_upd_ops; > +extern const struct clk_ops mtk_mux_gate_ops; > +extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; > + > +#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _gate, _upd_ofs, _upd, _flags, _ops) { \ > + .id = _id, \ > + .name = _name, \ > + .mux_ofs = _mux_ofs, \ > + .set_ofs = _mux_set_ofs, \ > + .clr_ofs = _mux_clr_ofs, \ > + .upd_ofs = _upd_ofs, \ > + .mux_shift = _shift, \ > + .mux_width = _width, \ > + .gate_shift = _gate, \ > + .upd_shift = _upd, \ > + .parent_names = _parents, \ > + .num_parents = ARRAY_SIZE(_parents), \ > + .flags = _flags, \ > + .ops = &_ops, \ > + } > + > +#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _gate, _upd_ofs, _upd, _flags) \ > + GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _gate, _upd_ofs, _upd, _flags, \ > + mtk_mux_gate_clr_set_upd_ops) > + > +#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _gate, _upd_ofs, _upd) \ > + MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ > + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \ > + _width, _gate, _upd_ofs, _upd, \ > + CLK_SET_RATE_PARENT) > + > +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, > + struct regmap *regmap, > + spinlock_t *lock); > + > +int mtk_clk_register_muxes(const struct mtk_mux *muxes, > + int num, struct device_node *node, > + spinlock_t *lock, > + struct clk_onecell_data *clk_data); > + > +#endif /* __DRV_CLK_MTK_MUX_H */ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA8CEC43381 for ; Tue, 5 Mar 2019 06:43:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B922E2075B for ; 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Tue, 5 Mar 2019 14:43:01 +0800 Message-ID: <1551768181.22671.2.camel@mtksdaap41> Subject: Re: [PATCH v5 2/9] clk: mediatek: Add new clkmux register API From: James Liao To: Weiyi Lu Date: Tue, 5 Mar 2019 14:43:01 +0800 In-Reply-To: <20190305050546.23431-4-weiyi.lu@mediatek.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-4-weiyi.lu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190304_224314_229879_FD706DBC X-CRM114-Status: GOOD ( 19.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Nicolas Boichat , srv_heupstream@mediatek.com, Stephen Boyd , linux-kernel@vger.kernel.org, stable@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Matthias Brugger , Owen Chen , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote: > From: Owen Chen > > On both MT8183 & MT6765, there add "set/clr" register for > each clkmux setting, and one update register to trigger value change. > It is designed to prevent read-modify-write racing issue. > The sw design need to add a new API to handle this hw change with > a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h". > > Signed-off-by: Owen Chen > Signed-off-by: Weiyi Lu Reviewed-by: James Liao > --- > drivers/clk/mediatek/Makefile | 3 +- > drivers/clk/mediatek/clk-mux.c | 223 +++++++++++++++++++++++++++++++++ > drivers/clk/mediatek/clk-mux.h | 89 +++++++++++++ > 3 files changed, 314 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/mediatek/clk-mux.c > create mode 100644 drivers/clk/mediatek/clk-mux.h > > diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile > index ee4410ff43ab..20cf9eea4171 100644 > --- a/drivers/clk/mediatek/Makefile > +++ b/drivers/clk/mediatek/Makefile > @@ -1,5 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > -obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o > +obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o > + > obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o > obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o > obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o > diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c > new file mode 100644 > index 000000000000..877a883fa616 > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mux.c > @@ -0,0 +1,223 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Owen Chen > + */ > + > +#include > +#include > +#include > +#include > + > +#include "clk-mtk.h" > +#include "clk-mux.h" > + > +static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw) > +{ > + return container_of(hw, struct mtk_clk_mux, hw); > +} > + > +static int mtk_clk_mux_enable(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = BIT(mux->data->gate_shift); > + > + return regmap_update_bits(mux->regmap, mux->data->mux_ofs, > + mask, ~mask); > +} > + > +static void mtk_clk_mux_disable(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = BIT(mux->data->gate_shift); > + > + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask); > +} > + > +static int mtk_clk_mux_enable_setclr(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + > + return regmap_write(mux->regmap, mux->data->clr_ofs, > + BIT(mux->data->gate_shift)); > +} > + > +static void mtk_clk_mux_disable_setclr(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + > + regmap_write(mux->regmap, mux->data->set_ofs, > + BIT(mux->data->gate_shift)); > +} > + > +static int mtk_clk_mux_is_enabled(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 val; > + > + regmap_read(mux->regmap, mux->data->mux_ofs, &val); > + > + return (val & BIT(mux->data->gate_shift)) == 0; > +} > + > +static u8 mtk_clk_mux_get_parent(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > + u32 val; > + > + regmap_read(mux->regmap, mux->data->mux_ofs, &val); > + val = (val >> mux->data->mux_shift) & mask; > + > + return val; > +} > + > +static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > + unsigned long flags; > + > + if (mux->lock) > + spin_lock_irqsave(mux->lock, flags); > + else > + __acquire(mux->lock); > + > + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, > + index << mux->data->mux_shift); > + > + if (mux->lock) > + spin_unlock_irqrestore(mux->lock, flags); > + else > + __release(mux->lock); > + > + return 0; > +} > + > +static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index) > +{ > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); > + u32 mask = GENMASK(mux->data->mux_width - 1, 0); > + u32 val, orig; > + unsigned long flags; > + > + if (mux->lock) > + spin_lock_irqsave(mux->lock, flags); > + else > + __acquire(mux->lock); > + > + regmap_read(mux->regmap, mux->data->mux_ofs, &orig); > + val = (orig & ~(mask << mux->data->mux_shift)) > + | (index << mux->data->mux_shift); > + > + if (val != orig) { > + regmap_write(mux->regmap, mux->data->clr_ofs, > + mask << mux->data->mux_shift); > + regmap_write(mux->regmap, mux->data->set_ofs, > + index << mux->data->mux_shift); > + > + if (mux->data->upd_shift >= 0) > + regmap_write(mux->regmap, mux->data->upd_ofs, > + BIT(mux->data->upd_shift)); > + } > + > + if (mux->lock) > + spin_unlock_irqrestore(mux->lock, flags); > + else > + __release(mux->lock); > + > + return 0; > +} > + > +const struct clk_ops mtk_mux_ops = { > + .get_parent = mtk_clk_mux_get_parent, > + .set_parent = mtk_clk_mux_set_parent_lock, > +}; > + > +const struct clk_ops mtk_mux_clr_set_upd_ops = { > + .get_parent = mtk_clk_mux_get_parent, > + .set_parent = mtk_clk_mux_set_parent_setclr_lock, > +}; > + > +const struct clk_ops mtk_mux_gate_ops = { > + .enable = mtk_clk_mux_enable, > + .disable = mtk_clk_mux_disable, > + .is_enabled = mtk_clk_mux_is_enabled, > + .get_parent = mtk_clk_mux_get_parent, > + .set_parent = mtk_clk_mux_set_parent_lock, > +}; > + > +const struct clk_ops mtk_mux_gate_clr_set_upd_ops = { > + .enable = mtk_clk_mux_enable_setclr, > + .disable = mtk_clk_mux_disable_setclr, > + .is_enabled = mtk_clk_mux_is_enabled, > + .get_parent = mtk_clk_mux_get_parent, > + .set_parent = mtk_clk_mux_set_parent_setclr_lock, > +}; > + > +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, > + struct regmap *regmap, > + spinlock_t *lock) > +{ > + struct mtk_clk_mux *clk_mux; > + struct clk_init_data init; > + struct clk *clk; > + > + clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL); > + if (!clk_mux) > + return ERR_PTR(-ENOMEM); > + > + init.name = mux->name; > + init.flags = mux->flags | CLK_SET_RATE_PARENT; > + init.parent_names = mux->parent_names; > + init.num_parents = mux->num_parents; > + init.ops = mux->ops; > + > + clk_mux->regmap = regmap; > + clk_mux->data = mux; > + clk_mux->lock = lock; > + clk_mux->hw.init = &init; > + > + clk = clk_register(NULL, &clk_mux->hw); > + if (IS_ERR(clk)) { > + kfree(clk_mux); > + return clk; > + } > + > + return clk; > +} > + > +int mtk_clk_register_muxes(const struct mtk_mux *muxes, > + int num, struct device_node *node, > + spinlock_t *lock, > + struct clk_onecell_data *clk_data) > +{ > + struct regmap *regmap; > + struct clk *clk; > + int i; > + > + regmap = syscon_node_to_regmap(node); > + if (IS_ERR(regmap)) { > + pr_err("Cannot find regmap for %pOF: %ld\n", node, > + PTR_ERR(regmap)); > + return PTR_ERR(regmap); > + } > + > + for (i = 0; i < num; i++) { > + const struct mtk_mux *mux = &muxes[i]; > + > + if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) { > + clk = mtk_clk_register_mux(mux, regmap, lock); > + > + if (IS_ERR(clk)) { > + pr_err("Failed to register clk %s: %ld\n", > + mux->name, PTR_ERR(clk)); > + continue; > + } > + > + clk_data->clks[mux->id] = clk; > + } > + } > + > + return 0; > +} > diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h > new file mode 100644 > index 000000000000..f5625f4d9e6c > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mux.h > @@ -0,0 +1,89 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Owen Chen > + */ > + > +#ifndef __DRV_CLK_MTK_MUX_H > +#define __DRV_CLK_MTK_MUX_H > + > +#include > + > +struct mtk_clk_mux { > + struct clk_hw hw; > + struct regmap *regmap; > + const struct mtk_mux *data; > + spinlock_t *lock; > +}; > + > +struct mtk_mux { > + int id; > + const char *name; > + const char * const *parent_names; > + unsigned int flags; > + > + u32 mux_ofs; > + u32 set_ofs; > + u32 clr_ofs; > + u32 upd_ofs; > + > + u8 mux_shift; > + u8 mux_width; > + u8 gate_shift; > + s8 upd_shift; > + > + const struct clk_ops *ops; > + > + signed char num_parents; > +}; > + > +extern const struct clk_ops mtk_mux_ops; > +extern const struct clk_ops mtk_mux_clr_set_upd_ops; > +extern const struct clk_ops mtk_mux_gate_ops; > +extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; > + > +#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _gate, _upd_ofs, _upd, _flags, _ops) { \ > + .id = _id, \ > + .name = _name, \ > + .mux_ofs = _mux_ofs, \ > + .set_ofs = _mux_set_ofs, \ > + .clr_ofs = _mux_clr_ofs, \ > + .upd_ofs = _upd_ofs, \ > + .mux_shift = _shift, \ > + .mux_width = _width, \ > + .gate_shift = _gate, \ > + .upd_shift = _upd, \ > + .parent_names = _parents, \ > + .num_parents = ARRAY_SIZE(_parents), \ > + .flags = _flags, \ > + .ops = &_ops, \ > + } > + > +#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _gate, _upd_ofs, _upd, _flags) \ > + GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _gate, _upd_ofs, _upd, _flags, \ > + mtk_mux_gate_clr_set_upd_ops) > + > +#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _gate, _upd_ofs, _upd) \ > + MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ > + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \ > + _width, _gate, _upd_ofs, _upd, \ > + CLK_SET_RATE_PARENT) > + > +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, > + struct regmap *regmap, > + spinlock_t *lock); > + > +int mtk_clk_register_muxes(const struct mtk_mux *muxes, > + int num, struct device_node *node, > + spinlock_t *lock, > + struct clk_onecell_data *clk_data); > + > +#endif /* __DRV_CLK_MTK_MUX_H */ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel