From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BC45C43381 for ; Tue, 5 Mar 2019 06:48:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D71F220842 for ; Tue, 5 Mar 2019 06:48:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727077AbfCEGsT (ORCPT ); Tue, 5 Mar 2019 01:48:19 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:25642 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725782AbfCEGsT (ORCPT ); Tue, 5 Mar 2019 01:48:19 -0500 X-UUID: 11b64de2bb8b4993a089caa2fbe7f9c7-20190305 X-UUID: 11b64de2bb8b4993a089caa2fbe7f9c7-20190305 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 862671918; Tue, 05 Mar 2019 14:48:11 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 5 Mar 2019 14:48:09 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 5 Mar 2019 14:48:09 +0800 Message-ID: <1551768489.22671.6.camel@mtksdaap41> Subject: Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off From: James Liao To: Weiyi Lu CC: Nicolas Boichat , Matthias Brugger , Stephen Boyd , Rob Herring , Fan Chen , , , , , , Date: Tue, 5 Mar 2019 14:48:09 +0800 In-Reply-To: <20190305050546.23431-11-weiyi.lu@mediatek.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-11-weiyi.lu@mediatek.com> Content-Type: text/plain; charset="us-ascii" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: D3F8F38F3EC0752BE607BE7487D1CA55696D4ED0C9B57A0CCD88AC5ED3BFA9A22000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote: > From: James Liao > > Some modules may need to change its clock rate before turn on it. > So changing PLL's rate when it is off should be allowed. > This patch removes PLL enabled check before set rate, so that > PLLs can set new frequency even if they are off. > > On MT8173 for example, ARMPLL's enable bit can be controlled by > other HW. That means ARMPLL may be turned on even if we (CPU / SW) > set ARMPLL's enable bit as 0. In this case, SW may want and can > still change ARMPLL's rate by changing its pcw and postdiv settings. > But without this patch, new pcw setting will not be applied because > its enable bit is 0. > > Signed-off-by: James Liao > Acked-by: Michael Turquette > Signed-off-by: Weiyi Lu Reviewed-by: James Liao > --- > drivers/clk/mediatek/clk-pll.c | 13 ++----------- > 1 file changed, 2 insertions(+), 11 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index 65cee1d6c400..8d556fc99fed 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c > @@ -124,9 +124,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > int postdiv) > { > u32 chg, val; > - int pll_en; > - > - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; > > /* disable tuner */ > __mtk_pll_tuner_disable(pll); > @@ -147,12 +144,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > pll->data->pcw_shift); > val |= pcw << pll->data->pcw_shift; > writel(val, pll->pcw_addr); > - > - chg = readl(pll->pcw_chg_addr); > - > - if (pll_en) > - chg |= PCW_CHG_MASK; > - > + chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; > writel(chg, pll->pcw_chg_addr); > if (pll->tuner_addr) > writel(val + 1, pll->tuner_addr); > @@ -160,8 +152,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > /* restore tuner_en */ > __mtk_pll_tuner_enable(pll); > > - if (pll_en) > - udelay(20); > + udelay(20); > } > > /* From mboxrd@z Thu Jan 1 00:00:00 1970 From: James Liao Subject: Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off Date: Tue, 5 Mar 2019 14:48:09 +0800 Message-ID: <1551768489.22671.6.camel@mtksdaap41> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-11-weiyi.lu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190305050546.23431-11-weiyi.lu@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org To: Weiyi Lu Cc: Nicolas Boichat , Matthias Brugger , Stephen Boyd , Rob Herring , Fan Chen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, srv_heupstream@mediatek.com, stable@vger.kernel.org List-Id: linux-mediatek@lists.infradead.org On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote: > From: James Liao > > Some modules may need to change its clock rate before turn on it. > So changing PLL's rate when it is off should be allowed. > This patch removes PLL enabled check before set rate, so that > PLLs can set new frequency even if they are off. > > On MT8173 for example, ARMPLL's enable bit can be controlled by > other HW. That means ARMPLL may be turned on even if we (CPU / SW) > set ARMPLL's enable bit as 0. In this case, SW may want and can > still change ARMPLL's rate by changing its pcw and postdiv settings. > But without this patch, new pcw setting will not be applied because > its enable bit is 0. > > Signed-off-by: James Liao > Acked-by: Michael Turquette > Signed-off-by: Weiyi Lu Reviewed-by: James Liao > --- > drivers/clk/mediatek/clk-pll.c | 13 ++----------- > 1 file changed, 2 insertions(+), 11 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index 65cee1d6c400..8d556fc99fed 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c > @@ -124,9 +124,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > int postdiv) > { > u32 chg, val; > - int pll_en; > - > - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; > > /* disable tuner */ > __mtk_pll_tuner_disable(pll); > @@ -147,12 +144,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > pll->data->pcw_shift); > val |= pcw << pll->data->pcw_shift; > writel(val, pll->pcw_addr); > - > - chg = readl(pll->pcw_chg_addr); > - > - if (pll_en) > - chg |= PCW_CHG_MASK; > - > + chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; > writel(chg, pll->pcw_chg_addr); > if (pll->tuner_addr) > writel(val + 1, pll->tuner_addr); > @@ -160,8 +152,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > /* restore tuner_en */ > __mtk_pll_tuner_enable(pll); > > - if (pll_en) > - udelay(20); > + udelay(20); > } > > /* From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74F74C43381 for ; Tue, 5 Mar 2019 06:48:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3FC162075B for ; Tue, 5 Mar 2019 06:48:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="G5dQdo1C" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3FC162075B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KLC3MGZuWmZyDNpNq6slQyldOHqxDviWaEEBGW0KPDI=; b=G5dQdo1CRFjOqr F8B88ulH8pEOv+7QakXdwf989hmEPWdlQoCKmAeMts9XAZWQxbUHyn5hw28vZe+9a7NNrhEBpGMcj Y0X7hb7FDq0rieXLbyUVBPKJ27BMHa8mLoNM2rOy2cWT4YwhJJk7mlnZAo3YWRUrzkRY0vGeTsJfV D3TUbPGa7/1OI4Mmt86h9aFhb2wHlGG7zhxAla2WXALXa+rN7nk3zE7ZeDhNjV6zXrBu8XjeZnDWi sb+hUrmAmyVRNN/HDjC7nrdC2SdYY42jIupfUP6xsNNX7LbBeOc1eU2JLh1p45ses9eTwfhPOROOD WqyNbeiN4iBmhBDOFvDg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h13sL-0000sC-Lj; Tue, 05 Mar 2019 06:48:29 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h13sI-0000rl-Ls; Tue, 05 Mar 2019 06:48:28 +0000 X-UUID: 64bf88c58c9d4ea291f59ad3a3038970-20190304 X-UUID: 64bf88c58c9d4ea291f59ad3a3038970-20190304 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 498035218; Mon, 04 Mar 2019 22:48:19 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 4 Mar 2019 22:48:18 -0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 5 Mar 2019 14:48:09 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 5 Mar 2019 14:48:09 +0800 Message-ID: <1551768489.22671.6.camel@mtksdaap41> Subject: Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off From: James Liao To: Weiyi Lu Date: Tue, 5 Mar 2019 14:48:09 +0800 In-Reply-To: <20190305050546.23431-11-weiyi.lu@mediatek.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-11-weiyi.lu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: D3F8F38F3EC0752BE607BE7487D1CA55696D4ED0C9B57A0CCD88AC5ED3BFA9A22000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190304_224826_716606_D632FEB4 X-CRM114-Status: GOOD ( 16.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Nicolas Boichat , srv_heupstream@mediatek.com, Stephen Boyd , linux-kernel@vger.kernel.org, stable@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote: > From: James Liao > > Some modules may need to change its clock rate before turn on it. > So changing PLL's rate when it is off should be allowed. > This patch removes PLL enabled check before set rate, so that > PLLs can set new frequency even if they are off. > > On MT8173 for example, ARMPLL's enable bit can be controlled by > other HW. That means ARMPLL may be turned on even if we (CPU / SW) > set ARMPLL's enable bit as 0. In this case, SW may want and can > still change ARMPLL's rate by changing its pcw and postdiv settings. > But without this patch, new pcw setting will not be applied because > its enable bit is 0. > > Signed-off-by: James Liao > Acked-by: Michael Turquette > Signed-off-by: Weiyi Lu Reviewed-by: James Liao > --- > drivers/clk/mediatek/clk-pll.c | 13 ++----------- > 1 file changed, 2 insertions(+), 11 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index 65cee1d6c400..8d556fc99fed 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c > @@ -124,9 +124,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > int postdiv) > { > u32 chg, val; > - int pll_en; > - > - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; > > /* disable tuner */ > __mtk_pll_tuner_disable(pll); > @@ -147,12 +144,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > pll->data->pcw_shift); > val |= pcw << pll->data->pcw_shift; > writel(val, pll->pcw_addr); > - > - chg = readl(pll->pcw_chg_addr); > - > - if (pll_en) > - chg |= PCW_CHG_MASK; > - > + chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; > writel(chg, pll->pcw_chg_addr); > if (pll->tuner_addr) > writel(val + 1, pll->tuner_addr); > @@ -160,8 +152,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > /* restore tuner_en */ > __mtk_pll_tuner_enable(pll); > > - if (pll_en) > - udelay(20); > + udelay(20); > } > > /* _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel