From: Joyce Kong <joyce.kong@arm.com>
To: dev@dpdk.org
Cc: nd@arm.com, jerinj@marvell.com, konstantin.ananyev@intel.com,
chaozhu@linux.vnet.ibm.com, bruce.richardson@intel.com,
thomas@monjalon.net, hemant.agrawal@nxp.com,
honnappa.nagarahalli@arm.com, gavin.hu@arm.com, stable@dpdk.org
Subject: [PATCH v5 1/3] rwlock: reimplement with atomic builtins
Date: Mon, 25 Mar 2019 17:14:57 +0800 [thread overview]
Message-ID: <1553505299-34459-2-git-send-email-joyce.kong@arm.com> (raw)
In-Reply-To: <1553505299-34459-1-git-send-email-joyce.kong@arm.com>
In-Reply-To: <1544672265-219262-2-git-send-email-joyce.kong@arm.com>
The __sync builtin based implementation generates full memory
barriers ('dmb ish') on Arm platforms. Using C11 atomic builtins
to generate one way barriers.
Here is the assembly code of __sync_compare_and_swap builtin.
__sync_bool_compare_and_swap(dst, exp, src);
0x000000000090f1b0 <+16>: e0 07 40 f9 ldr x0, [sp, #8]
0x000000000090f1b4 <+20>: e1 0f 40 79 ldrh w1, [sp, #6]
0x000000000090f1b8 <+24>: e2 0b 40 79 ldrh w2, [sp, #4]
0x000000000090f1bc <+28>: 21 3c 00 12 and w1, w1, #0xffff
0x000000000090f1c0 <+32>: 03 7c 5f 48 ldxrh w3, [x0]
0x000000000090f1c4 <+36>: 7f 00 01 6b cmp w3, w1
0x000000000090f1c8 <+40>: 61 00 00 54 b.ne 0x90f1d4
<rte_atomic16_cmpset+52> // b.any
0x000000000090f1cc <+44>: 02 fc 04 48 stlxrh w4, w2, [x0]
0x000000000090f1d0 <+48>: 84 ff ff 35 cbnz w4, 0x90f1c0
<rte_atomic16_cmpset+32>
0x000000000090f1d4 <+52>: bf 3b 03 d5 dmb ish
0x000000000090f1d8 <+56>: e0 17 9f 1a cset w0, eq // eq = none
Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Signed-off-by: Joyce Kong <joyce.kong@arm.com>
Tested-by: Joyce Kong <joyce.kong@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
---
lib/librte_eal/common/include/generic/rte_rwlock.h | 29 +++++++++++-----------
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/lib/librte_eal/common/include/generic/rte_rwlock.h b/lib/librte_eal/common/include/generic/rte_rwlock.h
index b05d85a..31608fa 100644
--- a/lib/librte_eal/common/include/generic/rte_rwlock.h
+++ b/lib/librte_eal/common/include/generic/rte_rwlock.h
@@ -64,14 +64,14 @@ rte_rwlock_read_lock(rte_rwlock_t *rwl)
int success = 0;
while (success == 0) {
- x = rwl->cnt;
+ x = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED);
/* write lock is held */
if (x < 0) {
rte_pause();
continue;
}
- success = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt,
- (uint32_t)x, (uint32_t)(x + 1));
+ success = __atomic_compare_exchange_n(&rwl->cnt, &x, x + 1, 1,
+ __ATOMIC_ACQUIRE, __ATOMIC_RELAXED);
}
}
@@ -95,13 +95,14 @@ rte_rwlock_read_trylock(rte_rwlock_t *rwl)
int success = 0;
while (success == 0) {
- x = rwl->cnt;
+ x = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED);
/* write lock is held */
if (x < 0)
return -EBUSY;
- success = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt,
- (uint32_t)x, (uint32_t)(x + 1));
+ success = __atomic_compare_exchange_n(&rwl->cnt, &x, x + 1, 1,
+ __ATOMIC_ACQUIRE, __ATOMIC_RELAXED);
}
+
return 0;
}
@@ -114,7 +115,7 @@ rte_rwlock_read_trylock(rte_rwlock_t *rwl)
static inline void
rte_rwlock_read_unlock(rte_rwlock_t *rwl)
{
- rte_atomic32_dec((rte_atomic32_t *)(intptr_t)&rwl->cnt);
+ __atomic_fetch_sub(&rwl->cnt, 1, __ATOMIC_RELEASE);
}
/**
@@ -135,9 +136,9 @@ rte_rwlock_write_trylock(rte_rwlock_t *rwl)
{
int32_t x;
- x = rwl->cnt;
- if (x != 0 || rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt,
- 0, (uint32_t)-1) == 0)
+ x = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED);
+ if (x != 0 || __atomic_compare_exchange_n(&rwl->cnt, &x, -1, 1,
+ __ATOMIC_ACQUIRE, __ATOMIC_RELAXED) == 0)
return -EBUSY;
return 0;
@@ -156,14 +157,14 @@ rte_rwlock_write_lock(rte_rwlock_t *rwl)
int success = 0;
while (success == 0) {
- x = rwl->cnt;
+ x = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED);
/* a lock is held */
if (x != 0) {
rte_pause();
continue;
}
- success = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt,
- 0, (uint32_t)-1);
+ success = __atomic_compare_exchange_n(&rwl->cnt, &x, -1, 1,
+ __ATOMIC_ACQUIRE, __ATOMIC_RELAXED);
}
}
@@ -176,7 +177,7 @@ rte_rwlock_write_lock(rte_rwlock_t *rwl)
static inline void
rte_rwlock_write_unlock(rte_rwlock_t *rwl)
{
- rte_atomic32_inc((rte_atomic32_t *)(intptr_t)&rwl->cnt);
+ __atomic_store_n(&rwl->cnt, 0, __ATOMIC_RELEASE);
}
/**
--
2.7.4
next prev parent reply other threads:[~2019-03-25 9:14 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-13 3:37 [PATCH v1 0/2] reimplement rwlock and add relevant perf test case Joyce Kong
2018-12-13 3:37 ` [PATCH v1 1/2] test/rwlock: add " Joyce Kong
2018-12-19 23:34 ` Ananyev, Konstantin
2018-12-20 1:01 ` Gavin Hu (Arm Technology China)
2018-12-20 1:45 ` Honnappa Nagarahalli
2019-03-14 13:15 ` [PATCH v3 0/3] rwlock: reimplement rwlock with atomic and add relevant " Joyce Kong
2019-03-14 13:15 ` [PATCH v3 1/3] rwlock: reimplement with atomic builtins Joyce Kong
2019-03-14 15:54 ` Stephen Hemminger
2019-03-15 3:04 ` Gavin Hu (Arm Technology China)
2019-03-15 11:41 ` Ananyev, Konstantin
2019-03-19 8:31 ` Gavin Hu (Arm Technology China)
2019-03-14 13:15 ` [PATCH v3 2/3] test/rwlock: add perf test case on all available cores Joyce Kong
2019-03-14 13:15 ` [PATCH v3 3/3] test/rwlock: amortize the cost of getting time Joyce Kong
2019-03-14 15:02 ` Honnappa Nagarahalli
2019-03-20 6:25 ` [PATCH v4 0/3] rwlock: reimplement rwlock with atomic and add relevant perf test case Joyce Kong
2019-03-20 6:25 ` [PATCH v4 1/3] rwlock: reimplement with atomic builtins Joyce Kong
2019-03-21 18:43 ` Ananyev, Konstantin
2019-03-25 9:18 ` Joyce Kong (Arm Technology China)
2019-03-20 6:25 ` [PATCH v4 2/3] test/rwlock: add perf test case on all available cores Joyce Kong
2019-03-21 18:44 ` Ananyev, Konstantin
2019-03-20 6:25 ` [PATCH v4 3/3] test/rwlock: amortize the cost of getting time Joyce Kong
2019-03-21 18:44 ` Ananyev, Konstantin
2019-03-25 9:14 ` [PATCH v5 0/3] rwlock: reimplement rwlock with atomic and add relevant perf test case Joyce Kong
2019-03-28 10:50 ` Thomas Monjalon
2019-04-16 14:57 ` [dpdk-dev] " Kevin Traynor
2019-03-25 9:14 ` Joyce Kong [this message]
2019-03-25 9:14 ` [PATCH v5 2/3] test/rwlock: add perf test case on all available cores Joyce Kong
2019-03-25 9:14 ` [PATCH v5 3/3] test/rwlock: amortize the cost of getting time Joyce Kong
2018-12-13 3:37 ` [PATCH v1 2/2] rwlock: reimplement with __atomic builtins Joyce Kong
2018-12-19 23:50 ` Ananyev, Konstantin
2018-12-13 5:27 ` [PATCH v1 0/2] reimplement rwlock and add relevant perf test case Stephen Hemminger
2018-12-14 1:30 ` Gavin Hu (Arm Technology China)
2018-12-17 5:16 ` Honnappa Nagarahalli
2018-12-19 20:37 ` Thomas Monjalon
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