From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4EA7C10F14 for ; Thu, 11 Apr 2019 20:24:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7D4C32146F for ; Thu, 11 Apr 2019 20:24:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1555014289; bh=GsDACCpTfbqWGhETI7YmHBIAv/urcICvhgOGv/4krgk=; h=In-Reply-To:References:From:Subject:Cc:To:Date:List-ID:From; b=ufKTTwF1/sNXRJnwCcdsnjHbxO3nvrKlktSYgmpkwLtpyb2pmIZXgKOQB5LKga/Ls th7tEz+Mi5kOhajuU2jyWbJuWxcIzrk3O7CgvSjEdojd4hVHKnASw06+r2/ULPRH+9 SLcMkDbfr8yry01aSJdeANpJw2q3D/itTwGWwuGI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726931AbfDKUYs (ORCPT ); Thu, 11 Apr 2019 16:24:48 -0400 Received: from mail.kernel.org ([198.145.29.99]:49112 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726630AbfDKUYr (ORCPT ); Thu, 11 Apr 2019 16:24:47 -0400 Received: from localhost (unknown [104.132.0.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2863220850; Thu, 11 Apr 2019 20:24:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1555014287; bh=GsDACCpTfbqWGhETI7YmHBIAv/urcICvhgOGv/4krgk=; h=In-Reply-To:References:From:Subject:Cc:To:Date:From; b=zGtvcjEAeyjT4nd0T/gkCn1CrDeSOTRjEPADy3OdVSMa8MaL4o7sb0XNg2aXPRcNn HnnFuwgHsaYpXjuQ78hE2lFD3qP4q0/+vHorPYiCxIiCfWiBjQf7PW1onjYZyiSIju lHZf46UYnJYCbwzr/F/Den62rBJiRq497hJoniOg= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20190305050546.23431-11-weiyi.lu@mediatek.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-11-weiyi.lu@mediatek.com> From: Stephen Boyd Subject: Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off Cc: James Liao , Fan Chen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, srv_heupstream@mediatek.com, stable@vger.kernel.org, Weiyi Lu To: Matthias Brugger , Nicolas Boichat , Rob Herring , Stephen Boyd , Weiyi Lu Message-ID: <155501428642.20095.13010940386938154148@swboyd.mtv.corp.google.com> User-Agent: alot/0.8 Date: Thu, 11 Apr 2019 13:24:46 -0700 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Weiyi Lu (2019-03-04 21:05:46) > From: James Liao >=20 > Some modules may need to change its clock rate before turn on it. > So changing PLL's rate when it is off should be allowed. > This patch removes PLL enabled check before set rate, so that > PLLs can set new frequency even if they are off. >=20 > On MT8173 for example, ARMPLL's enable bit can be controlled by > other HW. That means ARMPLL may be turned on even if we (CPU / SW) > set ARMPLL's enable bit as 0. In this case, SW may want and can > still change ARMPLL's rate by changing its pcw and postdiv settings. > But without this patch, new pcw setting will not be applied because > its enable bit is 0. >=20 > Signed-off-by: James Liao > Acked-by: Michael Turquette > Signed-off-by: Weiyi Lu > --- Applied to clk-next From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off Date: Thu, 11 Apr 2019 13:24:46 -0700 Message-ID: <155501428642.20095.13010940386938154148@swboyd.mtv.corp.google.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-11-weiyi.lu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20190305050546.23431-11-weiyi.lu@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org To: Matthias Brugger , Nicolas Boichat , Rob Herring , Stephen Boyd Cc: James Liao , Fan Chen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, srv_heupstream@mediatek.com, stable@vger.kernel.org, Weiyi Lu List-Id: linux-mediatek@lists.infradead.org Quoting Weiyi Lu (2019-03-04 21:05:46) > From: James Liao >=20 > Some modules may need to change its clock rate before turn on it. > So changing PLL's rate when it is off should be allowed. > This patch removes PLL enabled check before set rate, so that > PLLs can set new frequency even if they are off. >=20 > On MT8173 for example, ARMPLL's enable bit can be controlled by > other HW. That means ARMPLL may be turned on even if we (CPU / SW) > set ARMPLL's enable bit as 0. In this case, SW may want and can > still change ARMPLL's rate by changing its pcw and postdiv settings. > But without this patch, new pcw setting will not be applied because > its enable bit is 0. >=20 > Signed-off-by: James Liao > Acked-by: Michael Turquette > Signed-off-by: Weiyi Lu > --- Applied to clk-next From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4E41C10F14 for ; Thu, 11 Apr 2019 20:24:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B2E102146F for ; Thu, 11 Apr 2019 20:24:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="CexuHUz4"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="zGtvcjEA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B2E102146F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Date:Message-ID:To:Subject:From: References:In-Reply-To:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zvkiyk+nwt/Jhd5hO1oV+5xBLWDR7bsQUA8fkur453g=; b=CexuHUz4R5uaxV gYPYQQ4dohlI5M80v9xye8/YKDRUHAZ/Nvdkyjr4xzMW+qNJ9DhVuWcpuexnLdAMUdvbVSxKUphp/ 2ehLlZulMMJSMSpKJdmOjEhy6PrU/pHyAnAuEAMJH7ZsIj/HzLsfObSOcmINec8MJkHGWdmNRAOLM 3PIaMnmSDb/7qggk/Tf0vmk9pIMwFGmdB2dn+TTRauUNQ7zM7viBEfI/fqp9QBJ1Duu/RGp56MYLw kakXtRYgD4AvhW8NThqPPlG75YFipzK5ORW1pXgcgmlYLjVKa3U98/RIwTjp3sDf5ByRvAAaYJ1MP +QPny/X5/dm82wZ5y0wQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEgFf-0008HZ-39; Thu, 11 Apr 2019 20:24:51 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEgFb-0008Gz-Gk; Thu, 11 Apr 2019 20:24:48 +0000 Received: from localhost (unknown [104.132.0.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2863220850; Thu, 11 Apr 2019 20:24:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1555014287; bh=GsDACCpTfbqWGhETI7YmHBIAv/urcICvhgOGv/4krgk=; h=In-Reply-To:References:From:Subject:Cc:To:Date:From; b=zGtvcjEAeyjT4nd0T/gkCn1CrDeSOTRjEPADy3OdVSMa8MaL4o7sb0XNg2aXPRcNn HnnFuwgHsaYpXjuQ78hE2lFD3qP4q0/+vHorPYiCxIiCfWiBjQf7PW1onjYZyiSIju lHZf46UYnJYCbwzr/F/Den62rBJiRq497hJoniOg= MIME-Version: 1.0 In-Reply-To: <20190305050546.23431-11-weiyi.lu@mediatek.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-11-weiyi.lu@mediatek.com> From: Stephen Boyd Subject: Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off To: Matthias Brugger , Nicolas Boichat , Rob Herring , Stephen Boyd , Weiyi Lu Message-ID: <155501428642.20095.13010940386938154148@swboyd.mtv.corp.google.com> User-Agent: alot/0.8 Date: Thu, 11 Apr 2019 13:24:46 -0700 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190411_132447_568389_C207F306 X-CRM114-Status: UNSURE ( 8.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Quoting Weiyi Lu (2019-03-04 21:05:46) > From: James Liao > > Some modules may need to change its clock rate before turn on it. > So changing PLL's rate when it is off should be allowed. > This patch removes PLL enabled check before set rate, so that > PLLs can set new frequency even if they are off. > > On MT8173 for example, ARMPLL's enable bit can be controlled by > other HW. That means ARMPLL may be turned on even if we (CPU / SW) > set ARMPLL's enable bit as 0. In this case, SW may want and can > still change ARMPLL's rate by changing its pcw and postdiv settings. > But without this patch, new pcw setting will not be applied because > its enable bit is 0. > > Signed-off-by: James Liao > Acked-by: Michael Turquette > Signed-off-by: Weiyi Lu > --- Applied to clk-next _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel