From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11A08C282DA for ; Wed, 17 Apr 2019 21:44:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D7720217D7 for ; Wed, 17 Apr 2019 21:44:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387550AbfDQVmX (ORCPT ); Wed, 17 Apr 2019 17:42:23 -0400 Received: from mga12.intel.com ([192.55.52.136]:20150 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387475AbfDQVmV (ORCPT ); Wed, 17 Apr 2019 17:42:21 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Apr 2019 14:42:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,363,1549958400"; d="scan'208";a="224441163" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by orsmga001.jf.intel.com with ESMTP; 17 Apr 2019 14:42:20 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v7 09/21] x86/split_lock: Define MSR TEST_CTL register Date: Wed, 17 Apr 2019 14:33:59 -0700 Message-Id: <1555536851-17462-10-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1555536851-17462-1-git-send-email-fenghua.yu@intel.com> References: <1555536851-17462-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org Setting bit 29 in MSR TEST_CTL (0x33) enables split lock detection and clearing the bit disables split lock detection. Define the MSR and the bit. The definitions will be used in enabling or disabling split lock detection. Signed-off-by: Fenghua Yu --- arch/x86/include/asm/msr-index.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index f65ef6f783d2..296eeb761ab6 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -39,6 +39,10 @@ /* Intel MSRs. Some also available on other CPUs */ +#define MSR_TEST_CTL 0x00000033 +#define TEST_CTL_SPLIT_LOCK_DETECT_SHIFT 29 +#define TEST_CTL_SPLIT_LOCK_DETECT BIT(29) + #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ #define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ -- 2.19.1