From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ley Foon Tan Date: Fri, 10 May 2019 13:54:46 +0800 Subject: [U-Boot] [PATCH 12/14] arm: socfpga: agilex: Add SPL for Agilex SoC In-Reply-To: <1557467688-73706-1-git-send-email-ley.foon.tan@intel.com> References: <1557467688-73706-1-git-send-email-ley.foon.tan@intel.com> Message-ID: <1557467688-73706-13-git-send-email-ley.foon.tan@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Add SPL support for Agilex SoC. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/spl_agilex.c | 105 +++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 arch/arm/mach-socfpga/spl_agilex.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 51355ad070..476dcaefff 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -61,6 +61,7 @@ obj-y += spl_s10.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += ccu_agilex.o +obj-y += spl_agilex.o endif endif diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c new file mode 100644 index 0000000000..7f0551541a --- /dev/null +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_MMC_SUPPORT +u32 spl_boot_mode(const u32 boot_device) +{ +#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) + return MMCSD_MODE_FS; +#else + return MMCSD_MODE_RAW; +#endif +} +#endif + +void board_init_f(ulong dummy) +{ + const struct cm_config *cm_default_cfg = cm_get_default_config(); + int ret; + +#ifdef CONFIG_HW_WATCHDOG + /* Ensure watchdog is paused when debugging is happening */ + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg); + + /* Enable watchdog before initializing the HW */ + socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); + socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); + hw_watchdog_init(); +#endif + + /* ensure all processors are not released prior Linux boot */ + writeq(0, CPU_RELEASE_ADDR); + + socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); + timer_init(); + + sysmgr_pinmux_init(); + + /* configuring the HPS clocks */ + cm_basic_init(cm_default_cfg); + +#ifdef CONFIG_DEBUG_UART + socfpga_per_reset(SOCFPGA_RESET(UART0), 0); + debug_uart_init(); +#endif + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + cm_print_clock_quick_summary(); + + /* enable non-secure interface to DMA330 DMA and peripherals */ + writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma); + writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph); + + firewall_setup(); + ccu_init(); + +#if CONFIG_IS_ENABLED(ALTERA_SDRAM) + struct udevice *dev; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + hang(); + } +#endif + + mbox_init(); + +#ifdef CONFIG_CADENCE_QSPI + mbox_qspi_open(); +#endif +} -- 2.19.0