From mboxrd@z Thu Jan 1 00:00:00 1970 From: fabrizio.castro@bp.renesas.com (Fabrizio Castro) Date: Mon, 13 May 2019 16:37:11 +0100 Subject: [cip-dev] [PATCH 4.4.y 46/52] ARM: dts: r8a77470: Add SYS-DMAC support In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Message-ID: <1557761837-24993-47-git-send-email-fabrizio.castro@bp.renesas.com> To: cip-dev@lists.cip-project.org List-Id: cip-dev.lists.cip-project.org From: Biju Das commit 2e5775e3fd0667f7140a00748465af1c3d0aa5bb upstream. Describe SYS-DMAC0/1 in the R8A77470 device tree. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman [fab: reworked clocks and power-domains properties. Removed resets properties] Signed-off-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 1325dae..0daa451 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -196,6 +196,70 @@ reg = <0 0xe6300000 0 0x20000>; }; + dmac0: dma-controller at e6700000 { + compatible = "renesas,dmac-r8a77470", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A77470_CLK_SYS_DMAC0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller at e6720000 { + compatible = "renesas,dmac-r8a77470", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A77470_CLK_SYS_DMAC1>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <15>; + }; + scif0: serial at e6e60000 { compatible = "renesas,scif-r8a77470", "renesas,scif"; reg = <0 0xe6e60000 0 0x40>; -- 2.7.4