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bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org RnJvbTogQ2xhdWRpdSBCZXpuZWEgPGNsYXVkaXUuYmV6bmVhQG1pY3JvY2hpcC5jb20+DQoNCkRp ZmZlcmVudCBJUHMgdXNlcyBkaWZmZXJlbnQgYml0IG9mZnNldHMgaW4gcmVnaXN0ZXJzIGZvciB0 aGUgc2FtZQ0KZnVuY3Rpb25hbGl0eSwgdGh1cyBhZGFwdCB0aGUgZHJpdmVyIHRvIHN1cHBvcnQg dGhpcy4NCg0KU2lnbmVkLW9mZi1ieTogQ2xhdWRpdSBCZXpuZWEgPGNsYXVkaXUuYmV6bmVhQG1p Y3JvY2hpcC5jb20+DQotLS0NCiBkcml2ZXJzL2Nsay9hdDkxL3Nja2MuYyB8IDkzICsrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrLS0tLS0tLS0tLS0tLS0tLS0NCiAxIGZpbGUgY2hhbmdl ZCwgNjEgaW5zZXJ0aW9ucygrKSwgMzIgZGVsZXRpb25zKC0pDQoNCmRpZmYgLS1naXQgYS9kcml2 ZXJzL2Nsay9hdDkxL3Nja2MuYyBiL2RyaXZlcnMvY2xrL2F0OTEvc2NrYy5jDQppbmRleCA2YzU1 YTdhODZmNzkuLmFiMThiMWRhMjY5ZiAxMDA2NDQNCi0tLSBhL2RyaXZlcnMvY2xrL2F0OTEvc2Nr Yy5jDQorKysgYi9kcml2ZXJzL2Nsay9hdDkxL3Nja2MuYw0KQEAgLTIzLDE0ICsyMywxOCBAQA0K IAkJCQkgU0xPV19DTE9DS19GUkVRKQ0KIA0KICNkZWZpbmUJQVQ5MV9TQ0tDX0NSCQkJMHgwMA0K LSNkZWZpbmUJCUFUOTFfU0NLQ19SQ0VOCQkoMSA8PCAwKQ0KLSNkZWZpbmUJCUFUOTFfU0NLQ19P U0MzMkVOCSgxIDw8IDEpDQotI2RlZmluZQkJQVQ5MV9TQ0tDX09TQzMyQllQCSgxIDw8IDIpDQot I2RlZmluZQkJQVQ5MV9TQ0tDX09TQ1NFTAkoMSA8PCAzKQ0KKw0KK3N0cnVjdCBjbGtfc2xvd19i aXRzIHsNCisJdTMyIGNyX3JjZW47DQorCXUzMiBjcl9vc2MzMmVuOw0KKwl1MzIgY3Jfb3NjMzJi eXA7DQorCXUzMiBjcl9vc2NzZWw7DQorfTsNCiANCiBzdHJ1Y3QgY2xrX3Nsb3dfb3NjIHsNCiAJ c3RydWN0IGNsa19odyBodzsNCiAJdm9pZCBfX2lvbWVtICpzY2tjcjsNCisJY29uc3Qgc3RydWN0 IGNsa19zbG93X2JpdHMgKmJpdHM7DQogCXVuc2lnbmVkIGxvbmcgc3RhcnR1cF91c2VjOw0KIH07 DQogDQpAQCAtMzksNiArNDMsNyBAQCBzdHJ1Y3QgY2xrX3Nsb3dfb3NjIHsNCiBzdHJ1Y3QgY2xr X3NhbWE1ZDRfc2xvd19vc2Mgew0KIAlzdHJ1Y3QgY2xrX2h3IGh3Ow0KIAl2b2lkIF9faW9tZW0g KnNja2NyOw0KKwljb25zdCBzdHJ1Y3QgY2xrX3Nsb3dfYml0cyAqYml0czsNCiAJdW5zaWduZWQg bG9uZyBzdGFydHVwX3VzZWM7DQogCWJvb2wgcHJlcGFyZWQ7DQogfTsNCkBAIC00OCw2ICs1Myw3 IEBAIHN0cnVjdCBjbGtfc2FtYTVkNF9zbG93X29zYyB7DQogc3RydWN0IGNsa19zbG93X3JjX29z YyB7DQogCXN0cnVjdCBjbGtfaHcgaHc7DQogCXZvaWQgX19pb21lbSAqc2NrY3I7DQorCWNvbnN0 IHN0cnVjdCBjbGtfc2xvd19iaXRzICpiaXRzOw0KIAl1bnNpZ25lZCBsb25nIGZyZXF1ZW5jeTsN CiAJdW5zaWduZWQgbG9uZyBhY2N1cmFjeTsNCiAJdW5zaWduZWQgbG9uZyBzdGFydHVwX3VzZWM7 DQpAQCAtNTgsNiArNjQsNyBAQCBzdHJ1Y3QgY2xrX3Nsb3dfcmNfb3NjIHsNCiBzdHJ1Y3QgY2xr X3NhbTl4NV9zbG93IHsNCiAJc3RydWN0IGNsa19odyBodzsNCiAJdm9pZCBfX2lvbWVtICpzY2tj cjsNCisJY29uc3Qgc3RydWN0IGNsa19zbG93X2JpdHMgKmJpdHM7DQogCXU4IHBhcmVudDsNCiB9 Ow0KIA0KQEAgLTY5LDEwICs3NiwxMCBAQCBzdGF0aWMgaW50IGNsa19zbG93X29zY19wcmVwYXJl KHN0cnVjdCBjbGtfaHcgKmh3KQ0KIAl2b2lkIF9faW9tZW0gKnNja2NyID0gb3NjLT5zY2tjcjsN CiAJdTMyIHRtcCA9IHJlYWRsKHNja2NyKTsNCiANCi0JaWYgKHRtcCAmIChBVDkxX1NDS0NfT1ND MzJCWVAgfCBBVDkxX1NDS0NfT1NDMzJFTikpDQorCWlmICh0bXAgJiAob3NjLT5iaXRzLT5jcl9v c2MzMmJ5cCB8IG9zYy0+Yml0cy0+Y3Jfb3NjMzJlbikpDQogCQlyZXR1cm4gMDsNCiANCi0Jd3Jp dGVsKHRtcCB8IEFUOTFfU0NLQ19PU0MzMkVOLCBzY2tjcik7DQorCXdyaXRlbCh0bXAgfCBvc2Mt PmJpdHMtPmNyX29zYzMyZW4sIHNja2NyKTsNCiANCiAJdXNsZWVwX3JhbmdlKG9zYy0+c3RhcnR1 cF91c2VjLCBvc2MtPnN0YXJ0dXBfdXNlYyArIDEpOw0KIA0KQEAgLTg1LDEwICs5MiwxMCBAQCBz dGF0aWMgdm9pZCBjbGtfc2xvd19vc2NfdW5wcmVwYXJlKHN0cnVjdCBjbGtfaHcgKmh3KQ0KIAl2 b2lkIF9faW9tZW0gKnNja2NyID0gb3NjLT5zY2tjcjsNCiAJdTMyIHRtcCA9IHJlYWRsKHNja2Ny KTsNCiANCi0JaWYgKHRtcCAmIEFUOTFfU0NLQ19PU0MzMkJZUCkNCisJaWYgKHRtcCAmIG9zYy0+ Yml0cy0+Y3Jfb3NjMzJieXApDQogCQlyZXR1cm47DQogDQotCXdyaXRlbCh0bXAgJiB+QVQ5MV9T Q0tDX09TQzMyRU4sIHNja2NyKTsNCisJd3JpdGVsKHRtcCAmIH5vc2MtPmJpdHMtPmNyX29zYzMy ZW4sIHNja2NyKTsNCiB9DQogDQogc3RhdGljIGludCBjbGtfc2xvd19vc2NfaXNfcHJlcGFyZWQo c3RydWN0IGNsa19odyAqaHcpDQpAQCAtOTcsMTAgKzEwNCwxMCBAQCBzdGF0aWMgaW50IGNsa19z bG93X29zY19pc19wcmVwYXJlZChzdHJ1Y3QgY2xrX2h3ICpodykNCiAJdm9pZCBfX2lvbWVtICpz Y2tjciA9IG9zYy0+c2NrY3I7DQogCXUzMiB0bXAgPSByZWFkbChzY2tjcik7DQogDQotCWlmICh0 bXAgJiBBVDkxX1NDS0NfT1NDMzJCWVApDQorCWlmICh0bXAgJiBvc2MtPmJpdHMtPmNyX29zYzMy YnlwKQ0KIAkJcmV0dXJuIDE7DQogDQotCXJldHVybiAhISh0bXAgJiBBVDkxX1NDS0NfT1NDMzJF Tik7DQorCXJldHVybiAhISh0bXAgJiBvc2MtPmJpdHMtPmNyX29zYzMyZW4pOw0KIH0NCiANCiBz dGF0aWMgY29uc3Qgc3RydWN0IGNsa19vcHMgc2xvd19vc2Nfb3BzID0gew0KQEAgLTExNCw3ICsx MjEsOCBAQCBhdDkxX2Nsa19yZWdpc3Rlcl9zbG93X29zYyh2b2lkIF9faW9tZW0gKnNja2NyLA0K IAkJCSAgIGNvbnN0IGNoYXIgKm5hbWUsDQogCQkJICAgY29uc3QgY2hhciAqcGFyZW50X25hbWUs DQogCQkJICAgdW5zaWduZWQgbG9uZyBzdGFydHVwLA0KLQkJCSAgIGJvb2wgYnlwYXNzKQ0KKwkJ CSAgIGJvb2wgYnlwYXNzLA0KKwkJCSAgIGNvbnN0IHN0cnVjdCBjbGtfc2xvd19iaXRzICpiaXRz KQ0KIHsNCiAJc3RydWN0IGNsa19zbG93X29zYyAqb3NjOw0KIAlzdHJ1Y3QgY2xrX2h3ICpodzsN CkBAIC0xMzcsMTAgKzE0NSwxMSBAQCBhdDkxX2Nsa19yZWdpc3Rlcl9zbG93X29zYyh2b2lkIF9f aW9tZW0gKnNja2NyLA0KIAlvc2MtPmh3LmluaXQgPSAmaW5pdDsNCiAJb3NjLT5zY2tjciA9IHNj a2NyOw0KIAlvc2MtPnN0YXJ0dXBfdXNlYyA9IHN0YXJ0dXA7DQorCW9zYy0+Yml0cyA9IGJpdHM7 DQogDQogCWlmIChieXBhc3MpDQotCQl3cml0ZWwoKHJlYWRsKHNja2NyKSAmIH5BVDkxX1NDS0Nf T1NDMzJFTikgfCBBVDkxX1NDS0NfT1NDMzJCWVAsDQotCQkgICAgICAgc2NrY3IpOw0KKwkJd3Jp dGVsKChyZWFkbChzY2tjcikgJiB+b3NjLT5iaXRzLT5jcl9vc2MzMmVuKSB8DQorCQkJCQlvc2Mt PmJpdHMtPmNyX29zYzMyYnlwLCBzY2tjcik7DQogDQogCWh3ID0gJm9zYy0+aHc7DQogCXJldCA9 IGNsa19od19yZWdpc3RlcihOVUxMLCAmb3NjLT5odyk7DQpAQCAtMTczLDcgKzE4Miw3IEBAIHN0 YXRpYyBpbnQgY2xrX3Nsb3dfcmNfb3NjX3ByZXBhcmUoc3RydWN0IGNsa19odyAqaHcpDQogCXN0 cnVjdCBjbGtfc2xvd19yY19vc2MgKm9zYyA9IHRvX2Nsa19zbG93X3JjX29zYyhodyk7DQogCXZv aWQgX19pb21lbSAqc2NrY3IgPSBvc2MtPnNja2NyOw0KIA0KLQl3cml0ZWwocmVhZGwoc2NrY3Ip IHwgQVQ5MV9TQ0tDX1JDRU4sIHNja2NyKTsNCisJd3JpdGVsKHJlYWRsKHNja2NyKSB8IG9zYy0+ Yml0cy0+Y3JfcmNlbiwgc2NrY3IpOw0KIA0KIAl1c2xlZXBfcmFuZ2Uob3NjLT5zdGFydHVwX3Vz ZWMsIG9zYy0+c3RhcnR1cF91c2VjICsgMSk7DQogDQpAQCAtMTg1LDE0ICsxOTQsMTQgQEAgc3Rh dGljIHZvaWQgY2xrX3Nsb3dfcmNfb3NjX3VucHJlcGFyZShzdHJ1Y3QgY2xrX2h3ICpodykNCiAJ c3RydWN0IGNsa19zbG93X3JjX29zYyAqb3NjID0gdG9fY2xrX3Nsb3dfcmNfb3NjKGh3KTsNCiAJ dm9pZCBfX2lvbWVtICpzY2tjciA9IG9zYy0+c2NrY3I7DQogDQotCXdyaXRlbChyZWFkbChzY2tj cikgJiB+QVQ5MV9TQ0tDX1JDRU4sIHNja2NyKTsNCisJd3JpdGVsKHJlYWRsKHNja2NyKSAmIH5v c2MtPmJpdHMtPmNyX3JjZW4sIHNja2NyKTsNCiB9DQogDQogc3RhdGljIGludCBjbGtfc2xvd19y Y19vc2NfaXNfcHJlcGFyZWQoc3RydWN0IGNsa19odyAqaHcpDQogew0KIAlzdHJ1Y3QgY2xrX3Ns b3dfcmNfb3NjICpvc2MgPSB0b19jbGtfc2xvd19yY19vc2MoaHcpOw0KIA0KLQlyZXR1cm4gISEo cmVhZGwob3NjLT5zY2tjcikgJiBBVDkxX1NDS0NfUkNFTik7DQorCXJldHVybiAhIShyZWFkbChv c2MtPnNja2NyKSAmIG9zYy0+Yml0cy0+Y3JfcmNlbik7DQogfQ0KIA0KIHN0YXRpYyBjb25zdCBz dHJ1Y3QgY2xrX29wcyBzbG93X3JjX29zY19vcHMgPSB7DQpAQCAtMjA4LDcgKzIxNyw4IEBAIGF0 OTFfY2xrX3JlZ2lzdGVyX3Nsb3dfcmNfb3NjKHZvaWQgX19pb21lbSAqc2NrY3IsDQogCQkJICAg ICAgY29uc3QgY2hhciAqbmFtZSwNCiAJCQkgICAgICB1bnNpZ25lZCBsb25nIGZyZXF1ZW5jeSwN CiAJCQkgICAgICB1bnNpZ25lZCBsb25nIGFjY3VyYWN5LA0KLQkJCSAgICAgIHVuc2lnbmVkIGxv bmcgc3RhcnR1cCkNCisJCQkgICAgICB1bnNpZ25lZCBsb25nIHN0YXJ0dXAsDQorCQkJICAgICAg Y29uc3Qgc3RydWN0IGNsa19zbG93X2JpdHMgKmJpdHMpDQogew0KIAlzdHJ1Y3QgY2xrX3Nsb3df cmNfb3NjICpvc2M7DQogCXN0cnVjdCBjbGtfaHcgKmh3Ow0KQEAgLTIzMCw2ICsyNDAsNyBAQCBh dDkxX2Nsa19yZWdpc3Rlcl9zbG93X3JjX29zYyh2b2lkIF9faW9tZW0gKnNja2NyLA0KIA0KIAlv c2MtPmh3LmluaXQgPSAmaW5pdDsNCiAJb3NjLT5zY2tjciA9IHNja2NyOw0KKwlvc2MtPmJpdHMg PSBiaXRzOw0KIAlvc2MtPmZyZXF1ZW5jeSA9IGZyZXF1ZW5jeTsNCiAJb3NjLT5hY2N1cmFjeSA9 IGFjY3VyYWN5Ow0KIAlvc2MtPnN0YXJ0dXBfdXNlYyA9IHN0YXJ0dXA7DQpAQCAtMjU1LDE0ICsy NjYsMTQgQEAgc3RhdGljIGludCBjbGtfc2FtOXg1X3Nsb3dfc2V0X3BhcmVudChzdHJ1Y3QgY2xr X2h3ICpodywgdTggaW5kZXgpDQogDQogCXRtcCA9IHJlYWRsKHNja2NyKTsNCiANCi0JaWYgKCgh aW5kZXggJiYgISh0bXAgJiBBVDkxX1NDS0NfT1NDU0VMKSkgfHwNCi0JICAgIChpbmRleCAmJiAo dG1wICYgQVQ5MV9TQ0tDX09TQ1NFTCkpKQ0KKwlpZiAoKCFpbmRleCAmJiAhKHRtcCAmIHNsb3dj ay0+Yml0cy0+Y3Jfb3Njc2VsKSkgfHwNCisJICAgIChpbmRleCAmJiAodG1wICYgc2xvd2NrLT5i aXRzLT5jcl9vc2NzZWwpKSkNCiAJCXJldHVybiAwOw0KIA0KIAlpZiAoaW5kZXgpDQotCQl0bXAg fD0gQVQ5MV9TQ0tDX09TQ1NFTDsNCisJCXRtcCB8PSBzbG93Y2stPmJpdHMtPmNyX29zY3NlbDsN CiAJZWxzZQ0KLQkJdG1wICY9IH5BVDkxX1NDS0NfT1NDU0VMOw0KKwkJdG1wICY9IH5zbG93Y2st PmJpdHMtPmNyX29zY3NlbDsNCiANCiAJd3JpdGVsKHRtcCwgc2NrY3IpOw0KIA0KQEAgLTI3NSw3 ICsyODYsNyBAQCBzdGF0aWMgdTggY2xrX3NhbTl4NV9zbG93X2dldF9wYXJlbnQoc3RydWN0IGNs a19odyAqaHcpDQogew0KIAlzdHJ1Y3QgY2xrX3NhbTl4NV9zbG93ICpzbG93Y2sgPSB0b19jbGtf c2FtOXg1X3Nsb3coaHcpOw0KIA0KLQlyZXR1cm4gISEocmVhZGwoc2xvd2NrLT5zY2tjcikgJiBB VDkxX1NDS0NfT1NDU0VMKTsNCisJcmV0dXJuICEhKHJlYWRsKHNsb3djay0+c2NrY3IpICYgc2xv d2NrLT5iaXRzLT5jcl9vc2NzZWwpOw0KIH0NCiANCiBzdGF0aWMgY29uc3Qgc3RydWN0IGNsa19v cHMgc2FtOXg1X3Nsb3dfb3BzID0gew0KQEAgLTI4Nyw3ICsyOTgsOCBAQCBzdGF0aWMgc3RydWN0 IGNsa19odyAqIF9faW5pdA0KIGF0OTFfY2xrX3JlZ2lzdGVyX3NhbTl4NV9zbG93KHZvaWQgX19p b21lbSAqc2NrY3IsDQogCQkJICAgICAgY29uc3QgY2hhciAqbmFtZSwNCiAJCQkgICAgICBjb25z dCBjaGFyICoqcGFyZW50X25hbWVzLA0KLQkJCSAgICAgIGludCBudW1fcGFyZW50cykNCisJCQkg ICAgICBpbnQgbnVtX3BhcmVudHMsDQorCQkJICAgICAgY29uc3Qgc3RydWN0IGNsa19zbG93X2Jp dHMgKmJpdHMpDQogew0KIAlzdHJ1Y3QgY2xrX3NhbTl4NV9zbG93ICpzbG93Y2s7DQogCXN0cnVj dCBjbGtfaHcgKmh3Ow0KQEAgLTMwOSw3ICszMjEsOCBAQCBhdDkxX2Nsa19yZWdpc3Rlcl9zYW05 eDVfc2xvdyh2b2lkIF9faW9tZW0gKnNja2NyLA0KIA0KIAlzbG93Y2stPmh3LmluaXQgPSAmaW5p dDsNCiAJc2xvd2NrLT5zY2tjciA9IHNja2NyOw0KLQlzbG93Y2stPnBhcmVudCA9ICEhKHJlYWRs KHNja2NyKSAmIEFUOTFfU0NLQ19PU0NTRUwpOw0KKwlzbG93Y2stPmJpdHMgPSBiaXRzOw0KKwlz bG93Y2stPnBhcmVudCA9ICEhKHJlYWRsKHNja2NyKSAmIHNsb3djay0+Yml0cy0+Y3Jfb3Njc2Vs KTsNCiANCiAJaHcgPSAmc2xvd2NrLT5odzsNCiAJcmV0ID0gY2xrX2h3X3JlZ2lzdGVyKE5VTEws ICZzbG93Y2stPmh3KTsNCkBAIC0zMjIsNyArMzM1LDggQEAgYXQ5MV9jbGtfcmVnaXN0ZXJfc2Ft OXg1X3Nsb3codm9pZCBfX2lvbWVtICpzY2tjciwNCiB9DQogDQogc3RhdGljIHZvaWQgX19pbml0 IGF0OTFzYW05eDVfc2NrY19yZWdpc3RlcihzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wLA0KLQkJCQkJ ICAgIHVuc2lnbmVkIGludCByY19vc2Nfc3RhcnR1cF91cykNCisJCQkJCSAgICB1bnNpZ25lZCBp bnQgcmNfb3NjX3N0YXJ0dXBfdXMsDQorCQkJCQkgICAgY29uc3Qgc3RydWN0IGNsa19zbG93X2Jp dHMgKmJpdHMpDQogew0KIAljb25zdCBjaGFyICpwYXJlbnRfbmFtZXNbMl0gPSB7ICJzbG93X3Jj X29zYyIsICJzbG93X29zYyIgfTsNCiAJdm9pZCBfX2lvbWVtICpyZWdiYXNlID0gb2ZfaW9tYXAo bnAsIDApOw0KQEAgLTMzNSw3ICszNDksOCBAQCBzdGF0aWMgdm9pZCBfX2luaXQgYXQ5MXNhbTl4 NV9zY2tjX3JlZ2lzdGVyKHN0cnVjdCBkZXZpY2Vfbm9kZSAqbnAsDQogCQlyZXR1cm47DQogDQog CWh3ID0gYXQ5MV9jbGtfcmVnaXN0ZXJfc2xvd19yY19vc2MocmVnYmFzZSwgcGFyZW50X25hbWVz WzBdLCAzMjc2OCwNCi0JCQkJCSAgIDUwMDAwMDAwLCByY19vc2Nfc3RhcnR1cF91cyk7DQorCQkJ CQkgICA1MDAwMDAwMCwgcmNfb3NjX3N0YXJ0dXBfdXMsDQorCQkJCQkgICBiaXRzKTsNCiAJaWYg KElTX0VSUihodykpDQogCQlyZXR1cm47DQogDQpAQCAtMzU4LDExICszNzMsMTIgQEAgc3RhdGlj IHZvaWQgX19pbml0IGF0OTFzYW05eDVfc2NrY19yZWdpc3RlcihzdHJ1Y3QgZGV2aWNlX25vZGUg Km5wLA0KIAkJcmV0dXJuOw0KIA0KIAlodyA9IGF0OTFfY2xrX3JlZ2lzdGVyX3Nsb3dfb3NjKHJl Z2Jhc2UsIHBhcmVudF9uYW1lc1sxXSwgeHRhbF9uYW1lLA0KLQkJCQkJMTIwMDAwMCwgYnlwYXNz KTsNCisJCQkJCTEyMDAwMDAsIGJ5cGFzcywgYml0cyk7DQogCWlmIChJU19FUlIoaHcpKQ0KIAkJ cmV0dXJuOw0KIA0KLQlodyA9IGF0OTFfY2xrX3JlZ2lzdGVyX3NhbTl4NV9zbG93KHJlZ2Jhc2Us ICJzbG93Y2siLCBwYXJlbnRfbmFtZXMsIDIpOw0KKwlodyA9IGF0OTFfY2xrX3JlZ2lzdGVyX3Nh bTl4NV9zbG93KHJlZ2Jhc2UsICJzbG93Y2siLCBwYXJlbnRfbmFtZXMsIDIsDQorCQkJCQkgICBi aXRzKTsNCiAJaWYgKElTX0VSUihodykpDQogCQlyZXR1cm47DQogDQpAQCAtMzczLDE2ICszODks MjMgQEAgc3RhdGljIHZvaWQgX19pbml0IGF0OTFzYW05eDVfc2NrY19yZWdpc3RlcihzdHJ1Y3Qg ZGV2aWNlX25vZGUgKm5wLA0KIAkJb2ZfY2xrX2FkZF9od19wcm92aWRlcihjaGlsZCwgb2ZfY2xr X2h3X3NpbXBsZV9nZXQsIGh3KTsNCiB9DQogDQorc3RhdGljIGNvbnN0IHN0cnVjdCBjbGtfc2xv d19iaXRzIGF0OTFzYW05eDVfYml0cyA9IHsNCisJLmNyX3JjZW4gPSBCSVQoMCksDQorCS5jcl9v c2MzMmVuID0gQklUKDEpLA0KKwkuY3Jfb3NjMzJieXAgPSBCSVQoMiksDQorCS5jcl9vc2NzZWwg PSBCSVQoMyksDQorfTsNCisNCiBzdGF0aWMgdm9pZCBfX2luaXQgb2ZfYXQ5MXNhbTl4NV9zY2tj X3NldHVwKHN0cnVjdCBkZXZpY2Vfbm9kZSAqbnApDQogew0KLQlhdDkxc2FtOXg1X3Nja2NfcmVn aXN0ZXIobnAsIDc1KTsNCisJYXQ5MXNhbTl4NV9zY2tjX3JlZ2lzdGVyKG5wLCA3NSwgJmF0OTFz YW05eDVfYml0cyk7DQogfQ0KIENMS19PRl9ERUNMQVJFKGF0OTFzYW05eDVfY2xrX3Nja2MsICJh dG1lbCxhdDkxc2FtOXg1LXNja2MiLA0KIAkgICAgICAgb2ZfYXQ5MXNhbTl4NV9zY2tjX3NldHVw KTsNCiANCiBzdGF0aWMgdm9pZCBfX2luaXQgb2Zfc2FtYTVkM19zY2tjX3NldHVwKHN0cnVjdCBk ZXZpY2Vfbm9kZSAqbnApDQogew0KLQlhdDkxc2FtOXg1X3Nja2NfcmVnaXN0ZXIobnAsIDUwMCk7 DQorCWF0OTFzYW05eDVfc2NrY19yZWdpc3RlcihucCwgNTAwLCAmYXQ5MXNhbTl4NV9iaXRzKTsN CiB9DQogQ0xLX09GX0RFQ0xBUkUoc2FtYTVkM19jbGtfc2NrYywgImF0bWVsLHNhbWE1ZDMtc2Nr YyIsDQogCSAgICAgICBvZl9zYW1hNWQzX3Nja2Nfc2V0dXApOw0KQEAgLTM5OCw3ICs0MjEsNyBA QCBzdGF0aWMgaW50IGNsa19zYW1hNWQ0X3Nsb3dfb3NjX3ByZXBhcmUoc3RydWN0IGNsa19odyAq aHcpDQogCSAqIEFzc3VtZSB0aGF0IGlmIGl0IGhhcyBhbHJlYWR5IGJlZW4gc2VsZWN0ZWQgKGZv ciBleGFtcGxlIGJ5IHRoZQ0KIAkgKiBib290bG9hZGVyKSwgZW5vdWdoIHRpbWUgaGFzIGFyZWFk eSBwYXNzZWQuDQogCSAqLw0KLQlpZiAoKHJlYWRsKG9zYy0+c2NrY3IpICYgQVQ5MV9TQ0tDX09T Q1NFTCkpIHsNCisJaWYgKChyZWFkbChvc2MtPnNja2NyKSAmIG9zYy0+Yml0cy0+Y3Jfb3Njc2Vs KSkgew0KIAkJb3NjLT5wcmVwYXJlZCA9IHRydWU7DQogCQlyZXR1cm4gMDsNCiAJfQ0KQEAgLTQy MSw2ICs0NDQsMTAgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBjbGtfb3BzIHNhbWE1ZDRfc2xvd19v c2Nfb3BzID0gew0KIAkuaXNfcHJlcGFyZWQgPSBjbGtfc2FtYTVkNF9zbG93X29zY19pc19wcmVw YXJlZCwNCiB9Ow0KIA0KK3N0YXRpYyBjb25zdCBzdHJ1Y3QgY2xrX3Nsb3dfYml0cyBhdDkxc2Ft YTVkNF9iaXRzID0gew0KKwkuY3Jfb3Njc2VsID0gQklUKDMpLA0KK307DQorDQogc3RhdGljIHZv aWQgX19pbml0IG9mX3NhbWE1ZDRfc2NrY19zZXR1cChzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wKQ0K IHsNCiAJdm9pZCBfX2lvbWVtICpyZWdiYXNlID0gb2ZfaW9tYXAobnAsIDApOw0KQEAgLTQ1NSw2 ICs0ODIsNyBAQCBzdGF0aWMgdm9pZCBfX2luaXQgb2Zfc2FtYTVkNF9zY2tjX3NldHVwKHN0cnVj dCBkZXZpY2Vfbm9kZSAqbnApDQogCW9zYy0+aHcuaW5pdCA9ICZpbml0Ow0KIAlvc2MtPnNja2Ny ID0gcmVnYmFzZTsNCiAJb3NjLT5zdGFydHVwX3VzZWMgPSAxMjAwMDAwOw0KKwlvc2MtPmJpdHMg PSAmYXQ5MXNhbWE1ZDRfYml0czsNCiANCiAJaHcgPSAmb3NjLT5odzsNCiAJcmV0ID0gY2xrX2h3 X3JlZ2lzdGVyKE5VTEwsICZvc2MtPmh3KTsNCkBAIC00NjMsNyArNDkxLDggQEAgc3RhdGljIHZv aWQgX19pbml0IG9mX3NhbWE1ZDRfc2NrY19zZXR1cChzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wKQ0K IAkJcmV0dXJuOw0KIAl9DQogDQotCWh3ID0gYXQ5MV9jbGtfcmVnaXN0ZXJfc2FtOXg1X3Nsb3co cmVnYmFzZSwgInNsb3djayIsIHBhcmVudF9uYW1lcywgMik7DQorCWh3ID0gYXQ5MV9jbGtfcmVn aXN0ZXJfc2FtOXg1X3Nsb3cocmVnYmFzZSwgInNsb3djayIsIHBhcmVudF9uYW1lcywgMiwNCisJ CQkJCSAgICZhdDkxc2FtYTVkNF9iaXRzKTsNCiAJaWYgKElTX0VSUihodykpDQogCQlyZXR1cm47 DQogDQotLSANCjIuNy40DQoNCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: Subject: [PATCH v4 2/4] clk: at91: sckc: add support to specify registers bit offsets Date: Tue, 21 May 2019 10:11:26 +0000 Message-ID: <1558433454-27971-3-git-send-email-claudiu.beznea@microchip.com> References: <1558433454-27971-1-git-send-email-claudiu.beznea@microchip.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1558433454-27971-1-git-send-email-claudiu.beznea@microchip.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, Nicolas.Ferre@microchip.com, alexandre.belloni@bootlin.com, Ludovic.Desroches@microchip.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Claudiu.Beznea@microchip.com List-Id: devicetree@vger.kernel.org RnJvbTogQ2xhdWRpdSBCZXpuZWEgPGNsYXVkaXUuYmV6bmVhQG1pY3JvY2hpcC5jb20+DQoNCkRp ZmZlcmVudCBJUHMgdXNlcyBkaWZmZXJlbnQgYml0IG9mZnNldHMgaW4gcmVnaXN0ZXJzIGZvciB0 aGUgc2FtZQ0KZnVuY3Rpb25hbGl0eSwgdGh1cyBhZGFwdCB0aGUgZHJpdmVyIHRvIHN1cHBvcnQg dGhpcy4NCg0KU2lnbmVkLW9mZi1ieTogQ2xhdWRpdSBCZXpuZWEgPGNsYXVkaXUuYmV6bmVhQG1p Y3JvY2hpcC5jb20+DQotLS0NCiBkcml2ZXJzL2Nsay9hdDkxL3Nja2MuYyB8IDkzICsrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrLS0tLS0tLS0tLS0tLS0tLS0NCiAxIGZpbGUgY2hhbmdl ZCwgNjEgaW5zZXJ0aW9ucygrKSwgMzIgZGVsZXRpb25zKC0pDQoNCmRpZmYgLS1naXQgYS9kcml2 ZXJzL2Nsay9hdDkxL3Nja2MuYyBiL2RyaXZlcnMvY2xrL2F0OTEvc2NrYy5jDQppbmRleCA2YzU1 YTdhODZmNzkuLmFiMThiMWRhMjY5ZiAxMDA2NDQNCi0tLSBhL2RyaXZlcnMvY2xrL2F0OTEvc2Nr Yy5jDQorKysgYi9kcml2ZXJzL2Nsay9hdDkxL3Nja2MuYw0KQEAgLTIzLDE0ICsyMywxOCBAQA0K IAkJCQkgU0xPV19DTE9DS19GUkVRKQ0KIA0KICNkZWZpbmUJQVQ5MV9TQ0tDX0NSCQkJMHgwMA0K LSNkZWZpbmUJCUFUOTFfU0NLQ19SQ0VOCQkoMSA8PCAwKQ0KLSNkZWZpbmUJCUFUOTFfU0NLQ19P U0MzMkVOCSgxIDw8IDEpDQotI2RlZmluZQkJQVQ5MV9TQ0tDX09TQzMyQllQCSgxIDw8IDIpDQot I2RlZmluZQkJQVQ5MV9TQ0tDX09TQ1NFTAkoMSA8PCAzKQ0KKw0KK3N0cnVjdCBjbGtfc2xvd19i aXRzIHsNCisJdTMyIGNyX3JjZW47DQorCXUzMiBjcl9vc2MzMmVuOw0KKwl1MzIgY3Jfb3NjMzJi eXA7DQorCXUzMiBjcl9vc2NzZWw7DQorfTsNCiANCiBzdHJ1Y3QgY2xrX3Nsb3dfb3NjIHsNCiAJ c3RydWN0IGNsa19odyBodzsNCiAJdm9pZCBfX2lvbWVtICpzY2tjcjsNCisJY29uc3Qgc3RydWN0 IGNsa19zbG93X2JpdHMgKmJpdHM7DQogCXVuc2lnbmVkIGxvbmcgc3RhcnR1cF91c2VjOw0KIH07 DQogDQpAQCAtMzksNiArNDMsNyBAQCBzdHJ1Y3QgY2xrX3Nsb3dfb3NjIHsNCiBzdHJ1Y3QgY2xr X3NhbWE1ZDRfc2xvd19vc2Mgew0KIAlzdHJ1Y3QgY2xrX2h3IGh3Ow0KIAl2b2lkIF9faW9tZW0g KnNja2NyOw0KKwljb25zdCBzdHJ1Y3QgY2xrX3Nsb3dfYml0cyAqYml0czsNCiAJdW5zaWduZWQg bG9uZyBzdGFydHVwX3VzZWM7DQogCWJvb2wgcHJlcGFyZWQ7DQogfTsNCkBAIC00OCw2ICs1Myw3 IEBAIHN0cnVjdCBjbGtfc2FtYTVkNF9zbG93X29zYyB7DQogc3RydWN0IGNsa19zbG93X3JjX29z YyB7DQogCXN0cnVjdCBjbGtfaHcgaHc7DQogCXZvaWQgX19pb21lbSAqc2NrY3I7DQorCWNvbnN0 IHN0cnVjdCBjbGtfc2xvd19iaXRzICpiaXRzOw0KIAl1bnNpZ25lZCBsb25nIGZyZXF1ZW5jeTsN CiAJdW5zaWduZWQgbG9uZyBhY2N1cmFjeTsNCiAJdW5zaWduZWQgbG9uZyBzdGFydHVwX3VzZWM7 DQpAQCAtNTgsNiArNjQsNyBAQCBzdHJ1Y3QgY2xrX3Nsb3dfcmNfb3NjIHsNCiBzdHJ1Y3QgY2xr X3NhbTl4NV9zbG93IHsNCiAJc3RydWN0IGNsa19odyBodzsNCiAJdm9pZCBfX2lvbWVtICpzY2tj cjsNCisJY29uc3Qgc3RydWN0IGNsa19zbG93X2JpdHMgKmJpdHM7DQogCXU4IHBhcmVudDsNCiB9 Ow0KIA0KQEAgLTY5LDEwICs3NiwxMCBAQCBzdGF0aWMgaW50IGNsa19zbG93X29zY19wcmVwYXJl KHN0cnVjdCBjbGtfaHcgKmh3KQ0KIAl2b2lkIF9faW9tZW0gKnNja2NyID0gb3NjLT5zY2tjcjsN CiAJdTMyIHRtcCA9IHJlYWRsKHNja2NyKTsNCiANCi0JaWYgKHRtcCAmIChBVDkxX1NDS0NfT1ND MzJCWVAgfCBBVDkxX1NDS0NfT1NDMzJFTikpDQorCWlmICh0bXAgJiAob3NjLT5iaXRzLT5jcl9v c2MzMmJ5cCB8IG9zYy0+Yml0cy0+Y3Jfb3NjMzJlbikpDQogCQlyZXR1cm4gMDsNCiANCi0Jd3Jp dGVsKHRtcCB8IEFUOTFfU0NLQ19PU0MzMkVOLCBzY2tjcik7DQorCXdyaXRlbCh0bXAgfCBvc2Mt PmJpdHMtPmNyX29zYzMyZW4sIHNja2NyKTsNCiANCiAJdXNsZWVwX3JhbmdlKG9zYy0+c3RhcnR1 cF91c2VjLCBvc2MtPnN0YXJ0dXBfdXNlYyArIDEpOw0KIA0KQEAgLTg1LDEwICs5MiwxMCBAQCBz dGF0aWMgdm9pZCBjbGtfc2xvd19vc2NfdW5wcmVwYXJlKHN0cnVjdCBjbGtfaHcgKmh3KQ0KIAl2 b2lkIF9faW9tZW0gKnNja2NyID0gb3NjLT5zY2tjcjsNCiAJdTMyIHRtcCA9IHJlYWRsKHNja2Ny KTsNCiANCi0JaWYgKHRtcCAmIEFUOTFfU0NLQ19PU0MzMkJZUCkNCisJaWYgKHRtcCAmIG9zYy0+ Yml0cy0+Y3Jfb3NjMzJieXApDQogCQlyZXR1cm47DQogDQotCXdyaXRlbCh0bXAgJiB+QVQ5MV9T Q0tDX09TQzMyRU4sIHNja2NyKTsNCisJd3JpdGVsKHRtcCAmIH5vc2MtPmJpdHMtPmNyX29zYzMy ZW4sIHNja2NyKTsNCiB9DQogDQogc3RhdGljIGludCBjbGtfc2xvd19vc2NfaXNfcHJlcGFyZWQo c3RydWN0IGNsa19odyAqaHcpDQpAQCAtOTcsMTAgKzEwNCwxMCBAQCBzdGF0aWMgaW50IGNsa19z bG93X29zY19pc19wcmVwYXJlZChzdHJ1Y3QgY2xrX2h3ICpodykNCiAJdm9pZCBfX2lvbWVtICpz Y2tjciA9IG9zYy0+c2NrY3I7DQogCXUzMiB0bXAgPSByZWFkbChzY2tjcik7DQogDQotCWlmICh0 bXAgJiBBVDkxX1NDS0NfT1NDMzJCWVApDQorCWlmICh0bXAgJiBvc2MtPmJpdHMtPmNyX29zYzMy YnlwKQ0KIAkJcmV0dXJuIDE7DQogDQotCXJldHVybiAhISh0bXAgJiBBVDkxX1NDS0NfT1NDMzJF Tik7DQorCXJldHVybiAhISh0bXAgJiBvc2MtPmJpdHMtPmNyX29zYzMyZW4pOw0KIH0NCiANCiBz dGF0aWMgY29uc3Qgc3RydWN0IGNsa19vcHMgc2xvd19vc2Nfb3BzID0gew0KQEAgLTExNCw3ICsx MjEsOCBAQCBhdDkxX2Nsa19yZWdpc3Rlcl9zbG93X29zYyh2b2lkIF9faW9tZW0gKnNja2NyLA0K IAkJCSAgIGNvbnN0IGNoYXIgKm5hbWUsDQogCQkJICAgY29uc3QgY2hhciAqcGFyZW50X25hbWUs DQogCQkJICAgdW5zaWduZWQgbG9uZyBzdGFydHVwLA0KLQkJCSAgIGJvb2wgYnlwYXNzKQ0KKwkJ CSAgIGJvb2wgYnlwYXNzLA0KKwkJCSAgIGNvbnN0IHN0cnVjdCBjbGtfc2xvd19iaXRzICpiaXRz KQ0KIHsNCiAJc3RydWN0IGNsa19zbG93X29zYyAqb3NjOw0KIAlzdHJ1Y3QgY2xrX2h3ICpodzsN CkBAIC0xMzcsMTAgKzE0NSwxMSBAQCBhdDkxX2Nsa19yZWdpc3Rlcl9zbG93X29zYyh2b2lkIF9f aW9tZW0gKnNja2NyLA0KIAlvc2MtPmh3LmluaXQgPSAmaW5pdDsNCiAJb3NjLT5zY2tjciA9IHNj a2NyOw0KIAlvc2MtPnN0YXJ0dXBfdXNlYyA9IHN0YXJ0dXA7DQorCW9zYy0+Yml0cyA9IGJpdHM7 DQogDQogCWlmIChieXBhc3MpDQotCQl3cml0ZWwoKHJlYWRsKHNja2NyKSAmIH5BVDkxX1NDS0Nf T1NDMzJFTikgfCBBVDkxX1NDS0NfT1NDMzJCWVAsDQotCQkgICAgICAgc2NrY3IpOw0KKwkJd3Jp dGVsKChyZWFkbChzY2tjcikgJiB+b3NjLT5iaXRzLT5jcl9vc2MzMmVuKSB8DQorCQkJCQlvc2Mt PmJpdHMtPmNyX29zYzMyYnlwLCBzY2tjcik7DQogDQogCWh3ID0gJm9zYy0+aHc7DQogCXJldCA9 IGNsa19od19yZWdpc3RlcihOVUxMLCAmb3NjLT5odyk7DQpAQCAtMTczLDcgKzE4Miw3IEBAIHN0 YXRpYyBpbnQgY2xrX3Nsb3dfcmNfb3NjX3ByZXBhcmUoc3RydWN0IGNsa19odyAqaHcpDQogCXN0 cnVjdCBjbGtfc2xvd19yY19vc2MgKm9zYyA9IHRvX2Nsa19zbG93X3JjX29zYyhodyk7DQogCXZv aWQgX19pb21lbSAqc2NrY3IgPSBvc2MtPnNja2NyOw0KIA0KLQl3cml0ZWwocmVhZGwoc2NrY3Ip IHwgQVQ5MV9TQ0tDX1JDRU4sIHNja2NyKTsNCisJd3JpdGVsKHJlYWRsKHNja2NyKSB8IG9zYy0+ Yml0cy0+Y3JfcmNlbiwgc2NrY3IpOw0KIA0KIAl1c2xlZXBfcmFuZ2Uob3NjLT5zdGFydHVwX3Vz ZWMsIG9zYy0+c3RhcnR1cF91c2VjICsgMSk7DQogDQpAQCAtMTg1LDE0ICsxOTQsMTQgQEAgc3Rh dGljIHZvaWQgY2xrX3Nsb3dfcmNfb3NjX3VucHJlcGFyZShzdHJ1Y3QgY2xrX2h3ICpodykNCiAJ c3RydWN0IGNsa19zbG93X3JjX29zYyAqb3NjID0gdG9fY2xrX3Nsb3dfcmNfb3NjKGh3KTsNCiAJ dm9pZCBfX2lvbWVtICpzY2tjciA9IG9zYy0+c2NrY3I7DQogDQotCXdyaXRlbChyZWFkbChzY2tj cikgJiB+QVQ5MV9TQ0tDX1JDRU4sIHNja2NyKTsNCisJd3JpdGVsKHJlYWRsKHNja2NyKSAmIH5v c2MtPmJpdHMtPmNyX3JjZW4sIHNja2NyKTsNCiB9DQogDQogc3RhdGljIGludCBjbGtfc2xvd19y Y19vc2NfaXNfcHJlcGFyZWQoc3RydWN0IGNsa19odyAqaHcpDQogew0KIAlzdHJ1Y3QgY2xrX3Ns b3dfcmNfb3NjICpvc2MgPSB0b19jbGtfc2xvd19yY19vc2MoaHcpOw0KIA0KLQlyZXR1cm4gISEo cmVhZGwob3NjLT5zY2tjcikgJiBBVDkxX1NDS0NfUkNFTik7DQorCXJldHVybiAhIShyZWFkbChv c2MtPnNja2NyKSAmIG9zYy0+Yml0cy0+Y3JfcmNlbik7DQogfQ0KIA0KIHN0YXRpYyBjb25zdCBz dHJ1Y3QgY2xrX29wcyBzbG93X3JjX29zY19vcHMgPSB7DQpAQCAtMjA4LDcgKzIxNyw4IEBAIGF0 OTFfY2xrX3JlZ2lzdGVyX3Nsb3dfcmNfb3NjKHZvaWQgX19pb21lbSAqc2NrY3IsDQogCQkJICAg ICAgY29uc3QgY2hhciAqbmFtZSwNCiAJCQkgICAgICB1bnNpZ25lZCBsb25nIGZyZXF1ZW5jeSwN CiAJCQkgICAgICB1bnNpZ25lZCBsb25nIGFjY3VyYWN5LA0KLQkJCSAgICAgIHVuc2lnbmVkIGxv bmcgc3RhcnR1cCkNCisJCQkgICAgICB1bnNpZ25lZCBsb25nIHN0YXJ0dXAsDQorCQkJICAgICAg Y29uc3Qgc3RydWN0IGNsa19zbG93X2JpdHMgKmJpdHMpDQogew0KIAlzdHJ1Y3QgY2xrX3Nsb3df cmNfb3NjICpvc2M7DQogCXN0cnVjdCBjbGtfaHcgKmh3Ow0KQEAgLTIzMCw2ICsyNDAsNyBAQCBh dDkxX2Nsa19yZWdpc3Rlcl9zbG93X3JjX29zYyh2b2lkIF9faW9tZW0gKnNja2NyLA0KIA0KIAlv c2MtPmh3LmluaXQgPSAmaW5pdDsNCiAJb3NjLT5zY2tjciA9IHNja2NyOw0KKwlvc2MtPmJpdHMg PSBiaXRzOw0KIAlvc2MtPmZyZXF1ZW5jeSA9IGZyZXF1ZW5jeTsNCiAJb3NjLT5hY2N1cmFjeSA9 IGFjY3VyYWN5Ow0KIAlvc2MtPnN0YXJ0dXBfdXNlYyA9IHN0YXJ0dXA7DQpAQCAtMjU1LDE0ICsy NjYsMTQgQEAgc3RhdGljIGludCBjbGtfc2FtOXg1X3Nsb3dfc2V0X3BhcmVudChzdHJ1Y3QgY2xr X2h3ICpodywgdTggaW5kZXgpDQogDQogCXRtcCA9IHJlYWRsKHNja2NyKTsNCiANCi0JaWYgKCgh aW5kZXggJiYgISh0bXAgJiBBVDkxX1NDS0NfT1NDU0VMKSkgfHwNCi0JICAgIChpbmRleCAmJiAo dG1wICYgQVQ5MV9TQ0tDX09TQ1NFTCkpKQ0KKwlpZiAoKCFpbmRleCAmJiAhKHRtcCAmIHNsb3dj ay0+Yml0cy0+Y3Jfb3Njc2VsKSkgfHwNCisJICAgIChpbmRleCAmJiAodG1wICYgc2xvd2NrLT5i aXRzLT5jcl9vc2NzZWwpKSkNCiAJCXJldHVybiAwOw0KIA0KIAlpZiAoaW5kZXgpDQotCQl0bXAg fD0gQVQ5MV9TQ0tDX09TQ1NFTDsNCisJCXRtcCB8PSBzbG93Y2stPmJpdHMtPmNyX29zY3NlbDsN CiAJZWxzZQ0KLQkJdG1wICY9IH5BVDkxX1NDS0NfT1NDU0VMOw0KKwkJdG1wICY9IH5zbG93Y2st PmJpdHMtPmNyX29zY3NlbDsNCiANCiAJd3JpdGVsKHRtcCwgc2NrY3IpOw0KIA0KQEAgLTI3NSw3 ICsyODYsNyBAQCBzdGF0aWMgdTggY2xrX3NhbTl4NV9zbG93X2dldF9wYXJlbnQoc3RydWN0IGNs a19odyAqaHcpDQogew0KIAlzdHJ1Y3QgY2xrX3NhbTl4NV9zbG93ICpzbG93Y2sgPSB0b19jbGtf c2FtOXg1X3Nsb3coaHcpOw0KIA0KLQlyZXR1cm4gISEocmVhZGwoc2xvd2NrLT5zY2tjcikgJiBB VDkxX1NDS0NfT1NDU0VMKTsNCisJcmV0dXJuICEhKHJlYWRsKHNsb3djay0+c2NrY3IpICYgc2xv d2NrLT5iaXRzLT5jcl9vc2NzZWwpOw0KIH0NCiANCiBzdGF0aWMgY29uc3Qgc3RydWN0IGNsa19v cHMgc2FtOXg1X3Nsb3dfb3BzID0gew0KQEAgLTI4Nyw3ICsyOTgsOCBAQCBzdGF0aWMgc3RydWN0 IGNsa19odyAqIF9faW5pdA0KIGF0OTFfY2xrX3JlZ2lzdGVyX3NhbTl4NV9zbG93KHZvaWQgX19p b21lbSAqc2NrY3IsDQogCQkJICAgICAgY29uc3QgY2hhciAqbmFtZSwNCiAJCQkgICAgICBjb25z dCBjaGFyICoqcGFyZW50X25hbWVzLA0KLQkJCSAgICAgIGludCBudW1fcGFyZW50cykNCisJCQkg ICAgICBpbnQgbnVtX3BhcmVudHMsDQorCQkJICAgICAgY29uc3Qgc3RydWN0IGNsa19zbG93X2Jp dHMgKmJpdHMpDQogew0KIAlzdHJ1Y3QgY2xrX3NhbTl4NV9zbG93ICpzbG93Y2s7DQogCXN0cnVj dCBjbGtfaHcgKmh3Ow0KQEAgLTMwOSw3ICszMjEsOCBAQCBhdDkxX2Nsa19yZWdpc3Rlcl9zYW05 eDVfc2xvdyh2b2lkIF9faW9tZW0gKnNja2NyLA0KIA0KIAlzbG93Y2stPmh3LmluaXQgPSAmaW5p dDsNCiAJc2xvd2NrLT5zY2tjciA9IHNja2NyOw0KLQlzbG93Y2stPnBhcmVudCA9ICEhKHJlYWRs KHNja2NyKSAmIEFUOTFfU0NLQ19PU0NTRUwpOw0KKwlzbG93Y2stPmJpdHMgPSBiaXRzOw0KKwlz bG93Y2stPnBhcmVudCA9ICEhKHJlYWRsKHNja2NyKSAmIHNsb3djay0+Yml0cy0+Y3Jfb3Njc2Vs KTsNCiANCiAJaHcgPSAmc2xvd2NrLT5odzsNCiAJcmV0ID0gY2xrX2h3X3JlZ2lzdGVyKE5VTEws ICZzbG93Y2stPmh3KTsNCkBAIC0zMjIsNyArMzM1LDggQEAgYXQ5MV9jbGtfcmVnaXN0ZXJfc2Ft OXg1X3Nsb3codm9pZCBfX2lvbWVtICpzY2tjciwNCiB9DQogDQogc3RhdGljIHZvaWQgX19pbml0 IGF0OTFzYW05eDVfc2NrY19yZWdpc3RlcihzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wLA0KLQkJCQkJ ICAgIHVuc2lnbmVkIGludCByY19vc2Nfc3RhcnR1cF91cykNCisJCQkJCSAgICB1bnNpZ25lZCBp bnQgcmNfb3NjX3N0YXJ0dXBfdXMsDQorCQkJCQkgICAgY29uc3Qgc3RydWN0IGNsa19zbG93X2Jp dHMgKmJpdHMpDQogew0KIAljb25zdCBjaGFyICpwYXJlbnRfbmFtZXNbMl0gPSB7ICJzbG93X3Jj X29zYyIsICJzbG93X29zYyIgfTsNCiAJdm9pZCBfX2lvbWVtICpyZWdiYXNlID0gb2ZfaW9tYXAo bnAsIDApOw0KQEAgLTMzNSw3ICszNDksOCBAQCBzdGF0aWMgdm9pZCBfX2luaXQgYXQ5MXNhbTl4 NV9zY2tjX3JlZ2lzdGVyKHN0cnVjdCBkZXZpY2Vfbm9kZSAqbnAsDQogCQlyZXR1cm47DQogDQog CWh3ID0gYXQ5MV9jbGtfcmVnaXN0ZXJfc2xvd19yY19vc2MocmVnYmFzZSwgcGFyZW50X25hbWVz WzBdLCAzMjc2OCwNCi0JCQkJCSAgIDUwMDAwMDAwLCByY19vc2Nfc3RhcnR1cF91cyk7DQorCQkJ CQkgICA1MDAwMDAwMCwgcmNfb3NjX3N0YXJ0dXBfdXMsDQorCQkJCQkgICBiaXRzKTsNCiAJaWYg KElTX0VSUihodykpDQogCQlyZXR1cm47DQogDQpAQCAtMzU4LDExICszNzMsMTIgQEAgc3RhdGlj IHZvaWQgX19pbml0IGF0OTFzYW05eDVfc2NrY19yZWdpc3RlcihzdHJ1Y3QgZGV2aWNlX25vZGUg Km5wLA0KIAkJcmV0dXJuOw0KIA0KIAlodyA9IGF0OTFfY2xrX3JlZ2lzdGVyX3Nsb3dfb3NjKHJl Z2Jhc2UsIHBhcmVudF9uYW1lc1sxXSwgeHRhbF9uYW1lLA0KLQkJCQkJMTIwMDAwMCwgYnlwYXNz KTsNCisJCQkJCTEyMDAwMDAsIGJ5cGFzcywgYml0cyk7DQogCWlmIChJU19FUlIoaHcpKQ0KIAkJ cmV0dXJuOw0KIA0KLQlodyA9IGF0OTFfY2xrX3JlZ2lzdGVyX3NhbTl4NV9zbG93KHJlZ2Jhc2Us ICJzbG93Y2siLCBwYXJlbnRfbmFtZXMsIDIpOw0KKwlodyA9IGF0OTFfY2xrX3JlZ2lzdGVyX3Nh bTl4NV9zbG93KHJlZ2Jhc2UsICJzbG93Y2siLCBwYXJlbnRfbmFtZXMsIDIsDQorCQkJCQkgICBi aXRzKTsNCiAJaWYgKElTX0VSUihodykpDQogCQlyZXR1cm47DQogDQpAQCAtMzczLDE2ICszODks MjMgQEAgc3RhdGljIHZvaWQgX19pbml0IGF0OTFzYW05eDVfc2NrY19yZWdpc3RlcihzdHJ1Y3Qg ZGV2aWNlX25vZGUgKm5wLA0KIAkJb2ZfY2xrX2FkZF9od19wcm92aWRlcihjaGlsZCwgb2ZfY2xr X2h3X3NpbXBsZV9nZXQsIGh3KTsNCiB9DQogDQorc3RhdGljIGNvbnN0IHN0cnVjdCBjbGtfc2xv d19iaXRzIGF0OTFzYW05eDVfYml0cyA9IHsNCisJLmNyX3JjZW4gPSBCSVQoMCksDQorCS5jcl9v c2MzMmVuID0gQklUKDEpLA0KKwkuY3Jfb3NjMzJieXAgPSBCSVQoMiksDQorCS5jcl9vc2NzZWwg PSBCSVQoMyksDQorfTsNCisNCiBzdGF0aWMgdm9pZCBfX2luaXQgb2ZfYXQ5MXNhbTl4NV9zY2tj X3NldHVwKHN0cnVjdCBkZXZpY2Vfbm9kZSAqbnApDQogew0KLQlhdDkxc2FtOXg1X3Nja2NfcmVn aXN0ZXIobnAsIDc1KTsNCisJYXQ5MXNhbTl4NV9zY2tjX3JlZ2lzdGVyKG5wLCA3NSwgJmF0OTFz YW05eDVfYml0cyk7DQogfQ0KIENMS19PRl9ERUNMQVJFKGF0OTFzYW05eDVfY2xrX3Nja2MsICJh dG1lbCxhdDkxc2FtOXg1LXNja2MiLA0KIAkgICAgICAgb2ZfYXQ5MXNhbTl4NV9zY2tjX3NldHVw KTsNCiANCiBzdGF0aWMgdm9pZCBfX2luaXQgb2Zfc2FtYTVkM19zY2tjX3NldHVwKHN0cnVjdCBk ZXZpY2Vfbm9kZSAqbnApDQogew0KLQlhdDkxc2FtOXg1X3Nja2NfcmVnaXN0ZXIobnAsIDUwMCk7 DQorCWF0OTFzYW05eDVfc2NrY19yZWdpc3RlcihucCwgNTAwLCAmYXQ5MXNhbTl4NV9iaXRzKTsN CiB9DQogQ0xLX09GX0RFQ0xBUkUoc2FtYTVkM19jbGtfc2NrYywgImF0bWVsLHNhbWE1ZDMtc2Nr YyIsDQogCSAgICAgICBvZl9zYW1hNWQzX3Nja2Nfc2V0dXApOw0KQEAgLTM5OCw3ICs0MjEsNyBA QCBzdGF0aWMgaW50IGNsa19zYW1hNWQ0X3Nsb3dfb3NjX3ByZXBhcmUoc3RydWN0IGNsa19odyAq aHcpDQogCSAqIEFzc3VtZSB0aGF0IGlmIGl0IGhhcyBhbHJlYWR5IGJlZW4gc2VsZWN0ZWQgKGZv ciBleGFtcGxlIGJ5IHRoZQ0KIAkgKiBib290bG9hZGVyKSwgZW5vdWdoIHRpbWUgaGFzIGFyZWFk eSBwYXNzZWQuDQogCSAqLw0KLQlpZiAoKHJlYWRsKG9zYy0+c2NrY3IpICYgQVQ5MV9TQ0tDX09T Q1NFTCkpIHsNCisJaWYgKChyZWFkbChvc2MtPnNja2NyKSAmIG9zYy0+Yml0cy0+Y3Jfb3Njc2Vs KSkgew0KIAkJb3NjLT5wcmVwYXJlZCA9IHRydWU7DQogCQlyZXR1cm4gMDsNCiAJfQ0KQEAgLTQy MSw2ICs0NDQsMTAgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBjbGtfb3BzIHNhbWE1ZDRfc2xvd19v c2Nfb3BzID0gew0KIAkuaXNfcHJlcGFyZWQgPSBjbGtfc2FtYTVkNF9zbG93X29zY19pc19wcmVw YXJlZCwNCiB9Ow0KIA0KK3N0YXRpYyBjb25zdCBzdHJ1Y3QgY2xrX3Nsb3dfYml0cyBhdDkxc2Ft YTVkNF9iaXRzID0gew0KKwkuY3Jfb3Njc2VsID0gQklUKDMpLA0KK307DQorDQogc3RhdGljIHZv aWQgX19pbml0IG9mX3NhbWE1ZDRfc2NrY19zZXR1cChzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wKQ0K IHsNCiAJdm9pZCBfX2lvbWVtICpyZWdiYXNlID0gb2ZfaW9tYXAobnAsIDApOw0KQEAgLTQ1NSw2 ICs0ODIsNyBAQCBzdGF0aWMgdm9pZCBfX2luaXQgb2Zfc2FtYTVkNF9zY2tjX3NldHVwKHN0cnVj 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twcuSKKI4ZiDXA7uRsSKr4miX3b0IuaS9A4YY0d/eA456uodm8Ac9jz15N6G1azvoMZMzxaP78oiygryLO3++3txmdYnkZsqS/M6Lha5YAKkYLmDXI8lTGwaHlUM+44YsyYRMV+ceOhFn3lWxzN6isz6QiMqXL4LZUToNCRMtPzFStOZTa74JkfcAI60ROL0wwR2+9jXgK69GUuBjh4FUXpsyfL6NqqVQGtnkCRZfURwi2a0LcIlNCmLEYVltBFK661QyTq+TYtGmpIaqwLyIxL7hQwiVbhaZ9HJYKxJ4cZl50zvnNrpF/7VYOyknzh5ijTugdft0KralI2NZBGxwIYE+Px60V/lvmjaUhgBiXby72vCU3AiQCnzzX7+cDlTOS70DpFZpotn9Zh7U0NXjxgTb61Jqx0a1y2YyrnYNpw= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 31d26765-23c2-4c3f-41d2-08d6ddd4af08 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 May 2019 10:11:26.2075 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR11MB1949 X-OriginatorOrg: microchip.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190521_031128_778819_7259DBCF X-CRM114-Status: GOOD ( 13.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Claudiu.Beznea@microchip.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Different IPs uses different bit offsets in registers for the same functionality, thus adapt the driver to support this. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sckc.c | 93 ++++++++++++++++++++++++++++++++----------------- 1 file changed, 61 insertions(+), 32 deletions(-) diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index 6c55a7a86f79..ab18b1da269f 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -23,14 +23,18 @@ SLOW_CLOCK_FREQ) #define AT91_SCKC_CR 0x00 -#define AT91_SCKC_RCEN (1 << 0) -#define AT91_SCKC_OSC32EN (1 << 1) -#define AT91_SCKC_OSC32BYP (1 << 2) -#define AT91_SCKC_OSCSEL (1 << 3) + +struct clk_slow_bits { + u32 cr_rcen; + u32 cr_osc32en; + u32 cr_osc32byp; + u32 cr_oscsel; +}; struct clk_slow_osc { struct clk_hw hw; void __iomem *sckcr; + const struct clk_slow_bits *bits; unsigned long startup_usec; }; @@ -39,6 +43,7 @@ struct clk_slow_osc { struct clk_sama5d4_slow_osc { struct clk_hw hw; void __iomem *sckcr; + const struct clk_slow_bits *bits; unsigned long startup_usec; bool prepared; }; @@ -48,6 +53,7 @@ struct clk_sama5d4_slow_osc { struct clk_slow_rc_osc { struct clk_hw hw; void __iomem *sckcr; + const struct clk_slow_bits *bits; unsigned long frequency; unsigned long accuracy; unsigned long startup_usec; @@ -58,6 +64,7 @@ struct clk_slow_rc_osc { struct clk_sam9x5_slow { struct clk_hw hw; void __iomem *sckcr; + const struct clk_slow_bits *bits; u8 parent; }; @@ -69,10 +76,10 @@ static int clk_slow_osc_prepare(struct clk_hw *hw) void __iomem *sckcr = osc->sckcr; u32 tmp = readl(sckcr); - if (tmp & (AT91_SCKC_OSC32BYP | AT91_SCKC_OSC32EN)) + if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en)) return 0; - writel(tmp | AT91_SCKC_OSC32EN, sckcr); + writel(tmp | osc->bits->cr_osc32en, sckcr); usleep_range(osc->startup_usec, osc->startup_usec + 1); @@ -85,10 +92,10 @@ static void clk_slow_osc_unprepare(struct clk_hw *hw) void __iomem *sckcr = osc->sckcr; u32 tmp = readl(sckcr); - if (tmp & AT91_SCKC_OSC32BYP) + if (tmp & osc->bits->cr_osc32byp) return; - writel(tmp & ~AT91_SCKC_OSC32EN, sckcr); + writel(tmp & ~osc->bits->cr_osc32en, sckcr); } static int clk_slow_osc_is_prepared(struct clk_hw *hw) @@ -97,10 +104,10 @@ static int clk_slow_osc_is_prepared(struct clk_hw *hw) void __iomem *sckcr = osc->sckcr; u32 tmp = readl(sckcr); - if (tmp & AT91_SCKC_OSC32BYP) + if (tmp & osc->bits->cr_osc32byp) return 1; - return !!(tmp & AT91_SCKC_OSC32EN); + return !!(tmp & osc->bits->cr_osc32en); } static const struct clk_ops slow_osc_ops = { @@ -114,7 +121,8 @@ at91_clk_register_slow_osc(void __iomem *sckcr, const char *name, const char *parent_name, unsigned long startup, - bool bypass) + bool bypass, + const struct clk_slow_bits *bits) { struct clk_slow_osc *osc; struct clk_hw *hw; @@ -137,10 +145,11 @@ at91_clk_register_slow_osc(void __iomem *sckcr, osc->hw.init = &init; osc->sckcr = sckcr; osc->startup_usec = startup; + osc->bits = bits; if (bypass) - writel((readl(sckcr) & ~AT91_SCKC_OSC32EN) | AT91_SCKC_OSC32BYP, - sckcr); + writel((readl(sckcr) & ~osc->bits->cr_osc32en) | + osc->bits->cr_osc32byp, sckcr); hw = &osc->hw; ret = clk_hw_register(NULL, &osc->hw); @@ -173,7 +182,7 @@ static int clk_slow_rc_osc_prepare(struct clk_hw *hw) struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); void __iomem *sckcr = osc->sckcr; - writel(readl(sckcr) | AT91_SCKC_RCEN, sckcr); + writel(readl(sckcr) | osc->bits->cr_rcen, sckcr); usleep_range(osc->startup_usec, osc->startup_usec + 1); @@ -185,14 +194,14 @@ static void clk_slow_rc_osc_unprepare(struct clk_hw *hw) struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); void __iomem *sckcr = osc->sckcr; - writel(readl(sckcr) & ~AT91_SCKC_RCEN, sckcr); + writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr); } static int clk_slow_rc_osc_is_prepared(struct clk_hw *hw) { struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); - return !!(readl(osc->sckcr) & AT91_SCKC_RCEN); + return !!(readl(osc->sckcr) & osc->bits->cr_rcen); } static const struct clk_ops slow_rc_osc_ops = { @@ -208,7 +217,8 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, const char *name, unsigned long frequency, unsigned long accuracy, - unsigned long startup) + unsigned long startup, + const struct clk_slow_bits *bits) { struct clk_slow_rc_osc *osc; struct clk_hw *hw; @@ -230,6 +240,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, osc->hw.init = &init; osc->sckcr = sckcr; + osc->bits = bits; osc->frequency = frequency; osc->accuracy = accuracy; osc->startup_usec = startup; @@ -255,14 +266,14 @@ static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index) tmp = readl(sckcr); - if ((!index && !(tmp & AT91_SCKC_OSCSEL)) || - (index && (tmp & AT91_SCKC_OSCSEL))) + if ((!index && !(tmp & slowck->bits->cr_oscsel)) || + (index && (tmp & slowck->bits->cr_oscsel))) return 0; if (index) - tmp |= AT91_SCKC_OSCSEL; + tmp |= slowck->bits->cr_oscsel; else - tmp &= ~AT91_SCKC_OSCSEL; + tmp &= ~slowck->bits->cr_oscsel; writel(tmp, sckcr); @@ -275,7 +286,7 @@ static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw) { struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw); - return !!(readl(slowck->sckcr) & AT91_SCKC_OSCSEL); + return !!(readl(slowck->sckcr) & slowck->bits->cr_oscsel); } static const struct clk_ops sam9x5_slow_ops = { @@ -287,7 +298,8 @@ static struct clk_hw * __init at91_clk_register_sam9x5_slow(void __iomem *sckcr, const char *name, const char **parent_names, - int num_parents) + int num_parents, + const struct clk_slow_bits *bits) { struct clk_sam9x5_slow *slowck; struct clk_hw *hw; @@ -309,7 +321,8 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr, slowck->hw.init = &init; slowck->sckcr = sckcr; - slowck->parent = !!(readl(sckcr) & AT91_SCKC_OSCSEL); + slowck->bits = bits; + slowck->parent = !!(readl(sckcr) & slowck->bits->cr_oscsel); hw = &slowck->hw; ret = clk_hw_register(NULL, &slowck->hw); @@ -322,7 +335,8 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr, } static void __init at91sam9x5_sckc_register(struct device_node *np, - unsigned int rc_osc_startup_us) + unsigned int rc_osc_startup_us, + const struct clk_slow_bits *bits) { const char *parent_names[2] = { "slow_rc_osc", "slow_osc" }; void __iomem *regbase = of_iomap(np, 0); @@ -335,7 +349,8 @@ static void __init at91sam9x5_sckc_register(struct device_node *np, return; hw = at91_clk_register_slow_rc_osc(regbase, parent_names[0], 32768, - 50000000, rc_osc_startup_us); + 50000000, rc_osc_startup_us, + bits); if (IS_ERR(hw)) return; @@ -358,11 +373,12 @@ static void __init at91sam9x5_sckc_register(struct device_node *np, return; hw = at91_clk_register_slow_osc(regbase, parent_names[1], xtal_name, - 1200000, bypass); + 1200000, bypass, bits); if (IS_ERR(hw)) return; - hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2); + hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2, + bits); if (IS_ERR(hw)) return; @@ -373,16 +389,23 @@ static void __init at91sam9x5_sckc_register(struct device_node *np, of_clk_add_hw_provider(child, of_clk_hw_simple_get, hw); } +static const struct clk_slow_bits at91sam9x5_bits = { + .cr_rcen = BIT(0), + .cr_osc32en = BIT(1), + .cr_osc32byp = BIT(2), + .cr_oscsel = BIT(3), +}; + static void __init of_at91sam9x5_sckc_setup(struct device_node *np) { - at91sam9x5_sckc_register(np, 75); + at91sam9x5_sckc_register(np, 75, &at91sam9x5_bits); } CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc", of_at91sam9x5_sckc_setup); static void __init of_sama5d3_sckc_setup(struct device_node *np) { - at91sam9x5_sckc_register(np, 500); + at91sam9x5_sckc_register(np, 500, &at91sam9x5_bits); } CLK_OF_DECLARE(sama5d3_clk_sckc, "atmel,sama5d3-sckc", of_sama5d3_sckc_setup); @@ -398,7 +421,7 @@ static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw) * Assume that if it has already been selected (for example by the * bootloader), enough time has aready passed. */ - if ((readl(osc->sckcr) & AT91_SCKC_OSCSEL)) { + if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) { osc->prepared = true; return 0; } @@ -421,6 +444,10 @@ static const struct clk_ops sama5d4_slow_osc_ops = { .is_prepared = clk_sama5d4_slow_osc_is_prepared, }; +static const struct clk_slow_bits at91sama5d4_bits = { + .cr_oscsel = BIT(3), +}; + static void __init of_sama5d4_sckc_setup(struct device_node *np) { void __iomem *regbase = of_iomap(np, 0); @@ -455,6 +482,7 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np) osc->hw.init = &init; osc->sckcr = regbase; osc->startup_usec = 1200000; + osc->bits = &at91sama5d4_bits; hw = &osc->hw; ret = clk_hw_register(NULL, &osc->hw); @@ -463,7 +491,8 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np) return; } - hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2); + hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2, + &at91sama5d4_bits); if (IS_ERR(hw)) return; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel