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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.75 Subject: [Qemu-devel] [PATCH v3 1/1] configure: Define target access alignment in configure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, arikalo@wavecomp.com, mark.cave-ayland@ilande.co.uk, jcmvbkbc@gmail.com, aurelien@aurel32.net, amarkovic@wavecomp.com, atar4qemu@gmail.com, rth@twiddle.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Rename ALIGNED_ONLY to TARGET_ALIGNED_ONLY for clarity and move=0A= defines out of target/foo/cpu.h into configure, as we do with=0A= TARGET_WORDS_BIGENDIAN, so that it is always defined early.=0A= =0A= Also, poison the symbol in include/exec/poison.h to prevent use in=0A= common code.=0A= =0A= Reviewed-by: Philippe Mathieu-Daud=E9 =0A= Reviewed-by: Richard Henderson =0A= Signed-off-by: Tony Nguyen =0A= ---=0A= configure | 10 +++++++++-=0A= include/exec/poison.h | 1 +=0A= include/qom/cpu.h | 2 +-=0A= target/alpha/cpu.h | 2 --=0A= target/hppa/cpu.h | 1 -=0A= target/mips/cpu.h | 2 --=0A= target/sh4/cpu.h | 2 --=0A= target/sparc/cpu.h | 2 --=0A= target/xtensa/cpu.h | 2 --=0A= tcg/tcg.c | 2 +-=0A= tcg/tcg.h | 8 +++++---=0A= 11 files changed, 17 insertions(+), 17 deletions(-)=0A= =0A= diff --git a/configure b/configure=0A= index 714e7fb..482ba0b 100755=0A= --- a/configure=0A= +++ b/configure=0A= @@ -7431,8 +7431,13 @@ for target in $target_list; do=0A= target_dir=3D"$target"=0A= config_target_mak=3D$target_dir/config-target.mak=0A= target_name=3D$(echo $target | cut -d '-' -f 1)=0A= +target_aligned_only=3D"no"=0A= +case "$target_name" in=0A= + alpha|hppa|mips64el|mips64|mipsel|mips|mipsn32|mipsn32el|sh4|sh4eb|sparc= |sparc64|sparc32plus|xtensa|xtensaeb)=0A= + target_aligned_only=3D"yes"=0A= + ;;=0A= +esac=0A= target_bigendian=3D"no"=0A= -=0A= case "$target_name" in=0A= armeb|aarch64_be|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1= k|ppc|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)=0A= target_bigendian=3Dyes=0A= @@ -7717,6 +7722,9 @@ fi=0A= if supported_whpx_target $target; then=0A= echo "CONFIG_WHPX=3Dy" >> $config_target_mak=0A= fi=0A= +if test "$target_aligned_only" =3D "yes" ; then=0A= + echo "TARGET_ALIGNED_ONLY=3Dy" >> $config_target_mak=0A= +fi=0A= if test "$target_bigendian" =3D "yes" ; then=0A= echo "TARGET_WORDS_BIGENDIAN=3Dy" >> $config_target_mak=0A= fi=0A= diff --git a/include/exec/poison.h b/include/exec/poison.h=0A= index b862320..955eb86 100644=0A= --- a/include/exec/poison.h=0A= +++ b/include/exec/poison.h=0A= @@ -35,6 +35,7 @@=0A= #pragma GCC poison TARGET_UNICORE32=0A= #pragma GCC poison TARGET_XTENSA=0A= =0A= +#pragma GCC poison TARGET_ALIGNED_ONLY=0A= #pragma GCC poison TARGET_HAS_BFLT=0A= #pragma GCC poison TARGET_NAME=0A= #pragma GCC poison TARGET_SUPPORTS_MTTCG=0A= diff --git a/include/qom/cpu.h b/include/qom/cpu.h=0A= index 5ee0046..9b50b73 100644=0A= --- a/include/qom/cpu.h=0A= +++ b/include/qom/cpu.h=0A= @@ -89,7 +89,7 @@ struct TranslationBlock;=0A= * @do_unassigned_access: Callback for unassigned access handling.=0A= * (this is deprecated: new targets should use do_transaction_failed inste= ad)=0A= * @do_unaligned_access: Callback for unaligned access handling, if=0A= - * the target defines #ALIGNED_ONLY.=0A= + * the target defines #TARGET_ALIGNED_ONLY.=0A= * @do_transaction_failed: Callback for handling failed memory transaction= s=0A= * (ie bus faults or external aborts; not MMU faults)=0A= * @virtio_is_big_endian: Callback to return %true if a CPU which supports= =0A= diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h=0A= index b3e8a82..16eb804 100644=0A= --- a/target/alpha/cpu.h=0A= +++ b/target/alpha/cpu.h=0A= @@ -23,8 +23,6 @@=0A= #include "cpu-qom.h"=0A= #include "exec/cpu-defs.h"=0A= =0A= -#define ALIGNED_ONLY=0A= -=0A= /* Alpha processors have a weak memory model */=0A= #define TCG_GUEST_DEFAULT_MO (0)=0A= =0A= diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h=0A= index aab251b..2be67c2 100644=0A= --- a/target/hppa/cpu.h=0A= +++ b/target/hppa/cpu.h=0A= @@ -30,7 +30,6 @@=0A= basis. It's probably easier to fall back to a strong memory model. */= =0A= #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL=0A= =0A= -#define ALIGNED_ONLY=0A= #define MMU_KERNEL_IDX 0=0A= #define MMU_USER_IDX 3=0A= #define MMU_PHYS_IDX 4=0A= diff --git a/target/mips/cpu.h b/target/mips/cpu.h=0A= index 21c0615..c13cd4e 100644=0A= --- a/target/mips/cpu.h=0A= +++ b/target/mips/cpu.h=0A= @@ -1,8 +1,6 @@=0A= #ifndef MIPS_CPU_H=0A= #define MIPS_CPU_H=0A= =0A= -#define ALIGNED_ONLY=0A= -=0A= #include "cpu-qom.h"=0A= #include "exec/cpu-defs.h"=0A= #include "fpu/softfloat.h"=0A= diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h=0A= index aee733e..ecaa7a1 100644=0A= --- a/target/sh4/cpu.h=0A= +++ b/target/sh4/cpu.h=0A= @@ -23,8 +23,6 @@=0A= #include "cpu-qom.h"=0A= #include "exec/cpu-defs.h"=0A= =0A= -#define ALIGNED_ONLY=0A= -=0A= /* CPU Subtypes */=0A= #define SH_CPU_SH7750 (1 << 0)=0A= #define SH_CPU_SH7750S (1 << 1)=0A= diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h=0A= index 8ed2250..1406f0b 100644=0A= --- a/target/sparc/cpu.h=0A= +++ b/target/sparc/cpu.h=0A= @@ -5,8 +5,6 @@=0A= #include "cpu-qom.h"=0A= #include "exec/cpu-defs.h"=0A= =0A= -#define ALIGNED_ONLY=0A= -=0A= #if !defined(TARGET_SPARC64)=0A= #define TARGET_DPREGS 16=0A= #else=0A= diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h=0A= index 2c27713..0459243 100644=0A= --- a/target/xtensa/cpu.h=0A= +++ b/target/xtensa/cpu.h=0A= @@ -32,8 +32,6 @@=0A= #include "exec/cpu-defs.h"=0A= #include "xtensa-isa.h"=0A= =0A= -#define ALIGNED_ONLY=0A= -=0A= /* Xtensa processors have a weak memory model */=0A= #define TCG_GUEST_DEFAULT_MO (0)=0A= =0A= diff --git a/tcg/tcg.c b/tcg/tcg.c=0A= index be2c33c..8d23fb0 100644=0A= --- a/tcg/tcg.c=0A= +++ b/tcg/tcg.c=0A= @@ -1926,7 +1926,7 @@ static const char * const ldst_name[] =3D=0A= };=0A= =0A= static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] =3D = {=0A= -#ifdef ALIGNED_ONLY=0A= +#ifdef TARGET_ALIGNED_ONLY=0A= [MO_UNALN >> MO_ASHIFT] =3D "un+",=0A= [MO_ALIGN >> MO_ASHIFT] =3D "",=0A= #else=0A= diff --git a/tcg/tcg.h b/tcg/tcg.h=0A= index b411e17..529acb2 100644=0A= --- a/tcg/tcg.h=0A= +++ b/tcg/tcg.h=0A= @@ -333,10 +333,12 @@ typedef enum TCGMemOp {=0A= MO_TE =3D MO_LE,=0A= #endif=0A= =0A= - /* MO_UNALN accesses are never checked for alignment.=0A= + /*=0A= + * MO_UNALN accesses are never checked for alignment.=0A= * MO_ALIGN accesses will result in a call to the CPU's=0A= * do_unaligned_access hook if the guest address is not aligned.=0A= - * The default depends on whether the target CPU defines ALIGNED_ONLY.= =0A= + * The default depends on whether the target CPU defines=0A= + * TARGET_ALIGNED_ONLY.=0A= *=0A= * Some architectures (e.g. ARMv8) need the address which is aligned= =0A= * to a size more than the size of the memory access.=0A= @@ -353,7 +355,7 @@ typedef enum TCGMemOp {=0A= */=0A= MO_ASHIFT =3D 4,=0A= MO_AMASK =3D 7 << MO_ASHIFT,=0A= -#ifdef ALIGNED_ONLY=0A= +#ifdef TARGET_ALIGNED_ONLY=0A= MO_ALIGN =3D 0,=0A= MO_UNALN =3D MO_AMASK,=0A= #else=0A= -- =0A= 1.8.3.1=0A=