From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755920AbbJHT01 (ORCPT ); Thu, 8 Oct 2015 15:26:27 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:49463 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753181AbbJHT0Z (ORCPT ); Thu, 8 Oct 2015 15:26:25 -0400 From: Arnd Bergmann To: "M'boumba Cedric Madianga" Cc: linux-arm-kernel@lists.infradead.org, mcoquelin.stm32@gmail.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, vinod.koul@intel.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Subject: Re: [PATCH 1/4] dt-bindings: Document the STM32 DMA bindings Date: Thu, 08 Oct 2015 21:26:07 +0200 Message-ID: <15651913.U8kb3JZ9vO@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: References: <1444317612-818-1-git-send-email-cedric.madianga@gmail.com> <13614799.2Hi64P0fJ2@wuerfel> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:Am6/vUv2fm5fSh2x/kV9LF9VXdCqa4aXxvIyp00fvSgDx7n1rvd f/kiqT5sDwCnrsyMek0T6b0X0B6QHxgmtPZigXqeqTix5eB69AUVwPDOJ5IOV5OuNh9F5G8 nqiRB+qymStp5g1VcX9A5JgFGENP85mvdqgXSk3B6SQ21cvKr165gL/bvRkWYfyHNm5h3rM zRouatDDdoZq3JO3DMHuw== X-UI-Out-Filterresults: notjunk:1;V01:K0:SjHS8e4GqEA=:XlpRLNt9VLhJpNi/92toef myFxM1oIaG74e2R4kmahG/l29jqrRDFTPqV+oiCJZ9abFRwMAbUV3dBCLOAHNtUejXVGAwb7b zGnXb60CaGWcpHhFAjlkyEIxqAO7/oW9V8c8gYgS7056DMpCY1WDbz0jmA9IVVPitzW8V1FiE J3f/0OtVj1rdOqt/6odtsVp4/WLLfCc5haji8eB1tXhNFKO1vJ0lIARPRZc5VTOgSvOvfSOyF W25zauzh3H5XxFvxS6AJ5EBHdjTWzpDkdLwBcPBBg5oEcdQ5H/RfUH4uVmaLvuRYBQ8mBzk4Q PP0h4vG/wX66OD7u6uMnCDe2aBvGfAPZlbp3DGMxUBCoYA6FjRYQIdDBfRw9q5RyKqwMtaRP4 QMhbFlA5gXZbwjQLh1pQ6R4Rnf+PoylaJIsnXCEEVlb/8xd6HQ6mkpqRwhNu2NQeyX+/fL0U7 NGLzlpnk2iJmbveR+8FTAmZApKZYiHI/CN0ZING5ZE055CzEuGjkq2aYjKy2tFEVVuvc6V56y eV//leq5SMqTODDqMfMr85E9IKMtTUgKXjeg18+FbbG4I7k1wtEYhh0qIAOd93J0wh4klE83o p0U2Cp/h5YcMrVt/obXYyChT4IXKrDu4ClEdOxXHgZiTIu5aYXFz+diovTrMVW/GLzn0EGzR5 Zw3h9st0NIFMDwvVJwzdx6Vy23CoNlFWvwd8d1gDvW5/ti1/92wNIYor9yOjCl7vI6YtNBVcV Tb60BinvgUpx9J/Q Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday 08 October 2015 18:01:23 M'boumba Cedric Madianga wrote: > Hi Arnd, > > 2015-10-08 17:43 GMT+02:00 Arnd Bergmann : > > On Thursday 08 October 2015 17:20:09 M'boumba Cedric Madianga wrote: > >> +Each dmas request consists of 5 cells: > >> +1. A phandle pointing to the STM32 DMA controller > >> +2. The channel id > >> +3. The request line number > >> +4. A 32bit mask specifying the DMA channel configuration > >> > > > > It's fairly unusual to encode the channel id here, rather than > > letting the driver pick one. Is that actually required here? > > Yes it is required as in STM32 platform the channel/request DMA > mapping is done by hardware lines. > So, if one client wants to use DMA, he has to choose the correct > channel/request values according to the DMA mapping of his STM32 > platform. Interesting. So you have seven channels ans seven request lines, with a random but fixed mapping between them? How do you know which channels are available for memory-to-memory transfers? Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH 1/4] dt-bindings: Document the STM32 DMA bindings Date: Thu, 08 Oct 2015 21:26:07 +0200 Message-ID: <15651913.U8kb3JZ9vO@wuerfel> References: <1444317612-818-1-git-send-email-cedric.madianga@gmail.com> <13614799.2Hi64P0fJ2@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Return-path: In-Reply-To: Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: M'boumba Cedric Madianga Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On Thursday 08 October 2015 18:01:23 M'boumba Cedric Madianga wrote: > Hi Arnd, > > 2015-10-08 17:43 GMT+02:00 Arnd Bergmann : > > On Thursday 08 October 2015 17:20:09 M'boumba Cedric Madianga wrote: > >> +Each dmas request consists of 5 cells: > >> +1. A phandle pointing to the STM32 DMA controller > >> +2. The channel id > >> +3. The request line number > >> +4. A 32bit mask specifying the DMA channel configuration > >> > > > > It's fairly unusual to encode the channel id here, rather than > > letting the driver pick one. Is that actually required here? > > Yes it is required as in STM32 platform the channel/request DMA > mapping is done by hardware lines. > So, if one client wants to use DMA, he has to choose the correct > channel/request values according to the DMA mapping of his STM32 > platform. Interesting. So you have seven channels ans seven request lines, with a random but fixed mapping between them? How do you know which channels are available for memory-to-memory transfers? Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: arnd@arndb.de (Arnd Bergmann) Date: Thu, 08 Oct 2015 21:26:07 +0200 Subject: [PATCH 1/4] dt-bindings: Document the STM32 DMA bindings In-Reply-To: References: <1444317612-818-1-git-send-email-cedric.madianga@gmail.com> <13614799.2Hi64P0fJ2@wuerfel> Message-ID: <15651913.U8kb3JZ9vO@wuerfel> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thursday 08 October 2015 18:01:23 M'boumba Cedric Madianga wrote: > Hi Arnd, > > 2015-10-08 17:43 GMT+02:00 Arnd Bergmann : > > On Thursday 08 October 2015 17:20:09 M'boumba Cedric Madianga wrote: > >> +Each dmas request consists of 5 cells: > >> +1. A phandle pointing to the STM32 DMA controller > >> +2. The channel id > >> +3. The request line number > >> +4. A 32bit mask specifying the DMA channel configuration > >> > > > > It's fairly unusual to encode the channel id here, rather than > > letting the driver pick one. Is that actually required here? > > Yes it is required as in STM32 platform the channel/request DMA > mapping is done by hardware lines. > So, if one client wants to use DMA, he has to choose the correct > channel/request values according to the DMA mapping of his STM32 > platform. Interesting. So you have seven channels ans seven request lines, with a random but fixed mapping between them? How do you know which channels are available for memory-to-memory transfers? Arnd