From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ye Li Date: Wed, 14 Aug 2019 10:09:13 +0000 Subject: [U-Boot] [PATCH 6/6] spi: fsl_qspi: Fix flash write issue with small TX FIFO In-Reply-To: <1565777311-1752-1-git-send-email-ye.li@nxp.com> References: <1565777311-1752-1-git-send-email-ye.li@nxp.com> Message-ID: <1565777311-1752-6-git-send-email-ye.li@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The page write sequence in spi-mem is changed with orignal spi-flash. When the max_write_size is set by driver, the orignal sequence is 1. WREN 2. write max_write_size data to flash 3. wait for WIP clean 4. back to #1 if having data remained in a page. The new sequence is: 1. WREN 2. write (max_write_size - command length) data to flash 3. back to #2 if having data remained in a page 4. wait for WIP clean If TX FIFO (max_write_size) is small (for example iMX7ULP only has 64 bytes TX FIFO, while other iMX SOCs have 512 bytes), the driver has to check the WIP in step 3. Otherwise the WIP may set due to previous write is not completed by flash device, then cause current write failed. Signed-off-by: Ye Li --- drivers/spi/fsl_qspi.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index f3cf8e6..450155e 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -22,6 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; #define OFFSET_BITS_MASK GENMASK(23, 0) #define FLASH_STATUS_WEL 0x02 +#define FLASH_STATUS_WIP 0x01 /* SEQID */ #define SEQID_WREN 1 @@ -666,6 +667,27 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) mcr_reg); qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + if (priv->devtype_data->txfifo <= 256) { + status_reg = 0; + do { + WATCHDOG_RESET(); + + qspi_write32(priv->flags, ®s->ipcr, + (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1); + while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) + ; + + reg = qspi_read32(priv->flags, ®s->rbsr); + if (reg & QSPI_RBSR_RDBFL_MASK) { + status_reg = qspi_read32(priv->flags, ®s->rbdr[0]); + status_reg = qspi_endian_xchg(priv, status_reg); + } + qspi_write32(priv->flags, ®s->mcr, + qspi_read32(priv->flags, ®s->mcr) | + QSPI_MCR_CLR_RXF_MASK); + } while ((status_reg & FLASH_STATUS_WIP) == FLASH_STATUS_WIP); + } + status_reg = 0; while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) { WATCHDOG_RESET(); -- 2.7.4