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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v7 41/42] target/sparc: Add TLB entry with attributes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: frederic.konrad@adacore.com, berto@igalia.com, qemu-block@nongnu.org, arikalo@wavecomp.com, pasic@linux.ibm.com, hpoussin@reactos.org, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, lersek@redhat.com, jasowang@redhat.com, jiri@resnulli.us, ehabkost@redhat.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, stefanha@redhat.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, andrew@aj.id.au, claudio.fontana@suse.com, crwulff@gmail.com, laurent@vivier.eu, sundeep.lkml@gmail.com, michael@walle.cc, qemu-ppc@nongnu.org, kbastian@mail.uni-paderborn.de, imammedo@redhat.com, fam@euphon.net, peter.maydell@linaro.org, david@redhat.com, palmer@sifive.com, keith.busch@intel.com, jcmvbkbc@gmail.com, hare@suse.com, sstabellini@kernel.org, andrew.smirnov@gmail.com, deller@gmx.de, magnus.damm@gmail.com, atar4qemu@gmail.com, minyard@acm.org, sw@weilnetz.de, yuval.shaia@oracle.com, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, shorne@gmail.com, qemu-riscv@nongnu.org, i.mitsyanko@gmail.com, cohuck@redhat.com, philmd@redhat.com, amarkovic@wavecomp.com, peter.chubb@nicta.com.au, aurelien@aurel32.net, pburton@wavecomp.com, sagark@eecs.berkeley.edu, green@moxielogic.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, robh@kernel.org, borntraeger@de.ibm.com, joel@jms.id.au, antonynpavlov@gmail.com, chouteau@adacore.com, Andrew.Baumann@microsoft.com, mreitz@redhat.com, walling@linux.ibm.com, dmitry.fleytman@gmail.com, mst@redhat.com, mark.cave-ayland@ilande.co.uk, jslaby@suse.cz, marex@denx.de, proljc@gmail.com, marcandre.lureau@redhat.com, alistair@alistair23.me, paul.durrant@citrix.com, david@gibson.dropbear.id.au, xiaoguangrong.eric@gmail.com, huth@tuxfamily.org, jcd@tribudubois.net, pbonzini@redhat.com, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Append MemTxAttrs to interfaces so we can pass along up coming Invert Endian TTE bit on SPARC64. Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson --- target/sparc/mmu_helper.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index cbd1e91..826e14b 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -88,7 +88,7 @@ static const int perm_table[2][8] =3D { }; static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, + int *prot, int *access_index, MemTxAttrs *= attrs, target_ulong address, int rw, int mmu_idx, target_ulong *page_size) { @@ -219,6 +219,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, target_ulong vaddr; target_ulong page_size; int error_code =3D 0, prot, access_index; + MemTxAttrs attrs =3D {}; /* * TODO: If we ever need tlb_vaddr_to_host for this target, @@ -229,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, assert(!probe); address &=3D TARGET_PAGE_MASK; - error_code =3D get_physical_address(env, &paddr, &prot, &access_index, + error_code =3D get_physical_address(env, &paddr, &prot, &access_index,= &attrs, address, access_type, mmu_idx, &page_size); vaddr =3D address; @@ -490,8 +491,8 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *t= lb, return 0; } -static int get_physical_address_data(CPUSPARCState *env, - hwaddr *physical, int *prot, +static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, + int *prot, MemTxAttrs *attrs, target_ulong address, int rw, int mmu= _idx) { CPUState *cs =3D env_cpu(env); @@ -608,8 +609,8 @@ static int get_physical_address_data(CPUSPARCState *env= , return 1; } -static int get_physical_address_code(CPUSPARCState *env, - hwaddr *physical, int *prot, +static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, + int *prot, MemTxAttrs *attrs, target_ulong address, int mmu_idx) { CPUState *cs =3D env_cpu(env); @@ -686,7 +687,7 @@ static int get_physical_address_code(CPUSPARCState *env= , } static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, + int *prot, int *access_index, MemTxAttrs *= attrs, target_ulong address, int rw, int mmu_idx, target_ulong *page_size) { @@ -716,11 +717,11 @@ static int get_physical_address(CPUSPARCState *env, h= waddr *physical, } if (rw =3D=3D 2) { - return get_physical_address_code(env, physical, prot, address, + return get_physical_address_code(env, physical, prot, attrs, addre= ss, mmu_idx); } else { - return get_physical_address_data(env, physical, prot, address, rw, - mmu_idx); + return get_physical_address_data(env, physical, prot, attrs, addre= ss, + rw, mmu_idx); } } @@ -734,10 +735,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, target_ulong vaddr; hwaddr paddr; target_ulong page_size; + MemTxAttrs attrs =3D {}; int error_code =3D 0, prot, access_index; address &=3D TARGET_PAGE_MASK; - error_code =3D get_physical_address(env, &paddr, &prot, &access_index, + error_code =3D get_physical_address(env, &paddr, &prot, &access_index,= &attrs, address, access_type, mmu_idx, &page_size); if (likely(error_code =3D=3D 0)) { @@ -747,7 +749,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx, + page_size); return true; } if (probe) { @@ -849,9 +852,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env,= hwaddr *phys, { target_ulong page_size; int prot, access_index; + MemTxAttrs attrs =3D {}; - return get_physical_address(env, phys, &prot, &access_index, addr, rw, - mmu_idx, &page_size); + return get_physical_address(env, phys, &prot, &access_index, &attrs, a= ddr, + rw, mmu_idx, &page_size); } #if defined(TARGET_SPARC64) -- 1.8.3.1 ? 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boundary="===============5853881241155194981==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============5853881241155194981== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_15659411776007672btcom_" --_000_15659411776007672btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Append MemTxAttrs to interfaces so we can pass along up coming Invert Endian TTE bit on SPARC64. Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson --- target/sparc/mmu_helper.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index cbd1e91..826e14b 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -88,7 +88,7 @@ static const int perm_table[2][8] =3D { }; static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, + int *prot, int *access_index, MemTxAttrs *= attrs, target_ulong address, int rw, int mmu_idx, target_ulong *page_size) { @@ -219,6 +219,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, target_ulong vaddr; target_ulong page_size; int error_code =3D 0, prot, access_index; + MemTxAttrs attrs =3D {}; /* * TODO: If we ever need tlb_vaddr_to_host for this target, @@ -229,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, assert(!probe); address &=3D TARGET_PAGE_MASK; - error_code =3D get_physical_address(env, &paddr, &prot, &access_index, + error_code =3D get_physical_address(env, &paddr, &prot, &access_index,= &attrs, address, access_type, mmu_idx, &page_size); vaddr =3D address; @@ -490,8 +491,8 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *t= lb, return 0; } -static int get_physical_address_data(CPUSPARCState *env, - hwaddr *physical, int *prot, +static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, + int *prot, MemTxAttrs *attrs, target_ulong address, int rw, int mmu= _idx) { CPUState *cs =3D env_cpu(env); @@ -608,8 +609,8 @@ static int get_physical_address_data(CPUSPARCState *env= , return 1; } -static int get_physical_address_code(CPUSPARCState *env, - hwaddr *physical, int *prot, +static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, + int *prot, MemTxAttrs *attrs, target_ulong address, int mmu_idx) { CPUState *cs =3D env_cpu(env); @@ -686,7 +687,7 @@ static int get_physical_address_code(CPUSPARCState *env= , } static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, + int *prot, int *access_index, MemTxAttrs *= attrs, target_ulong address, int rw, int mmu_idx, target_ulong *page_size) { @@ -716,11 +717,11 @@ static int get_physical_address(CPUSPARCState *env, h= waddr *physical, } if (rw =3D=3D 2) { - return get_physical_address_code(env, physical, prot, address, + return get_physical_address_code(env, physical, prot, attrs, addre= ss, mmu_idx); } else { - return get_physical_address_data(env, physical, prot, address, rw, - mmu_idx); + return get_physical_address_data(env, physical, prot, attrs, addre= ss, + rw, mmu_idx); } } @@ -734,10 +735,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, target_ulong vaddr; hwaddr paddr; target_ulong page_size; + MemTxAttrs attrs =3D {}; int error_code =3D 0, prot, access_index; address &=3D TARGET_PAGE_MASK; - error_code =3D get_physical_address(env, &paddr, &prot, &access_index, + error_code =3D get_physical_address(env, &paddr, &prot, &access_index,= &attrs, address, access_type, mmu_idx, &page_size); if (likely(error_code =3D=3D 0)) { @@ -747,7 +749,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx, + page_size); return true; } if (probe) { @@ -849,9 +852,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env,= hwaddr *phys, { target_ulong page_size; int prot, access_index; + MemTxAttrs attrs =3D {}; - return get_physical_address(env, phys, &prot, &access_index, addr, rw, - mmu_idx, &page_size); + return get_physical_address(env, phys, &prot, &access_index, &attrs, a= ddr, + rw, mmu_idx, &page_size); } #if defined(TARGET_SPARC64) -- 1.8.3.1 ? --_000_15659411776007672btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Append MemTxAttrs to interfaces so we= can pass along up coming Invert
Endian TTE bit on SPARC64.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/mmu_helper.c | 32 ++++++= 3;+++++++++++--------------
 1 file changed, 18 insertions(+), 14 deletions(-)

diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index cbd1e91..826e14b 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -88,7 +88,7 @@ static const int perm_table[2][8] =3D {
 };
 
 static int get_physical_address(CPUSPARCState *env, hwaddr *phys= ical,
-                    = ;            int *prot, int *access_index,
+                   &= nbsp;            int *prot, int *access_index= , MemTxAttrs *attrs,
                    =              target_ulong address, int r= w, int mmu_idx,
                    =              target_ulong *page_size)
 {
@@ -219,6 +219,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr ad= dress, int size,
     target_ulong vaddr;
     target_ulong page_size;
     int error_code =3D 0, prot, access_index;
+    MemTxAttrs attrs =3D {};
 
     /*
      * TODO: If we ever need tlb_vaddr_to_host for thi= s target,
@@ -229,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr ad= dress, int size,
     assert(!probe);
 
     address &=3D TARGET_PAGE_MASK;
-    error_code =3D get_physical_address(env, &paddr, &a= mp;prot, &access_index,
+    error_code =3D get_physical_address(env, &paddr= , &prot, &access_index, &attrs,
                    =                    addres= s, access_type,
                    =                    mmu_id= x, &page_size);
     vaddr =3D address;
@@ -490,8 +491,8 @@ static inline int ultrasparc_tag_match(SparcTL= BEntry *tlb,
     return 0;
 }
 
-static int get_physical_address_data(CPUSPARCState *env,
-                    = ;                 hwaddr *physical,= int *prot,
+static int get_physical_address_data(CPUSPARCState *env, hwaddr *= physical,
+                   &= nbsp;                 int *prot, Me= mTxAttrs *attrs,
                    =                   target_ulong= address, int rw, int mmu_idx)
 {
     CPUState *cs =3D env_cpu(env);
@@ -608,8 +609,8 @@ static int get_physical_address_data(CPUSPARCS= tate *env,
     return 1;
 }
 
-static int get_physical_address_code(CPUSPARCState *env,
-                    = ;                 hwaddr *physical,= int *prot,
+static int get_physical_address_code(CPUSPARCState *env, hwaddr *= physical,
+                   &= nbsp;                 int *prot, Me= mTxAttrs *attrs,
                    =                   target_ulong= address, int mmu_idx)
 {
     CPUState *cs =3D env_cpu(env);
@@ -686,7 +687,7 @@ static int get_physical_address_code(CPUSPARCS= tate *env,
 }
 
 static int get_physical_address(CPUSPARCState *env, hwaddr *phys= ical,
-                    = ;            int *prot, int *access_index,
+                   &= nbsp;            int *prot, int *access_index= , MemTxAttrs *attrs,
                    =              target_ulong address, int r= w, int mmu_idx,
                    =              target_ulong *page_size)
 {
@@ -716,11 +717,11 @@ static int get_physical_address(CPUSPARCStat= e *env, hwaddr *physical,
     }
 
     if (rw =3D=3D 2) {
-        return get_physical_address_code(env, phy= sical, prot, address,
+        return get_physical_address_code(env,= physical, prot, attrs, address,
                    =                      = ; mmu_idx);
     } else {
-        return get_physical_address_data(env, phy= sical, prot, address, rw,
-                    = ;                     mmu= _idx);
+        return get_physical_address_data(env,= physical, prot, attrs, address,
+                   &= nbsp;                    = rw, mmu_idx);
     }
 }
 
@@ -734,10 +735,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr = address, int size,
     target_ulong vaddr;
     hwaddr paddr;
     target_ulong page_size;
+    MemTxAttrs attrs =3D {};
     int error_code =3D 0, prot, access_index;
 
     address &=3D TARGET_PAGE_MASK;
-    error_code =3D get_physical_address(env, &paddr, &a= mp;prot, &access_index,
+    error_code =3D get_physical_address(env, &paddr= , &prot, &access_index, &attrs,
                    =                    addres= s, access_type,
                    =                    mmu_id= x, &page_size);
     if (likely(error_code =3D=3D 0)) {
@@ -747,7 +749,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr ad= dress, int size,
                    =                 env->dmmu.mmu_pr= imary_context,
                    =                 env->dmmu.mmu_se= condary_context);
 
-        tlb_set_page(cs, vaddr, paddr, prot, mmu_= idx, page_size);
+        tlb_set_page_with_attrs(cs, vaddr, pa= ddr, attrs, prot, mmu_idx,
+                   &= nbsp;            page_size);
         return true;
     }
     if (probe) {
@@ -849,9 +852,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCSt= ate *env, hwaddr *phys,
 {
     target_ulong page_size;
     int prot, access_index;
+    MemTxAttrs attrs =3D {};
 
-    return get_physical_address(env, phys, &prot, &= access_index, addr, rw,
-                    = ;            mmu_idx, &page_size);
+    return get_physical_address(env, phys, &prot, &= amp;access_index, &attrs, addr,
+                   &= nbsp;            rw, mmu_idx, &page_size)= ;
 }
 
 #if defined(TARGET_SPARC64)
-- 
1.8.3.1

​

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Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson --- target/sparc/mmu_helper.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index cbd1e91..826e14b 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -88,7 +88,7 @@ static const int perm_table[2][8] =3D { }; static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, + int *prot, int *access_index, MemTxAttrs *= attrs, target_ulong address, int rw, int mmu_idx, target_ulong *page_size) { @@ -219,6 +219,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, target_ulong vaddr; target_ulong page_size; int error_code =3D 0, prot, access_index; + MemTxAttrs attrs =3D {}; /* * TODO: If we ever need tlb_vaddr_to_host for this target, @@ -229,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, assert(!probe); address &=3D TARGET_PAGE_MASK; - error_code =3D get_physical_address(env, &paddr, &prot, &access_index, + error_code =3D get_physical_address(env, &paddr, &prot, &access_index,= &attrs, address, access_type, mmu_idx, &page_size); vaddr =3D address; @@ -490,8 +491,8 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *t= lb, return 0; } -static int get_physical_address_data(CPUSPARCState *env, - hwaddr *physical, int *prot, +static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, + int *prot, MemTxAttrs *attrs, target_ulong address, int rw, int mmu= _idx) { CPUState *cs =3D env_cpu(env); @@ -608,8 +609,8 @@ static int get_physical_address_data(CPUSPARCState *env= , return 1; } -static int get_physical_address_code(CPUSPARCState *env, - hwaddr *physical, int *prot, +static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, + int *prot, MemTxAttrs *attrs, target_ulong address, int mmu_idx) { CPUState *cs =3D env_cpu(env); @@ -686,7 +687,7 @@ static int get_physical_address_code(CPUSPARCState *env= , } static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, + int *prot, int *access_index, MemTxAttrs *= attrs, target_ulong address, int rw, int mmu_idx, target_ulong *page_size) { @@ -716,11 +717,11 @@ static int get_physical_address(CPUSPARCState *env, h= waddr *physical, } if (rw =3D=3D 2) { - return get_physical_address_code(env, physical, prot, address, + return get_physical_address_code(env, physical, prot, attrs, addre= ss, mmu_idx); } else { - return get_physical_address_data(env, physical, prot, address, rw, - mmu_idx); + return get_physical_address_data(env, physical, prot, attrs, addre= ss, + rw, mmu_idx); } } @@ -734,10 +735,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, target_ulong vaddr; hwaddr paddr; target_ulong page_size; + MemTxAttrs attrs =3D {}; int error_code =3D 0, prot, access_index; address &=3D TARGET_PAGE_MASK; - error_code =3D get_physical_address(env, &paddr, &prot, &access_index, + error_code =3D get_physical_address(env, &paddr, &prot, &access_index,= &attrs, address, access_type, mmu_idx, &page_size); if (likely(error_code =3D=3D 0)) { @@ -747,7 +749,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx, + page_size); return true; } if (probe) { @@ -849,9 +852,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env,= hwaddr *phys, { target_ulong page_size; int prot, access_index; + MemTxAttrs attrs =3D {}; - return get_physical_address(env, phys, &prot, &access_index, addr, rw, - mmu_idx, &page_size); + return get_physical_address(env, phys, &prot, &access_index, &attrs, a= ddr, + rw, mmu_idx, &page_size); } #if defined(TARGET_SPARC64) -- 1.8.3.1 ? --_000_15659411776007672btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Append MemTxAttrs to interfaces so we= can pass along up coming Invert
Endian TTE bit on SPARC64.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/mmu_helper.c | 32 ++++++= 3;+++++++++++--------------
 1 file changed, 18 insertions(+), 14 deletions(-)

diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index cbd1e91..826e14b 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -88,7 +88,7 @@ static const int perm_table[2][8] =3D {
 };
 
 static int get_physical_address(CPUSPARCState *env, hwaddr *phys= ical,
-                    = ;            int *prot, int *access_index,
+                   &= nbsp;            int *prot, int *access_index= , MemTxAttrs *attrs,
                    =              target_ulong address, int r= w, int mmu_idx,
                    =              target_ulong *page_size)
 {
@@ -219,6 +219,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr ad= dress, int size,
     target_ulong vaddr;
     target_ulong page_size;
     int error_code =3D 0, prot, access_index;
+    MemTxAttrs attrs =3D {};
 
     /*
      * TODO: If we ever need tlb_vaddr_to_host for thi= s target,
@@ -229,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr ad= dress, int size,
     assert(!probe);
 
     address &=3D TARGET_PAGE_MASK;
-    error_code =3D get_physical_address(env, &paddr, &a= mp;prot, &access_index,
+    error_code =3D get_physical_address(env, &paddr= , &prot, &access_index, &attrs,
                    =                    addres= s, access_type,
                    =                    mmu_id= x, &page_size);
     vaddr =3D address;
@@ -490,8 +491,8 @@ static inline int ultrasparc_tag_match(SparcTL= BEntry *tlb,
     return 0;
 }
 
-static int get_physical_address_data(CPUSPARCState *env,
-                    = ;                 hwaddr *physical,= int *prot,
+static int get_physical_address_data(CPUSPARCState *env, hwaddr *= physical,
+                   &= nbsp;                 int *prot, Me= mTxAttrs *attrs,
                    =                   target_ulong= address, int rw, int mmu_idx)
 {
     CPUState *cs =3D env_cpu(env);
@@ -608,8 +609,8 @@ static int get_physical_address_data(CPUSPARCS= tate *env,
     return 1;
 }
 
-static int get_physical_address_code(CPUSPARCState *env,
-                    = ;                 hwaddr *physical,= int *prot,
+static int get_physical_address_code(CPUSPARCState *env, hwaddr *= physical,
+                   &= nbsp;                 int *prot, Me= mTxAttrs *attrs,
                    =                   target_ulong= address, int mmu_idx)
 {
     CPUState *cs =3D env_cpu(env);
@@ -686,7 +687,7 @@ static int get_physical_address_code(CPUSPARCS= tate *env,
 }
 
 static int get_physical_address(CPUSPARCState *env, hwaddr *phys= ical,
-                    = ;            int *prot, int *access_index,
+                   &= nbsp;            int *prot, int *access_index= , MemTxAttrs *attrs,
                    =              target_ulong address, int r= w, int mmu_idx,
                    =              target_ulong *page_size)
 {
@@ -716,11 +717,11 @@ static int get_physical_address(CPUSPARCStat= e *env, hwaddr *physical,
     }
 
     if (rw =3D=3D 2) {
-        return get_physical_address_code(env, phy= sical, prot, address,
+        return get_physical_address_code(env,= physical, prot, attrs, address,
                    =                      = ; mmu_idx);
     } else {
-        return get_physical_address_data(env, phy= sical, prot, address, rw,
-                    = ;                     mmu= _idx);
+        return get_physical_address_data(env,= physical, prot, attrs, address,
+                   &= nbsp;                    = rw, mmu_idx);
     }
 }
 
@@ -734,10 +735,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr = address, int size,
     target_ulong vaddr;
     hwaddr paddr;
     target_ulong page_size;
+    MemTxAttrs attrs =3D {};
     int error_code =3D 0, prot, access_index;
 
     address &=3D TARGET_PAGE_MASK;
-    error_code =3D get_physical_address(env, &paddr, &a= mp;prot, &access_index,
+    error_code =3D get_physical_address(env, &paddr= , &prot, &access_index, &attrs,
                    =                    addres= s, access_type,
                    =                    mmu_id= x, &page_size);
     if (likely(error_code =3D=3D 0)) {
@@ -747,7 +749,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr ad= dress, int size,
                    =                 env->dmmu.mmu_pr= imary_context,
                    =                 env->dmmu.mmu_se= condary_context);
 
-        tlb_set_page(cs, vaddr, paddr, prot, mmu_= idx, page_size);
+        tlb_set_page_with_attrs(cs, vaddr, pa= ddr, attrs, prot, mmu_idx,
+                   &= nbsp;            page_size);
         return true;
     }
     if (probe) {
@@ -849,9 +852,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCSt= ate *env, hwaddr *phys,
 {
     target_ulong page_size;
     int prot, access_index;
+    MemTxAttrs attrs =3D {};
 
-    return get_physical_address(env, phys, &prot, &= access_index, addr, rw,
-                    = ;            mmu_idx, &page_size);
+    return get_physical_address(env, phys, &prot, &= amp;access_index, &attrs, addr,
+                   &= nbsp;            rw, mmu_idx, &page_size)= ;
 }
 
 #if defined(TARGET_SPARC64)
-- 
1.8.3.1

​

--_000_15659411776007672btcom_--