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Mon, 19 Aug 2019 22:09:23 +0000 From: "Shirley Her (SC)" To: "adrian.hunter@intel.com" , "ulf.hansson@linaro.org" , "linux-mmc@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: "Chevron Li (WH)" , "Shaper Liu (WH)" , "Louis Lu (TP)" , "Xiaoguang Yu (WH)" , "max.huang@bayhbutech.com" , "Shirley Her (SC)" Subject: Subject: [PATCH V7 2/3] mmc: sdhci-pci-o2micro: Move functions in preparation to fix DLL lock phase shift issue Thread-Topic: Subject: [PATCH V7 2/3] mmc: sdhci-pci-o2micro: Move functions in preparation to fix DLL lock phase shift issue Thread-Index: AQHVVtrCDQhIjjDlrUWEGKagsZN8YQ== Date: Mon, 19 Aug 2019 22:09:23 +0000 Message-ID: <1566252561-5144-1-git-send-email-shirley.her@bayhubtech.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR05CA0025.namprd05.prod.outlook.com (2603:10b6:a03:c0::38) To MWHPR16MB1455.namprd16.prod.outlook.com (2603:10b6:320:28::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=shirley.her@bayhubtech.com; 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received-spf: None (protection.outlook.com: bayhubtech.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: XB+binCcNUN8eO+g+rBXRdqTN0lcUkyJoLs2/ldr3VyLyMzbQw8B4ISn9y9dFOaME7uun10UBY/lF31QXcMUUSC+/bIrl2ofyY8L0JAPanh0IUbmtA4dZcr8/vrTidGY4LXqKCNGO7J7FGmDnpfGDB7q4R0wTLxEElW3M2DwKWXCNm5GEuALB0yNijyPcQpCnzJH9V59CT35mHq8XcGtp6/+U01j8NQNg+rcYVBE6Pn/p8ZtJ8ie+7+KLa/q/IM0lJ1l70rqZMqp3YdRFsUETgZXay9CFScTKZN9DLPA91nt9/rzsJ2vK6Q+ikqbV5wxe2oFhvDVeABNumd1WrDyHkyUW3ggoCGuDazw4LUtPPioh4NR/IAdWAqYqC5cmYQrMgUH0bBOaMx59EhPdPkK8lMHzA7qiwqN6amNmTSiASo= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: bayhubtech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9dc32291-dddd-4370-8306-08d724f1e46c X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Aug 2019 22:09:23.6448 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 0a7aae2b-8f2e-44df-ba2f-42de7f93c642 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: CRCR1HOllOHjLBCm62Th9NwmdnBLOnMkEBqfNet5xW2bobrwEPHkOZ5PNr1pN0AWo4RLPLjxGvCJh4rUVjFFfL/JejkFXqZyZqk04XOvvcQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR16MB0029 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move functions in preparation to fix DLL lock phase shift issue Signed-off-by:Shirley Her --- change in V7: 1. change subject to match the patch 2. move functions in preparation to fix DLL lock phase shift issue change in V6: 1. change subject and commit message to match the patch 2. modify the get CD status functions 3. re-arrange the order of some functions change in V5: 1. split 2 patches into 3 patches 2. make dll_adjust_count start from 0 3. fix ret overwritten issue 4. use break instead of goto change in V4: 1. add a bug fix for V3 change in V3: 1. add more explanation in dll_recovery and execute_tuning function 2. move dll_adjust_count to O2_host struct 3. fix some coding style error 4. renaming O2_PLL_WDT_CONTROL1 TO O2_PLL_DLL_WDT_CONTROL1 change in V2: 1. use usleep_range instead of udelay 2. move dll_adjust_count to sdhci-pci-o2micro.c chagne in V1: 1. add error recovery function to relock DLL with correct phase 2. retuning HS200 after DLL locked --- drivers/mmc/host/sdhci-pci-o2micro.c | 186 +++++++++++++++++--------------= ---- 1 file changed, 93 insertions(+), 93 deletions(-) diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-= pci-o2micro.c index b3a33d9..021e481 100644 --- a/drivers/mmc/host/sdhci-pci-o2micro.c +++ b/drivers/mmc/host/sdhci-pci-o2micro.c @@ -58,6 +58,99 @@ =20 #define O2_SD_DETECT_SETTING 0x324 =20 +static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) +{ + ktime_t timeout; + u32 scratch32; + + /* Wait max 50 ms */ + timeout =3D ktime_add_ms(ktime_get(), 50); + while (1) { + bool timedout =3D ktime_after(ktime_get(), timeout); + + scratch32 =3D sdhci_readl(host, SDHCI_PRESENT_STATE); + if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT + =3D=3D (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) + break; + + if (timedout) { + pr_err("%s: Card Detect debounce never finished.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return; + } + udelay(10); + } +} + +static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) +{ + ktime_t timeout; + u16 scratch; + u32 scratch32; + + /* PLL software reset */ + scratch32 =3D sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); + scratch32 |=3D O2_PLL_SOFT_RESET; + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); + udelay(1); + scratch32 &=3D ~(O2_PLL_SOFT_RESET); + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); + + /* PLL force active */ + scratch32 |=3D O2_PLL_FORCE_ACTIVE; + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); + + /* Wait max 20 ms */ + timeout =3D ktime_add_ms(ktime_get(), 20); + while (1) { + bool timedout =3D ktime_after(ktime_get(), timeout); + + scratch =3D sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); + if (scratch & O2_PLL_LOCK_STATUS) + break; + if (timedout) { + pr_err("%s: Internal clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + goto out; + } + udelay(10); + } + + /* Wait for card detect finish */ + udelay(1); + sdhci_o2_wait_card_detect_stable(host); + +out: + /* Cancel PLL force active */ + scratch32 =3D sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); + scratch32 &=3D ~O2_PLL_FORCE_ACTIVE; + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); +} + +static int sdhci_o2_get_cd(struct mmc_host *mmc) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + + sdhci_o2_enable_internal_clock(host); + + return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); +} + +static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) +{ + u32 scratch_32; + pci_read_config_dword(chip->pdev, + O2_SD_PLL_SETTING, &scratch_32); + + scratch_32 &=3D 0x0000FFFF; + scratch_32 |=3D value; + + pci_write_config_dword(chip->pdev, + O2_SD_PLL_SETTING, scratch_32); +} + static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) { u16 reg; @@ -136,19 +229,6 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mm= c, u32 opcode) return 0; } =20 -static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) -{ - u32 scratch_32; - pci_read_config_dword(chip->pdev, - O2_SD_PLL_SETTING, &scratch_32); - - scratch_32 &=3D 0x0000FFFF; - scratch_32 |=3D value; - - pci_write_config_dword(chip->pdev, - O2_SD_PLL_SETTING, scratch_32); -} - static void o2_pci_led_enable(struct sdhci_pci_chip *chip) { int ret; @@ -284,86 +364,6 @@ static void sdhci_pci_o2_enable_msi(struct sdhci_pci_c= hip *chip, host->irq =3D pci_irq_vector(chip->pdev, 0); } =20 -static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) -{ - ktime_t timeout; - u32 scratch32; - - /* Wait max 50 ms */ - timeout =3D ktime_add_ms(ktime_get(), 50); - while (1) { - bool timedout =3D ktime_after(ktime_get(), timeout); - - scratch32 =3D sdhci_readl(host, SDHCI_PRESENT_STATE); - if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT - =3D=3D (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) - break; - - if (timedout) { - pr_err("%s: Card Detect debounce never finished.\n", - mmc_hostname(host->mmc)); - sdhci_dumpregs(host); - return; - } - udelay(10); - } -} - -static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) -{ - ktime_t timeout; - u16 scratch; - u32 scratch32; - - /* PLL software reset */ - scratch32 =3D sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); - scratch32 |=3D O2_PLL_SOFT_RESET; - sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); - udelay(1); - scratch32 &=3D ~(O2_PLL_SOFT_RESET); - sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); - - /* PLL force active */ - scratch32 |=3D O2_PLL_FORCE_ACTIVE; - sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); - - /* Wait max 20 ms */ - timeout =3D ktime_add_ms(ktime_get(), 20); - while (1) { - bool timedout =3D ktime_after(ktime_get(), timeout); - - scratch =3D sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); - if (scratch & O2_PLL_LOCK_STATUS) - break; - if (timedout) { - pr_err("%s: Internal clock never stabilised.\n", - mmc_hostname(host->mmc)); - sdhci_dumpregs(host); - goto out; - } - udelay(10); - } - - /* Wait for card detect finish */ - udelay(1); - sdhci_o2_wait_card_detect_stable(host); - -out: - /* Cancel PLL force active */ - scratch32 =3D sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); - scratch32 &=3D ~O2_PLL_FORCE_ACTIVE; - sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); -} - -static int sdhci_o2_get_cd(struct mmc_host *mmc) -{ - struct sdhci_host *host =3D mmc_priv(mmc); - - sdhci_o2_enable_internal_clock(host); - - return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); -} - static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) { /* Enable internal clock */ --=20 2.7.4