From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8A85C3A5A1 for ; Thu, 22 Aug 2019 12:05:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9AE47233FD for ; Thu, 22 Aug 2019 12:05:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388346AbfHVMFr (ORCPT ); Thu, 22 Aug 2019 08:05:47 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:23713 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1731326AbfHVMFr (ORCPT ); Thu, 22 Aug 2019 08:05:47 -0400 X-UUID: 8ad007a033e94d2c86504cb82cb2715a-20190822 X-UUID: 8ad007a033e94d2c86504cb82cb2715a-20190822 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1573296079; Thu, 22 Aug 2019 20:05:31 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS32DR.mediatek.inc (172.27.6.104) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 20:05:29 +0800 Received: from [10.17.3.153] (172.27.4.253) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 20:05:28 +0800 Message-ID: <1566475533.11621.18.camel@mhfsdcap03> Subject: Re: [PATCH v10 09/23] iommu/io-pgtable-arm-v7s: Extend to support PA[33:32] for MediaTek From: Yong Wu To: Will Deacon , Robin Murphy CC: , , Nicolas Boichat , , , , Joerg Roedel , , Evan Green , Tomasz Figa , , Rob Herring , , Matthias Brugger , , , Matthias Kaehlcke , Date: Thu, 22 Aug 2019 20:05:33 +0800 In-Reply-To: <20190822112836.efodtwu3souq3uwa@willie-the-truck> References: <1566395606-7975-1-git-send-email-yong.wu@mediatek.com> <1566395606-7975-10-git-send-email-yong.wu@mediatek.com> <20190821152448.qmoqjh5zznfpdi6n@willie-the-truck> <1566464186.11621.7.camel@mhfsdcap03> <10d5122d-3375-161b-9356-2ddfc1c835bd@arm.com> <20190822101749.3kwzd5lb7zinsord@willie-the-truck> <20190822112836.efodtwu3souq3uwa@willie-the-truck> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: F20067B59D18F1DAE1600790624773E385B1897B1B418F35B0B8F7CF6BE8012E2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks very much for viewing this so quickly. On Thu, 2019-08-22 at 12:28 +0100, Will Deacon wrote: > On Thu, Aug 22, 2019 at 11:57:11AM +0100, Robin Murphy wrote: > > On 2019-08-22 11:17 am, Will Deacon wrote: > > > On Thu, Aug 22, 2019 at 11:08:58AM +0100, Robin Murphy wrote: > > > > On 2019-08-22 9:56 am, Yong Wu wrote: > > > > > On Wed, 2019-08-21 at 16:24 +0100, Will Deacon wrote: > > > > > > On Wed, Aug 21, 2019 at 09:53:12PM +0800, Yong Wu wrote: > > > > > > > MediaTek extend the arm v7s descriptor to support up to 34 bits PA where > > > > > > > the bit32 and bit33 are encoded in the bit9 and bit4 of the PTE > > > > > > > respectively. Meanwhile the iova still is 32bits. > > > > > > > > > > > > > > Regarding whether the pagetable address could be over 4GB, the mt8183 > > > > > > > support it while the previous mt8173 don't, thus keep it as is. > > > > > > > > > > > > > > Signed-off-by: Yong Wu > > > > > > > --- > > > > > > > drivers/iommu/io-pgtable-arm-v7s.c | 32 +++++++++++++++++++++++++------- > > > > > > > include/linux/io-pgtable.h | 7 +++---- > > > > > > > 2 files changed, 28 insertions(+), 11 deletions(-) > > > > > > > > > > > > [...] > > > > > > > > > > > > > @@ -731,7 +747,9 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > > > > > > > { > > > > > > > struct arm_v7s_io_pgtable *data; > > > > > > > - if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS) > > > > > > > + if (cfg->ias > ARM_V7S_ADDR_BITS || > > > > > > > + (cfg->oas > ARM_V7S_ADDR_BITS && > > > > > > > + !(cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT))) > > > > > > > > > > > > Please can you instead change arm_v7s_alloc_pgtable() so that it allows an > > > > > > ias of up to 34 when the IO_PGTABLE_QUIRK_ARM_MTK_EXT is set? > > > > > > > > > > Here I only simply skip the oas checking for our case. then which way do > > > > > your prefer? something like you commented before:? > > > > > > > > > > > > > > > if (cfg->ias > ARM_V7S_ADDR_BITS) > > > > > return NULL; > > > > > > > > > > if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT) { > > > > > if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) > > > > > cfg->oas = min(cfg->oas, ARM_V7S_ADDR_BITS); > > > > > else if (cfg->oas > 34) > > > > > return NULL; > > > > > } else if (cfg->oas > ARM_V7S_ADDR_BITS) { > > > > > return NULL; > > > > > } > > > > > > > > All it should take is something like: > > > > > > > > if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT) > > > > max_oas = 34; > > > > else > > > > max_oas = 32; > > > > if (cfg->oas > max_oas) > > > > return NULL; > > > > > > > > or even just: > > > > > > > > if (cfg->oas > 32 || > > > > (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT && cfg->oas > 34)) > > > > return NULL; > > > > > > > > (and if we prefer the latter style, perhaps we could introduce some kind of > > > > "is_mtk_4gb()" helper to save on verbosity) > > > > > > I wondered the same thing, but another place we'd want the check is in > > > iopte_to_paddr() which probably needs the PHYS_ADDR_T check to avoid GCC > > > warnings, although I didn't try it. > > > > I'm pretty sure I confirmed that "paddr |= BIT_ULL(32)" doesn't warn when > > phys_addt_t is 32-bit - it's well-defined unsigned integer truncation after > > all, and if GCC starts warning about all the valid no-op code it optimises > > away then it's going to run up against IS_ENABLED() first and foremost ;) > > You're quite right, although we live in a world where GCC shouts at us about > missing comments in switch statements so I think my worry was justified! > > > > So if we did: > > > > > > static bool cfg_mtk_ext_enabled(struct io_pgtable_cfg *cfg) > > > { > > > return IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && > > > cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT; > > > } > > > > > > Then I suppose we could do this in _alloc(): > > > > > > if (cfg->oas > cfg_mtk_ext_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS) > > > return NULL; > > ^^ Apparantly, I left the bracketting here as an exercise to the reader. > > > > > > > and then this in iopte_to_paddr(): > > > > > > [...] > > > > > > paddr = pte & mask; > > > if (!cfg_mtk_ext_enabled(cfg)) > > > return paddr; > > > > > > if (pte & ARM_V7S_ATTR_MTK_PA_BIT32) > > > paddr |= ... > > > > > > [...] > > > > > > What do you reckon? > > > > Yeah, that's the general shape of things I was picturing - I'm not that > > fussed about the PHYS_ADDR_T_64BIT thing, especially if it's wrapped up in > > just one place, so if you do want to keep it as belt-and-braces I'll just > > consider it a slight code size optimisation for 32-bit builds. > > Ok, great. Yong Wu -- are you ok respinning with the above + missing > brackets? Of course I can. NearlyAll the interface in this file is prefixed with "arm_v7s_", so does the new interface also need it?, like arm_v7s_is_mtk_enabled. And keep the iopte_to_paddr and paddr_to_iopte symmetrical. Then the final patch would looks like below, is it ok? +static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg) +{ + return IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && + (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT); +} + static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl, struct io_pgtable_cfg *cfg) { - return paddr & ARM_V7S_LVL_MASK(lvl); + arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl); + + if (!arm_v7s_is_mtk_enabled(cfg)) + return pte; + + if (paddr & BIT_ULL(32)) + pte |= ARM_V7S_ATTR_MTK_PA_BIT32; + if (paddr & BIT_ULL(33)) + pte |= ARM_V7S_ATTR_MTK_PA_BIT33; + return pte; } static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, struct io_pgtable_cfg *cfg) { arm_v7s_iopte mask; + phys_addr_t paddr; if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) mask = ARM_V7S_TABLE_MASK; @@ -194,7 +212,15 @@ static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, else mask = ARM_V7S_LVL_MASK(lvl); - return pte & mask; + paddr = pte & mask; + if (!arm_v7s_is_mtk_enabled(cfg)) + return paddr; + + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32) + paddr |= BIT_ULL(32); + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33) + paddr |= BIT_ULL(33); + return paddr; } static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl, @@ -315,9 +341,6 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl, if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)) pte |= ARM_V7S_ATTR_NS_SECTION; - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT) - pte |= ARM_V7S_ATTR_MTK_4GB; - return pte; } @@ -731,7 +754,10 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, { struct arm_v7s_io_pgtable *data; - if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS) + if (cfg->ias > ARM_V7S_ADDR_BITS) + return NULL; + + if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) return NULL; > > Will From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yong Wu Subject: Re: [PATCH v10 09/23] iommu/io-pgtable-arm-v7s: Extend to support PA[33:32] for MediaTek Date: Thu, 22 Aug 2019 20:05:33 +0800 Message-ID: <1566475533.11621.18.camel@mhfsdcap03> References: <1566395606-7975-1-git-send-email-yong.wu@mediatek.com> <1566395606-7975-10-git-send-email-yong.wu@mediatek.com> <20190821152448.qmoqjh5zznfpdi6n@willie-the-truck> <1566464186.11621.7.camel@mhfsdcap03> <10d5122d-3375-161b-9356-2ddfc1c835bd@arm.com> <20190822101749.3kwzd5lb7zinsord@willie-the-truck> <20190822112836.efodtwu3souq3uwa@willie-the-truck> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190822112836.efodtwu3souq3uwa@willie-the-truck> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Will Deacon , Robin Murphy Cc: youlin.pei-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Nicolas Boichat , cui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, Tomasz Figa , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Evan Green , chao.hao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, Rob Herring , linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Matthias Brugger , ming-fan.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, anan.sun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, Matthias Kaehlcke , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org Thanks very much for viewing this so quickly. On Thu, 2019-08-22 at 12:28 +0100, Will Deacon wrote: > On Thu, Aug 22, 2019 at 11:57:11AM +0100, Robin Murphy wrote: > > On 2019-08-22 11:17 am, Will Deacon wrote: > > > On Thu, Aug 22, 2019 at 11:08:58AM +0100, Robin Murphy wrote: > > > > On 2019-08-22 9:56 am, Yong Wu wrote: > > > > > On Wed, 2019-08-21 at 16:24 +0100, Will Deacon wrote: > > > > > > On Wed, Aug 21, 2019 at 09:53:12PM +0800, Yong Wu wrote: > > > > > > > MediaTek extend the arm v7s descriptor to support up to 34 bits PA where > > > > > > > the bit32 and bit33 are encoded in the bit9 and bit4 of the PTE > > > > > > > respectively. Meanwhile the iova still is 32bits. > > > > > > > > > > > > > > Regarding whether the pagetable address could be over 4GB, the mt8183 > > > > > > > support it while the previous mt8173 don't, thus keep it as is. > > > > > > > > > > > > > > Signed-off-by: Yong Wu > > > > > > > --- > > > > > > > drivers/iommu/io-pgtable-arm-v7s.c | 32 +++++++++++++++++++++++++------- > > > > > > > include/linux/io-pgtable.h | 7 +++---- > > > > > > > 2 files changed, 28 insertions(+), 11 deletions(-) > > > > > > > > > > > > [...] > > > > > > > > > > > > > @@ -731,7 +747,9 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > > > > > > > { > > > > > > > struct arm_v7s_io_pgtable *data; > > > > > > > - if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS) > > > > > > > + if (cfg->ias > ARM_V7S_ADDR_BITS || > > > > > > > + (cfg->oas > ARM_V7S_ADDR_BITS && > > > > > > > + !(cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT))) > > > > > > > > > > > > Please can you instead change arm_v7s_alloc_pgtable() so that it allows an > > > > > > ias of up to 34 when the IO_PGTABLE_QUIRK_ARM_MTK_EXT is set? > > > > > > > > > > Here I only simply skip the oas checking for our case. then which way do > > > > > your prefer? something like you commented before:? > > > > > > > > > > > > > > > if (cfg->ias > ARM_V7S_ADDR_BITS) > > > > > return NULL; > > > > > > > > > > if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT) { > > > > > if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) > > > > > cfg->oas = min(cfg->oas, ARM_V7S_ADDR_BITS); > > > > > else if (cfg->oas > 34) > > > > > return NULL; > > > > > } else if (cfg->oas > ARM_V7S_ADDR_BITS) { > > > > > return NULL; > > > > > } > > > > > > > > All it should take is something like: > > > > > > > > if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT) > > > > max_oas = 34; > > > > else > > > > max_oas = 32; > > > > if (cfg->oas > max_oas) > > > > return NULL; > > > > > > > > or even just: > > > > > > > > if (cfg->oas > 32 || > > > > (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT && cfg->oas > 34)) > > > > return NULL; > > > > > > > > (and if we prefer the latter style, perhaps we could introduce some kind of > > > > "is_mtk_4gb()" helper to save on verbosity) > > > > > > I wondered the same thing, but another place we'd want the check is in > > > iopte_to_paddr() which probably needs the PHYS_ADDR_T check to avoid GCC > > > warnings, although I didn't try it. > > > > I'm pretty sure I confirmed that "paddr |= BIT_ULL(32)" doesn't warn when > > phys_addt_t is 32-bit - it's well-defined unsigned integer truncation after > > all, and if GCC starts warning about all the valid no-op code it optimises > > away then it's going to run up against IS_ENABLED() first and foremost ;) > > You're quite right, although we live in a world where GCC shouts at us about > missing comments in switch statements so I think my worry was justified! > > > > So if we did: > > > > > > static bool cfg_mtk_ext_enabled(struct io_pgtable_cfg *cfg) > > > { > > > return IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && > > > cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT; > > > } > > > > > > Then I suppose we could do this in _alloc(): > > > > > > if (cfg->oas > cfg_mtk_ext_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS) > > > return NULL; > > ^^ Apparantly, I left the bracketting here as an exercise to the reader. > > > > > > > and then this in iopte_to_paddr(): > > > > > > [...] > > > > > > paddr = pte & mask; > > > if (!cfg_mtk_ext_enabled(cfg)) > > > return paddr; > > > > > > if (pte & ARM_V7S_ATTR_MTK_PA_BIT32) > > > paddr |= ... > > > > > > [...] > > > > > > What do you reckon? > > > > Yeah, that's the general shape of things I was picturing - I'm not that > > fussed about the PHYS_ADDR_T_64BIT thing, especially if it's wrapped up in > > just one place, so if you do want to keep it as belt-and-braces I'll just > > consider it a slight code size optimisation for 32-bit builds. > > Ok, great. Yong Wu -- are you ok respinning with the above + missing > brackets? Of course I can. NearlyAll the interface in this file is prefixed with "arm_v7s_", so does the new interface also need it?, like arm_v7s_is_mtk_enabled. And keep the iopte_to_paddr and paddr_to_iopte symmetrical. Then the final patch would looks like below, is it ok? +static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg) +{ + return IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && + (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT); +} + static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl, struct io_pgtable_cfg *cfg) { - return paddr & ARM_V7S_LVL_MASK(lvl); + arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl); + + if (!arm_v7s_is_mtk_enabled(cfg)) + return pte; + + if (paddr & BIT_ULL(32)) + pte |= ARM_V7S_ATTR_MTK_PA_BIT32; + if (paddr & BIT_ULL(33)) + pte |= ARM_V7S_ATTR_MTK_PA_BIT33; + return pte; } static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, struct io_pgtable_cfg *cfg) { arm_v7s_iopte mask; + phys_addr_t paddr; if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) mask = ARM_V7S_TABLE_MASK; @@ -194,7 +212,15 @@ static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, else mask = ARM_V7S_LVL_MASK(lvl); - return pte & mask; + paddr = pte & mask; + if (!arm_v7s_is_mtk_enabled(cfg)) + return paddr; + + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32) + paddr |= BIT_ULL(32); + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33) + paddr |= BIT_ULL(33); + return paddr; } static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl, @@ -315,9 +341,6 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl, if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)) pte |= ARM_V7S_ATTR_NS_SECTION; - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT) - pte |= ARM_V7S_ATTR_MTK_4GB; - return pte; } @@ -731,7 +754,10 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, { struct arm_v7s_io_pgtable *data; - if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS) + if (cfg->ias > ARM_V7S_ADDR_BITS) + return NULL; + + if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) return NULL; > > Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A9C9C3A5A1 for ; Thu, 22 Aug 2019 12:05:44 +0000 (UTC) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB0ED233FC for ; Thu, 22 Aug 2019 12:05:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DB0ED233FC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=iommu-bounces@lists.linux-foundation.org Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 97D7BF90; Thu, 22 Aug 2019 12:05:43 +0000 (UTC) Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id CD2EFF87 for ; Thu, 22 Aug 2019 12:05:42 +0000 (UTC) X-Greylist: from auto-whitelisted by SQLgrey-1.7.6 Received: from mailgw02.mediatek.com (unknown [1.203.163.81]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 6DC4E67F for ; Thu, 22 Aug 2019 12:05:41 +0000 (UTC) X-UUID: 8ad007a033e94d2c86504cb82cb2715a-20190822 X-UUID: 8ad007a033e94d2c86504cb82cb2715a-20190822 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1573296079; Thu, 22 Aug 2019 20:05:31 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS32DR.mediatek.inc (172.27.6.104) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 20:05:29 +0800 Received: from [10.17.3.153] (172.27.4.253) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 20:05:28 +0800 Message-ID: <1566475533.11621.18.camel@mhfsdcap03> Subject: Re: [PATCH v10 09/23] iommu/io-pgtable-arm-v7s: Extend to support PA[33:32] for MediaTek From: Yong Wu To: Will Deacon , Robin Murphy Date: Thu, 22 Aug 2019 20:05:33 +0800 In-Reply-To: <20190822112836.efodtwu3souq3uwa@willie-the-truck> References: <1566395606-7975-1-git-send-email-yong.wu@mediatek.com> <1566395606-7975-10-git-send-email-yong.wu@mediatek.com> <20190821152448.qmoqjh5zznfpdi6n@willie-the-truck> <1566464186.11621.7.camel@mhfsdcap03> <10d5122d-3375-161b-9356-2ddfc1c835bd@arm.com> <20190822101749.3kwzd5lb7zinsord@willie-the-truck> <20190822112836.efodtwu3souq3uwa@willie-the-truck> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: F20067B59D18F1DAE1600790624773E385B1897B1B418F35B0B8F7CF6BE8012E2000:8 X-MTK: N Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , cui.zhang@mediatek.com, srv_heupstream@mediatek.com, Tomasz Figa , linux-kernel@vger.kernel.org, Evan Green , chao.hao@mediatek.com, iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Matthias Kaehlcke , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: iommu-bounces@lists.linux-foundation.org Errors-To: iommu-bounces@lists.linux-foundation.org Thanks very much for viewing this so quickly. On Thu, 2019-08-22 at 12:28 +0100, Will Deacon wrote: > On Thu, Aug 22, 2019 at 11:57:11AM +0100, Robin Murphy wrote: > > On 2019-08-22 11:17 am, Will Deacon wrote: > > > On Thu, Aug 22, 2019 at 11:08:58AM +0100, Robin Murphy wrote: > > > > On 2019-08-22 9:56 am, Yong Wu wrote: > > > > > On Wed, 2019-08-21 at 16:24 +0100, Will Deacon wrote: > > > > > > On Wed, Aug 21, 2019 at 09:53:12PM +0800, Yong Wu wrote: > > > > > > > MediaTek extend the arm v7s descriptor to support up to 34 bits PA where > > > > > > > the bit32 and bit33 are encoded in the bit9 and bit4 of the PTE > > > > > > > respectively. Meanwhile the iova still is 32bits. > > > > > > > > > > > > > > Regarding whether the pagetable address could be over 4GB, the mt8183 > > > > > > > support it while the previous mt8173 don't, thus keep it as is. > > > > > > > > > > > > > > Signed-off-by: Yong Wu > > > > > > > --- > > > > > > > drivers/iommu/io-pgtable-arm-v7s.c | 32 +++++++++++++++++++++++++------- > > > > > > > include/linux/io-pgtable.h | 7 +++---- > > > > > > > 2 files changed, 28 insertions(+), 11 deletions(-) > > > > > > > > > > > > [...] > > > > > > > > > > > > > @@ -731,7 +747,9 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > > > > > > > { > > > > > > > struct arm_v7s_io_pgtable *data; > > > > > > > - if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS) > > > > > > > + if (cfg->ias > ARM_V7S_ADDR_BITS || > > > > > > > + (cfg->oas > ARM_V7S_ADDR_BITS && > > > > > > > + !(cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT))) > > > > > > > > > > > > Please can you instead change arm_v7s_alloc_pgtable() so that it allows an > > > > > > ias of up to 34 when the IO_PGTABLE_QUIRK_ARM_MTK_EXT is set? > > > > > > > > > > Here I only simply skip the oas checking for our case. then which way do > > > > > your prefer? something like you commented before:? > > > > > > > > > > > > > > > if (cfg->ias > ARM_V7S_ADDR_BITS) > > > > > return NULL; > > > > > > > > > > if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT) { > > > > > if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) > > > > > cfg->oas = min(cfg->oas, ARM_V7S_ADDR_BITS); > > > > > else if (cfg->oas > 34) > > > > > return NULL; > > > > > } else if (cfg->oas > ARM_V7S_ADDR_BITS) { > > > > > return NULL; > > > > > } > > > > > > > > All it should take is something like: > > > > > > > > if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT) > > > > max_oas = 34; > > > > else > > > > max_oas = 32; > > > > if (cfg->oas > max_oas) > > > > return NULL; > > > > > > > > or even just: > > > > > > > > if (cfg->oas > 32 || > > > > (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT && cfg->oas > 34)) > > > > return NULL; > > > > > > > > (and if we prefer the latter style, perhaps we could introduce some kind of > > > > "is_mtk_4gb()" helper to save on verbosity) > > > > > > I wondered the same thing, but another place we'd want the check is in > > > iopte_to_paddr() which probably needs the PHYS_ADDR_T check to avoid GCC > > > warnings, although I didn't try it. > > > > I'm pretty sure I confirmed that "paddr |= BIT_ULL(32)" doesn't warn when > > phys_addt_t is 32-bit - it's well-defined unsigned integer truncation after > > all, and if GCC starts warning about all the valid no-op code it optimises > > away then it's going to run up against IS_ENABLED() first and foremost ;) > > You're quite right, although we live in a world where GCC shouts at us about > missing comments in switch statements so I think my worry was justified! > > > > So if we did: > > > > > > static bool cfg_mtk_ext_enabled(struct io_pgtable_cfg *cfg) > > > { > > > return IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && > > > cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT; > > > } > > > > > > Then I suppose we could do this in _alloc(): > > > > > > if (cfg->oas > cfg_mtk_ext_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS) > > > return NULL; > > ^^ Apparantly, I left the bracketting here as an exercise to the reader. > > > > > > > and then this in iopte_to_paddr(): > > > > > > [...] > > > > > > paddr = pte & mask; > > > if (!cfg_mtk_ext_enabled(cfg)) > > > return paddr; > > > > > > if (pte & ARM_V7S_ATTR_MTK_PA_BIT32) > > > paddr |= ... > > > > > > [...] > > > > > > What do you reckon? > > > > Yeah, that's the general shape of things I was picturing - I'm not that > > fussed about the PHYS_ADDR_T_64BIT thing, especially if it's wrapped up in > > just one place, so if you do want to keep it as belt-and-braces I'll just > > consider it a slight code size optimisation for 32-bit builds. > > Ok, great. Yong Wu -- are you ok respinning with the above + missing > brackets? Of course I can. NearlyAll the interface in this file is prefixed with "arm_v7s_", so does the new interface also need it?, like arm_v7s_is_mtk_enabled. And keep the iopte_to_paddr and paddr_to_iopte symmetrical. Then the final patch would looks like below, is it ok? +static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg) +{ + return IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && + (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT); +} + static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl, struct io_pgtable_cfg *cfg) { - return paddr & ARM_V7S_LVL_MASK(lvl); + arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl); + + if (!arm_v7s_is_mtk_enabled(cfg)) + return pte; + + if (paddr & BIT_ULL(32)) + pte |= ARM_V7S_ATTR_MTK_PA_BIT32; + if (paddr & BIT_ULL(33)) + pte |= ARM_V7S_ATTR_MTK_PA_BIT33; + return pte; } static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, struct io_pgtable_cfg *cfg) { arm_v7s_iopte mask; + phys_addr_t paddr; if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) mask = ARM_V7S_TABLE_MASK; @@ -194,7 +212,15 @@ static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, else mask = ARM_V7S_LVL_MASK(lvl); - return pte & mask; + paddr = pte & mask; + if (!arm_v7s_is_mtk_enabled(cfg)) + return paddr; + + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32) + paddr |= BIT_ULL(32); + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33) + paddr |= BIT_ULL(33); + return paddr; } static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl, @@ -315,9 +341,6 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl, if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)) pte |= ARM_V7S_ATTR_NS_SECTION; - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT) - pte |= ARM_V7S_ATTR_MTK_4GB; - return pte; } @@ -731,7 +754,10 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, { struct arm_v7s_io_pgtable *data; - if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS) + if (cfg->ias > ARM_V7S_ADDR_BITS) + return NULL; + + if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) return NULL; > > Will _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 063A6C41514 for ; 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bh=XoZF0RlYoSQwX3VRIhphyNoBapkNb88/aNbxvdZz8pY=; b=Mf/65Fhoso/+Sb x7tqwMz5t6aUJwiul/NgoNs+aiv8M2obXq30R6HCELHiJjeESPTT2U4oIa03Ua7TTFmnZmI4qhDVh UgT9eC4tTw5MddSSE8xDE8YuEtYAayaRwD36lnjbzV454Z2cPxL2dbT5xVlcaW+hMZR71UZmeKJFE 8NpTvKV8CCmzkmU6OZlgt9yhx6IbZrQFcI53swvjaYiFhPzGPZmK/zj0uzJJx+KmMuI4ztGYYsLXp dybfJnaZQvX+RyVnYRFTAGk3cnARkvGF+TBtuHyw6y6oI4ovsqLeGJZlaboQpvRtc3ZZlQLP1VfQw hKRG+wXdCw/tbMYuGPiw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1i0lqd-0006xn-Pj; Thu, 22 Aug 2019 12:05:47 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1i0lqa-0006xR-HH; Thu, 22 Aug 2019 12:05:46 +0000 X-UUID: 870cff0c27f247458ea5116ed24f79cd-20190822 X-UUID: 870cff0c27f247458ea5116ed24f79cd-20190822 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 2002956516; Thu, 22 Aug 2019 04:05:33 -0800 Received: from MTKMBS32DR.mediatek.inc (172.27.6.104) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 05:05:31 -0700 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS32DR.mediatek.inc (172.27.6.104) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 20:05:29 +0800 Received: from [10.17.3.153] (172.27.4.253) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 20:05:28 +0800 Message-ID: <1566475533.11621.18.camel@mhfsdcap03> Subject: Re: [PATCH v10 09/23] iommu/io-pgtable-arm-v7s: Extend to support PA[33:32] for MediaTek From: Yong Wu To: Will Deacon , Robin Murphy Date: Thu, 22 Aug 2019 20:05:33 +0800 In-Reply-To: <20190822112836.efodtwu3souq3uwa@willie-the-truck> References: <1566395606-7975-1-git-send-email-yong.wu@mediatek.com> <1566395606-7975-10-git-send-email-yong.wu@mediatek.com> <20190821152448.qmoqjh5zznfpdi6n@willie-the-truck> <1566464186.11621.7.camel@mhfsdcap03> <10d5122d-3375-161b-9356-2ddfc1c835bd@arm.com> <20190822101749.3kwzd5lb7zinsord@willie-the-truck> <20190822112836.efodtwu3souq3uwa@willie-the-truck> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: F20067B59D18F1DAE1600790624773E385B1897B1B418F35B0B8F7CF6BE8012E2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190822_050544_583196_8ADDBA28 X-CRM114-Status: GOOD ( 32.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , cui.zhang@mediatek.com, srv_heupstream@mediatek.com, Tomasz Figa , Joerg Roedel , linux-kernel@vger.kernel.org, Evan Green , chao.hao@mediatek.com, iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Matthias Kaehlcke , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Thanks very much for viewing this so quickly. On Thu, 2019-08-22 at 12:28 +0100, Will Deacon wrote: > On Thu, Aug 22, 2019 at 11:57:11AM +0100, Robin Murphy wrote: > > On 2019-08-22 11:17 am, Will Deacon wrote: > > > On Thu, Aug 22, 2019 at 11:08:58AM +0100, Robin Murphy wrote: > > > > On 2019-08-22 9:56 am, Yong Wu wrote: > > > > > On Wed, 2019-08-21 at 16:24 +0100, Will Deacon wrote: > > > > > > On Wed, Aug 21, 2019 at 09:53:12PM +0800, Yong Wu wrote: > > > > > > > MediaTek extend the arm v7s descriptor to support up to 34 bits PA where > > > > > > > the bit32 and bit33 are encoded in the bit9 and bit4 of the PTE > > > > > > > respectively. Meanwhile the iova still is 32bits. > > > > > > > > > > > > > > Regarding whether the pagetable address could be over 4GB, the mt8183 > > > > > > > support it while the previous mt8173 don't, thus keep it as is. > > > > > > > > > > > > > > Signed-off-by: Yong Wu > > > > > > > --- > > > > > > > drivers/iommu/io-pgtable-arm-v7s.c | 32 +++++++++++++++++++++++++------- > > > > > > > include/linux/io-pgtable.h | 7 +++---- > > > > > > > 2 files changed, 28 insertions(+), 11 deletions(-) > > > > > > > > > > > > [...] > > > > > > > > > > > > > @@ -731,7 +747,9 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > > > > > > > { > > > > > > > struct arm_v7s_io_pgtable *data; > > > > > > > - if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS) > > > > > > > + if (cfg->ias > ARM_V7S_ADDR_BITS || > > > > > > > + (cfg->oas > ARM_V7S_ADDR_BITS && > > > > > > > + !(cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT))) > > > > > > > > > > > > Please can you instead change arm_v7s_alloc_pgtable() so that it allows an > > > > > > ias of up to 34 when the IO_PGTABLE_QUIRK_ARM_MTK_EXT is set? > > > > > > > > > > Here I only simply skip the oas checking for our case. then which way do > > > > > your prefer? something like you commented before:? > > > > > > > > > > > > > > > if (cfg->ias > ARM_V7S_ADDR_BITS) > > > > > return NULL; > > > > > > > > > > if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT) { > > > > > if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) > > > > > cfg->oas = min(cfg->oas, ARM_V7S_ADDR_BITS); > > > > > else if (cfg->oas > 34) > > > > > return NULL; > > > > > } else if (cfg->oas > ARM_V7S_ADDR_BITS) { > > > > > return NULL; > > > > > } > > > > > > > > All it should take is something like: > > > > > > > > if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT) > > > > max_oas = 34; > > > > else > > > > max_oas = 32; > > > > if (cfg->oas > max_oas) > > > > return NULL; > > > > > > > > or even just: > > > > > > > > if (cfg->oas > 32 || > > > > (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT && cfg->oas > 34)) > > > > return NULL; > > > > > > > > (and if we prefer the latter style, perhaps we could introduce some kind of > > > > "is_mtk_4gb()" helper to save on verbosity) > > > > > > I wondered the same thing, but another place we'd want the check is in > > > iopte_to_paddr() which probably needs the PHYS_ADDR_T check to avoid GCC > > > warnings, although I didn't try it. > > > > I'm pretty sure I confirmed that "paddr |= BIT_ULL(32)" doesn't warn when > > phys_addt_t is 32-bit - it's well-defined unsigned integer truncation after > > all, and if GCC starts warning about all the valid no-op code it optimises > > away then it's going to run up against IS_ENABLED() first and foremost ;) > > You're quite right, although we live in a world where GCC shouts at us about > missing comments in switch statements so I think my worry was justified! > > > > So if we did: > > > > > > static bool cfg_mtk_ext_enabled(struct io_pgtable_cfg *cfg) > > > { > > > return IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && > > > cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT; > > > } > > > > > > Then I suppose we could do this in _alloc(): > > > > > > if (cfg->oas > cfg_mtk_ext_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS) > > > return NULL; > > ^^ Apparantly, I left the bracketting here as an exercise to the reader. > > > > > > > and then this in iopte_to_paddr(): > > > > > > [...] > > > > > > paddr = pte & mask; > > > if (!cfg_mtk_ext_enabled(cfg)) > > > return paddr; > > > > > > if (pte & ARM_V7S_ATTR_MTK_PA_BIT32) > > > paddr |= ... > > > > > > [...] > > > > > > What do you reckon? > > > > Yeah, that's the general shape of things I was picturing - I'm not that > > fussed about the PHYS_ADDR_T_64BIT thing, especially if it's wrapped up in > > just one place, so if you do want to keep it as belt-and-braces I'll just > > consider it a slight code size optimisation for 32-bit builds. > > Ok, great. Yong Wu -- are you ok respinning with the above + missing > brackets? Of course I can. NearlyAll the interface in this file is prefixed with "arm_v7s_", so does the new interface also need it?, like arm_v7s_is_mtk_enabled. And keep the iopte_to_paddr and paddr_to_iopte symmetrical. Then the final patch would looks like below, is it ok? +static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg) +{ + return IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && + (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT); +} + static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl, struct io_pgtable_cfg *cfg) { - return paddr & ARM_V7S_LVL_MASK(lvl); + arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl); + + if (!arm_v7s_is_mtk_enabled(cfg)) + return pte; + + if (paddr & BIT_ULL(32)) + pte |= ARM_V7S_ATTR_MTK_PA_BIT32; + if (paddr & BIT_ULL(33)) + pte |= ARM_V7S_ATTR_MTK_PA_BIT33; + return pte; } static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, struct io_pgtable_cfg *cfg) { arm_v7s_iopte mask; + phys_addr_t paddr; if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) mask = ARM_V7S_TABLE_MASK; @@ -194,7 +212,15 @@ static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, else mask = ARM_V7S_LVL_MASK(lvl); - return pte & mask; + paddr = pte & mask; + if (!arm_v7s_is_mtk_enabled(cfg)) + return paddr; + + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32) + paddr |= BIT_ULL(32); + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33) + paddr |= BIT_ULL(33); + return paddr; } static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl, @@ -315,9 +341,6 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl, if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)) pte |= ARM_V7S_ATTR_NS_SECTION; - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT) - pte |= ARM_V7S_ATTR_MTK_4GB; - return pte; } @@ -731,7 +754,10 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, { struct arm_v7s_io_pgtable *data; - if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS) + if (cfg->ias > ARM_V7S_ADDR_BITS) + return NULL; + + if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) return NULL; > > Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel