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From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PATCH v2 06/30] target/mips: Clean up handling of CP0 register 5
Date: Wed, 28 Aug 2019 18:26:30 +0200	[thread overview]
Message-ID: <1567009614-12438-7-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1567009614-12438-1-git-send-email-aleksandar.markovic@rt-rk.com>

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Clean up handling of CP0 register 5.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/cpu.h       |  6 +++++
 target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
 2 files changed, 38 insertions(+), 32 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 04d4b09..248f7df 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -315,6 +315,12 @@ typedef struct mips_def_t mips_def_t;
 /* CP0 Register 05 */
 #define CP0_REG05__PAGEMASK        0
 #define CP0_REG05__PAGEGRAIN       1
+#define CP0_REG05__SEGCTL0         2
+#define CP0_REG05__SEGCTL1         3
+#define CP0_REG05__SEGCTL2         4
+#define CP0_REG05__PWBASE          5
+#define CP0_REG05__PWFIELD         6
+#define CP0_REG05__PWSIZE          7
 /* CP0 Register 06 */
 #define CP0_REG06__WIRED           0
 /* CP0 Register 07 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 677a2d0..4395345 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7043,44 +7043,44 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_05:
         switch (sel) {
-        case 0:
+        case CP0_REG05__PAGEMASK:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
             register_name = "PageMask";
             break;
-        case 1:
+        case CP0_REG05__PAGEGRAIN:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
             register_name = "PageGrain";
             break;
-        case 2:
+        case CP0_REG05__SEGCTL0:
             CP0_CHECK(ctx->sc);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
             tcg_gen_ext32s_tl(arg, arg);
             register_name = "SegCtl0";
             break;
-        case 3:
+        case CP0_REG05__SEGCTL1:
             CP0_CHECK(ctx->sc);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
             tcg_gen_ext32s_tl(arg, arg);
             register_name = "SegCtl1";
             break;
-        case 4:
+        case CP0_REG05__SEGCTL2:
             CP0_CHECK(ctx->sc);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
             tcg_gen_ext32s_tl(arg, arg);
             register_name = "SegCtl2";
             break;
-        case 5:
+        case CP0_REG05__PWBASE:
             check_pw(ctx);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
             register_name = "PWBase";
             break;
-        case 6:
+        case CP0_REG05__PWFIELD:
             check_pw(ctx);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
             register_name = "PWField";
             break;
-        case 7:
+        case CP0_REG05__PWSIZE:
             check_pw(ctx);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
             register_name = "PWSize";
@@ -7785,42 +7785,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_05:
         switch (sel) {
-        case 0:
+        case CP0_REG05__PAGEMASK:
             gen_helper_mtc0_pagemask(cpu_env, arg);
             register_name = "PageMask";
             break;
-        case 1:
+        case CP0_REG05__PAGEGRAIN:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_pagegrain(cpu_env, arg);
             register_name = "PageGrain";
             ctx->base.is_jmp = DISAS_STOP;
             break;
-        case 2:
+        case CP0_REG05__SEGCTL0:
             CP0_CHECK(ctx->sc);
             gen_helper_mtc0_segctl0(cpu_env, arg);
             register_name = "SegCtl0";
             break;
-        case 3:
+        case CP0_REG05__SEGCTL1:
             CP0_CHECK(ctx->sc);
             gen_helper_mtc0_segctl1(cpu_env, arg);
             register_name = "SegCtl1";
             break;
-        case 4:
+        case CP0_REG05__SEGCTL2:
             CP0_CHECK(ctx->sc);
             gen_helper_mtc0_segctl2(cpu_env, arg);
             register_name = "SegCtl2";
             break;
-        case 5:
+        case CP0_REG05__PWBASE:
             check_pw(ctx);
             gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
             register_name = "PWBase";
             break;
-        case 6:
+        case CP0_REG05__PWFIELD:
             check_pw(ctx);
             gen_helper_mtc0_pwfield(cpu_env, arg);
             register_name = "PWField";
             break;
-        case 7:
+        case CP0_REG05__PWSIZE:
             check_pw(ctx);
             gen_helper_mtc0_pwsize(cpu_env, arg);
             register_name = "PWSize";
@@ -8537,41 +8537,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_05:
         switch (sel) {
-        case 0:
+        case CP0_REG05__PAGEMASK:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
             register_name = "PageMask";
             break;
-        case 1:
+        case CP0_REG05__PAGEGRAIN:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
             register_name = "PageGrain";
             break;
-        case 2:
+        case CP0_REG05__SEGCTL0:
             CP0_CHECK(ctx->sc);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
             register_name = "SegCtl0";
             break;
-        case 3:
+        case CP0_REG05__SEGCTL1:
             CP0_CHECK(ctx->sc);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
             register_name = "SegCtl1";
             break;
-        case 4:
+        case CP0_REG05__SEGCTL2:
             CP0_CHECK(ctx->sc);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
             register_name = "SegCtl2";
             break;
-        case 5:
+        case CP0_REG05__PWBASE:
             check_pw(ctx);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
             register_name = "PWBase";
             break;
-        case 6:
+        case CP0_REG05__PWFIELD:
             check_pw(ctx);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
             register_name = "PWField";
             break;
-        case 7:
+        case CP0_REG05__PWSIZE:
             check_pw(ctx);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
             register_name = "PWSize";
@@ -9259,41 +9259,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_05:
         switch (sel) {
-        case 0:
+        case CP0_REG05__PAGEMASK:
             gen_helper_mtc0_pagemask(cpu_env, arg);
             register_name = "PageMask";
             break;
-        case 1:
+        case CP0_REG05__PAGEGRAIN:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_pagegrain(cpu_env, arg);
             register_name = "PageGrain";
             break;
-        case 2:
+        case CP0_REG05__SEGCTL0:
             CP0_CHECK(ctx->sc);
             gen_helper_mtc0_segctl0(cpu_env, arg);
             register_name = "SegCtl0";
             break;
-        case 3:
+        case CP0_REG05__SEGCTL1:
             CP0_CHECK(ctx->sc);
             gen_helper_mtc0_segctl1(cpu_env, arg);
             register_name = "SegCtl1";
             break;
-        case 4:
+        case CP0_REG05__SEGCTL2:
             CP0_CHECK(ctx->sc);
             gen_helper_mtc0_segctl2(cpu_env, arg);
             register_name = "SegCtl2";
             break;
-        case 5:
+        case CP0_REG05__PWBASE:
             check_pw(ctx);
             tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
             register_name = "PWBase";
             break;
-        case 6:
+        case CP0_REG05__PWFIELD:
             check_pw(ctx);
             gen_helper_mtc0_pwfield(cpu_env, arg);
             register_name = "PWField";
             break;
-        case 7:
+        case CP0_REG05__PWSIZE:
             check_pw(ctx);
             gen_helper_mtc0_pwsize(cpu_env, arg);
             register_name = "PWSize";
-- 
2.7.4



  parent reply	other threads:[~2019-08-28 16:33 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-28 16:26 [Qemu-devel] [PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 01/30] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 02/30] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 03/30] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 04/30] target/mips: Clean up handling of CP0 register 3 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 05/30] target/mips: Clean up handling of CP0 register 4 Aleksandar Markovic
2019-08-28 16:26 ` Aleksandar Markovic [this message]
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 07/30] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 08/30] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 09/30] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 10/30] target/mips: Clean up handling of CP0 register 9 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 11/30] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 12/30] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 13/30] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 14/30] target/mips: Clean up handling of CP0 register 13 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 15/30] target/mips: Clean up handling of CP0 register 14 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 16/30] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 17/30] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 18/30] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 19/30] target/mips: Clean up handling of CP0 register 18 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 20/30] target/mips: Clean up handling of CP0 register 19 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 21/30] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 22/30] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 23/30] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 24/30] target/mips: Clean up handling of CP0 register 25 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 25/30] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 26/30] target/mips: Clean up handling of CP0 register 27 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 27/30] target/mips: Clean up handling of CP0 register 28 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 28/30] target/mips: Clean up handling of CP0 register 29 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 29/30] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
2019-08-28 16:26 ` [Qemu-devel] [PATCH v2 30/30] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic
2019-08-28 16:46 ` [Qemu-devel] [EXTERNAL][PATCH v2 00/30] Clean up handling of configuration register CP0 Aleksandar Rikalo

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