From mboxrd@z Thu Jan 1 00:00:00 1970 From: fabrizio.castro@bp.renesas.com (Fabrizio Castro) Date: Mon, 2 Sep 2019 09:48:22 +0100 Subject: [cip-dev] [PATCH resend] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string Message-ID: <1567414102-4869-1-git-send-email-fabrizio.castro@bp.renesas.com> To: cip-dev@lists.cip-project.org List-Id: cip-dev.lists.cip-project.org From: Rob Herring commit 31af04cd60d3162a58213363fd740a2b0cf0a08e upstream. The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek Cc: Mark Rutland Cc: Will Deacon Acked-by: Antoine Tenart Acked-by: Nishanth Menon Acked-by: Maxime Ripard Acked-by: Manivannan Sadhasivam Acked-by: Chanho Min Acked-by: Krzysztof Kozlowski Acked-by: Masahiro Yamada Acked-by: Gregory CLEMENT Acked-by: Thierry Reding Acked-by: Heiko Stuebner Acked-by: Simon Horman Acked-by: Tero Kristo Acked-by: Wei Xu Acked-by: Liviu Dudau Acked-by: Matthias Brugger Acked-by: Michal Simek Acked-by: Scott Branden Acked-by: Kevin Hilman Acked-by: Chunyan Zhang Acked-by: Robert Richter Acked-by: Jisheng Zhang Acked-by: Dinh Nguyen Signed-off-by: Rob Herring Signed-off-by: Arnd Bergmann [fab: dropped changes not related to r8a774a1.dtsi] Signed-off-by: Fabrizio Castro --- I have put the CIP maintainers in CC, to try and troubleshoot where the mysterious spaces are coming from, please bear with me... arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 1969649..a77de9e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -61,7 +61,7 @@ #size-cells = <0>; a57_0: cpu at 0 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x0>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; @@ -71,7 +71,7 @@ }; a57_1: cpu at 1 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x1>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; @@ -81,7 +81,7 @@ }; a53_0: cpu at 100 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x100>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; @@ -91,7 +91,7 @@ }; a53_1: cpu at 101 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x101>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; @@ -101,7 +101,7 @@ }; a53_2: cpu at 102 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x102>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; @@ -111,7 +111,7 @@ }; a53_3: cpu at 103 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x103>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; -- 2.7.4