From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFA4ACA9EA0 for ; Fri, 18 Oct 2019 17:27:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A11ED21D7C for ; Fri, 18 Oct 2019 17:27:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2634460AbfJRR10 (ORCPT ); Fri, 18 Oct 2019 13:27:26 -0400 Received: from [217.140.110.172] ([217.140.110.172]:47180 "EHLO foss.arm.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S2502098AbfJRR1Z (ORCPT ); Fri, 18 Oct 2019 13:27:25 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 712401476; Fri, 18 Oct 2019 10:27:02 -0700 (PDT) Received: from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A5F203F718; Fri, 18 Oct 2019 10:26:59 -0700 (PDT) From: Dave Martin To: linux-kernel@vger.kernel.org Cc: Andrew Jones , Arnd Bergmann , Catalin Marinas , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Kees Cook , =?UTF-8?q?Kristina=20Mart=C5=A1enko?= , Marc Zyngier , Mark Brown , Paul Elliott , Peter Zijlstra , Richard Henderson , Sudakshina Das , Szabolcs Nagy , Thomas Gleixner , Will Deacon , Yu-cheng Yu , Amit Kachhap , Vincenzo Frascino , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 09/12] arm64: traps: Fix inconsistent faulting instruction skipping Date: Fri, 18 Oct 2019 18:25:42 +0100 Message-Id: <1571419545-20401-10-git-send-email-Dave.Martin@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1571419545-20401-1-git-send-email-Dave.Martin@arm.com> References: <1571419545-20401-1-git-send-email-Dave.Martin@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Correct skipping of an instruction on AArch32 works a bit differently from AArch64, mainly due to the different CPSR/PSTATE semantics. There have been various attempts to get this right. Currenty arm64_skip_faulting_instruction() mostly does the right thing, but does not advance the IT state machine for the AArch32 case. arm64_compat_skip_faulting_instruction() handles the IT state machine but is local to traps.c, and porting other code to use it will make a mess since there are some call sites that apply for both the compat and native cases. Since manual instruction skipping implies a trap, it's a relatively slow path. So, make arm64_skip_faulting_instruction() handle both compat and native, and get rid of the arm64_compat_skip_faulting_instruction() special case. Fixes: 32a3e635fb0e ("arm64: compat: Add CNTFRQ trap handler") Fixes: 1f1c014035a8 ("arm64: compat: Add condition code checks and IT advance") Fixes: 6436beeee572 ("arm64: Fix single stepping in kernel traps") Fixes: bd35a4adc413 ("arm64: Port SWP/SWPB emulation support from arm") Signed-off-by: Dave Martin --- **NOTE** Despite discussions on the v2 series to the effect that the prior behaviour is not broken, I'm now not so sure: Taking another look, I now can't track down for example where SWP in an IT block is specified to be UNPREDICTABLE. I only see e.g., ARM DDI 0487E.a Section 1.8.2 ("F1.8.2 Partial deprecation of IT"), which only deprecates the affected instructions. The legacy AArch32 SWP{B} insn is obsoleted by ARMv8, but the whole point of the armv8_deprecated stuff is to provide some backwards compatiblity with v7. So, this looks like it needs a closer look. I'll leave the Fixes tags for now, so that the archaeology doesn't need to be repeated if we conclude that this patch really is a fix. --- arch/arm64/kernel/traps.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 15e3c4f..44c91d4 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -268,6 +268,8 @@ void arm64_notify_die(const char *str, struct pt_regs *regs, } } +static void advance_itstate(struct pt_regs *regs); + void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) { regs->pc += size; @@ -278,6 +280,9 @@ void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) */ if (user_mode(regs)) user_fastforward_single_step(current); + + if (regs->pstate & PSR_MODE32_BIT) + advance_itstate(regs); } static LIST_HEAD(undef_hook); @@ -629,19 +634,12 @@ static void advance_itstate(struct pt_regs *regs) compat_set_it_state(regs, it); } -static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs, - unsigned int sz) -{ - advance_itstate(regs); - arm64_skip_faulting_instruction(regs, sz); -} - static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) { int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; pt_regs_write_reg(regs, reg, arch_timer_get_rate()); - arm64_compat_skip_faulting_instruction(regs, 4); + arm64_skip_faulting_instruction(regs, 4); } static const struct sys64_hook cp15_32_hooks[] = { @@ -661,7 +659,7 @@ static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs) pt_regs_write_reg(regs, rt, lower_32_bits(val)); pt_regs_write_reg(regs, rt2, upper_32_bits(val)); - arm64_compat_skip_faulting_instruction(regs, 4); + arm64_skip_faulting_instruction(regs, 4); } static const struct sys64_hook cp15_64_hooks[] = { @@ -682,7 +680,7 @@ asmlinkage void __exception do_cp15instr(unsigned int esr, struct pt_regs *regs) * There is no T16 variant of a CP access, so we * always advance PC by 4 bytes. */ - arm64_compat_skip_faulting_instruction(regs, 4); + arm64_skip_faulting_instruction(regs, 4); return; } -- 2.1.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Martin Subject: [PATCH v3 09/12] arm64: traps: Fix inconsistent faulting instruction skipping Date: Fri, 18 Oct 2019 18:25:42 +0100 Message-ID: <1571419545-20401-10-git-send-email-Dave.Martin@arm.com> References: <1571419545-20401-1-git-send-email-Dave.Martin@arm.com> Return-path: In-Reply-To: <1571419545-20401-1-git-send-email-Dave.Martin@arm.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-kernel@vger.kernel.org Cc: Andrew Jones , Arnd Bergmann , Catalin Marinas , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Kees Cook , =?UTF-8?q?Kristina=20Mart=C5=A1enko?= , Marc Zyngier , Mark Brown , Paul Elliott , Peter Zijlstra , Richard Henderson , Sudakshina Das , Szabolcs Nagy , Thomas Gleixner , Will Deacon , Yu-cheng Yu , Amit Kachhap , V List-Id: linux-arch.vger.kernel.org Correct skipping of an instruction on AArch32 works a bit differently from AArch64, mainly due to the different CPSR/PSTATE semantics. There have been various attempts to get this right. Currenty arm64_skip_faulting_instruction() mostly does the right thing, but does not advance the IT state machine for the AArch32 case. arm64_compat_skip_faulting_instruction() handles the IT state machine but is local to traps.c, and porting other code to use it will make a mess since there are some call sites that apply for both the compat and native cases. Since manual instruction skipping implies a trap, it's a relatively slow path. So, make arm64_skip_faulting_instruction() handle both compat and native, and get rid of the arm64_compat_skip_faulting_instruction() special case. Fixes: 32a3e635fb0e ("arm64: compat: Add CNTFRQ trap handler") Fixes: 1f1c014035a8 ("arm64: compat: Add condition code checks and IT advance") Fixes: 6436beeee572 ("arm64: Fix single stepping in kernel traps") Fixes: bd35a4adc413 ("arm64: Port SWP/SWPB emulation support from arm") Signed-off-by: Dave Martin --- **NOTE** Despite discussions on the v2 series to the effect that the prior behaviour is not broken, I'm now not so sure: Taking another look, I now can't track down for example where SWP in an IT block is specified to be UNPREDICTABLE. I only see e.g., ARM DDI 0487E.a Section 1.8.2 ("F1.8.2 Partial deprecation of IT"), which only deprecates the affected instructions. The legacy AArch32 SWP{B} insn is obsoleted by ARMv8, but the whole point of the armv8_deprecated stuff is to provide some backwards compatiblity with v7. So, this looks like it needs a closer look. I'll leave the Fixes tags for now, so that the archaeology doesn't need to be repeated if we conclude that this patch really is a fix. --- arch/arm64/kernel/traps.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 15e3c4f..44c91d4 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -268,6 +268,8 @@ void arm64_notify_die(const char *str, struct pt_regs *regs, } } +static void advance_itstate(struct pt_regs *regs); + void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) { regs->pc += size; @@ -278,6 +280,9 @@ void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) */ if (user_mode(regs)) user_fastforward_single_step(current); + + if (regs->pstate & PSR_MODE32_BIT) + advance_itstate(regs); } static LIST_HEAD(undef_hook); @@ -629,19 +634,12 @@ static void advance_itstate(struct pt_regs *regs) compat_set_it_state(regs, it); } -static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs, - unsigned int sz) -{ - advance_itstate(regs); - arm64_skip_faulting_instruction(regs, sz); -} - static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) { int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; pt_regs_write_reg(regs, reg, arch_timer_get_rate()); - arm64_compat_skip_faulting_instruction(regs, 4); + arm64_skip_faulting_instruction(regs, 4); } static const struct sys64_hook cp15_32_hooks[] = { @@ -661,7 +659,7 @@ static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs) pt_regs_write_reg(regs, rt, lower_32_bits(val)); pt_regs_write_reg(regs, rt2, upper_32_bits(val)); - arm64_compat_skip_faulting_instruction(regs, 4); + arm64_skip_faulting_instruction(regs, 4); } static const struct sys64_hook cp15_64_hooks[] = { @@ -682,7 +680,7 @@ asmlinkage void __exception do_cp15instr(unsigned int esr, struct pt_regs *regs) * There is no T16 variant of a CP access, so we * always advance PC by 4 bytes. */ - arm64_compat_skip_faulting_instruction(regs, 4); + arm64_skip_faulting_instruction(regs, 4); return; } -- 2.1.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 999B0CA9EA0 for ; Fri, 18 Oct 2019 17:30:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6C81621D7C for ; Fri, 18 Oct 2019 17:30:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="E9AeQABF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6C81621D7C Authentication-Results: mail.kernel.org; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iLW51-0000VZ-Mr; Fri, 18 Oct 2019 17:30:23 +0000 Received: from [217.140.110.172] (helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iLW1x-0004sG-Bj for linux-arm-kernel@lists.infradead.org; Fri, 18 Oct 2019 17:27:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 712401476; Fri, 18 Oct 2019 10:27:02 -0700 (PDT) Received: from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A5F203F718; Fri, 18 Oct 2019 10:26:59 -0700 (PDT) From: Dave Martin To: linux-kernel@vger.kernel.org Subject: [PATCH v3 09/12] arm64: traps: Fix inconsistent faulting instruction skipping Date: Fri, 18 Oct 2019 18:25:42 +0100 Message-Id: <1571419545-20401-10-git-send-email-Dave.Martin@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1571419545-20401-1-git-send-email-Dave.Martin@arm.com> References: <1571419545-20401-1-git-send-email-Dave.Martin@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191018_102713_599545_53CD6E9D X-CRM114-Status: GOOD ( 16.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Elliott , Peter Zijlstra , Catalin Marinas , Yu-cheng Yu , Amit Kachhap , Vincenzo Frascino , Will Deacon , linux-arch@vger.kernel.org, Marc Zyngier , Eugene Syromiatnikov , Szabolcs Nagy , "H.J. Lu" , Andrew Jones , Kees Cook , Arnd Bergmann , Jann Horn , Richard Henderson , =?UTF-8?q?Kristina=20Mart=C5=A1enko?= , Mark Brown , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Florian Weimer , Sudakshina Das MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Correct skipping of an instruction on AArch32 works a bit differently from AArch64, mainly due to the different CPSR/PSTATE semantics. There have been various attempts to get this right. Currenty arm64_skip_faulting_instruction() mostly does the right thing, but does not advance the IT state machine for the AArch32 case. arm64_compat_skip_faulting_instruction() handles the IT state machine but is local to traps.c, and porting other code to use it will make a mess since there are some call sites that apply for both the compat and native cases. Since manual instruction skipping implies a trap, it's a relatively slow path. So, make arm64_skip_faulting_instruction() handle both compat and native, and get rid of the arm64_compat_skip_faulting_instruction() special case. Fixes: 32a3e635fb0e ("arm64: compat: Add CNTFRQ trap handler") Fixes: 1f1c014035a8 ("arm64: compat: Add condition code checks and IT advance") Fixes: 6436beeee572 ("arm64: Fix single stepping in kernel traps") Fixes: bd35a4adc413 ("arm64: Port SWP/SWPB emulation support from arm") Signed-off-by: Dave Martin --- **NOTE** Despite discussions on the v2 series to the effect that the prior behaviour is not broken, I'm now not so sure: Taking another look, I now can't track down for example where SWP in an IT block is specified to be UNPREDICTABLE. I only see e.g., ARM DDI 0487E.a Section 1.8.2 ("F1.8.2 Partial deprecation of IT"), which only deprecates the affected instructions. The legacy AArch32 SWP{B} insn is obsoleted by ARMv8, but the whole point of the armv8_deprecated stuff is to provide some backwards compatiblity with v7. So, this looks like it needs a closer look. I'll leave the Fixes tags for now, so that the archaeology doesn't need to be repeated if we conclude that this patch really is a fix. --- arch/arm64/kernel/traps.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 15e3c4f..44c91d4 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -268,6 +268,8 @@ void arm64_notify_die(const char *str, struct pt_regs *regs, } } +static void advance_itstate(struct pt_regs *regs); + void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) { regs->pc += size; @@ -278,6 +280,9 @@ void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) */ if (user_mode(regs)) user_fastforward_single_step(current); + + if (regs->pstate & PSR_MODE32_BIT) + advance_itstate(regs); } static LIST_HEAD(undef_hook); @@ -629,19 +634,12 @@ static void advance_itstate(struct pt_regs *regs) compat_set_it_state(regs, it); } -static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs, - unsigned int sz) -{ - advance_itstate(regs); - arm64_skip_faulting_instruction(regs, sz); -} - static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) { int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; pt_regs_write_reg(regs, reg, arch_timer_get_rate()); - arm64_compat_skip_faulting_instruction(regs, 4); + arm64_skip_faulting_instruction(regs, 4); } static const struct sys64_hook cp15_32_hooks[] = { @@ -661,7 +659,7 @@ static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs) pt_regs_write_reg(regs, rt, lower_32_bits(val)); pt_regs_write_reg(regs, rt2, upper_32_bits(val)); - arm64_compat_skip_faulting_instruction(regs, 4); + arm64_skip_faulting_instruction(regs, 4); } static const struct sys64_hook cp15_64_hooks[] = { @@ -682,7 +680,7 @@ asmlinkage void __exception do_cp15instr(unsigned int esr, struct pt_regs *regs) * There is no T16 variant of a CP access, so we * always advance PC by 4 bytes. */ - arm64_compat_skip_faulting_instruction(regs, 4); + arm64_skip_faulting_instruction(regs, 4); return; } -- 2.1.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel