From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com
Subject: [PULL 04/11] target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>
Date: Thu, 24 Oct 2019 13:06:28 +0200 [thread overview]
Message-ID: <1571915195-4381-5-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1571915195-4381-1-git-send-email-aleksandar.markovic@rt-rk.com>
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1571826227-10583-5-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/helper.h | 11 +++-
target/mips/msa_helper.c | 163 ++++++++++++++++++++++++++++++++++++++++++-----
target/mips/translate.c | 38 +++++++++--
3 files changed, 187 insertions(+), 25 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index d615c83..cef4de6 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -877,6 +877,15 @@ DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32)
@@ -940,8 +949,6 @@ DEF_HELPER_5(msa_max_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_max_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index a2052ba..3eb0ab1 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1736,7 +1736,152 @@ void helper_msa_div_u_d(CPUMIPSState *env,
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Int Max Min group helpers here */
+static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
+ uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
+ return abs_arg1 > abs_arg2 ? arg1 : arg2;
+}
+
+void helper_msa_max_a_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_max_a_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_max_a_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_max_a_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_max_a_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_max_a_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_max_a_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_max_a_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_max_a_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_max_a_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_max_a_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_max_a_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_max_a_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_max_a_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_max_a_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_max_a_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_max_a_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_max_a_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_max_a_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_max_a_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_max_a_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_max_a_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_max_a_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_max_a_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_max_a_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_max_a_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_max_a_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_max_a_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_max_a_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_max_a_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_max_a_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_max_a_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_max_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_max_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
+ uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
+ return abs_arg1 < abs_arg2 ? arg1 : arg2;
+}
+
+void helper_msa_min_a_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_min_a_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_min_a_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_min_a_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_min_a_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_min_a_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_min_a_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_min_a_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_min_a_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_min_a_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_min_a_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_min_a_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_min_a_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_min_a_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_min_a_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_min_a_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_min_a_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_min_a_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_min_a_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_min_a_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_min_a_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_min_a_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_min_a_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_min_a_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_min_a_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_min_a_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_min_a_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_min_a_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_min_a_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_min_a_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_min_a_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_min_a_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_min_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_min_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
/*
@@ -2456,20 +2601,6 @@ MSA_TEROP_IMMU_DF(binsli, binsl)
MSA_TEROP_IMMU_DF(binsri, binsr)
#undef MSA_TEROP_IMMU_DF
-static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
- uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
- return abs_arg1 > abs_arg2 ? arg1 : arg2;
-}
-
-static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
- uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
- return abs_arg1 < abs_arg2 ? arg1 : arg2;
-}
-
static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
@@ -2773,8 +2904,6 @@ MSA_BINOP_DF(max_s)
MSA_BINOP_DF(max_u)
MSA_BINOP_DF(min_s)
MSA_BINOP_DF(min_u)
-MSA_BINOP_DF(max_a)
-MSA_BINOP_DF(min_a)
MSA_BINOP_DF(add_a)
MSA_BINOP_DF(adds_a)
MSA_BINOP_DF(adds_s)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5039716..8e26548 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28642,6 +28642,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_MAX_A_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_max_a_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_max_a_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_max_a_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_max_a_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MIN_A_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_min_a_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_min_a_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_min_a_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_min_a_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_MOD_S_df:
switch (df) {
case DF_BYTE:
@@ -28767,15 +28799,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_ILVR_df:
gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MAX_A_df:
- gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_ILVEV_df:
gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MIN_A_df:
- gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_ILVOD_df:
gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.7.4
next prev parent reply other threads:[~2019-10-24 12:40 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-24 11:06 [PULL 00/11] MIPS queue for October 24th, 2019 Aleksandar Markovic
2019-10-24 11:06 ` [PULL 01/11] target/mips: Clean up helper.c Aleksandar Markovic
2019-10-24 11:06 ` [PULL 02/11] target/mips: Clean up op_helper.c Aleksandar Markovic
2019-10-24 11:06 ` [PULL 03/11] MAINTAINERS: Update mail address of Aleksandar Rikalo Aleksandar Markovic
2019-10-24 11:06 ` Aleksandar Markovic [this message]
2019-10-24 11:06 ` [PULL 05/11] target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D> Aleksandar Markovic
2019-10-24 11:06 ` [PULL 06/11] target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D> Aleksandar Markovic
2019-10-24 11:06 ` [PULL 07/11] target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D> Aleksandar Markovic
2019-10-24 11:06 ` [PULL 08/11] target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D> Aleksandar Markovic
2019-10-24 11:06 ` [PULL 09/11] target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D> Aleksandar Markovic
2019-10-24 11:06 ` [PULL 10/11] target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D> Aleksandar Markovic
2019-10-24 11:06 ` [PULL 11/11] target/mips: Add support for emulation of CRC32 group of instructions Aleksandar Markovic
2019-10-25 4:43 ` [PULL 00/11] MIPS queue for October 24th, 2019 no-reply
2019-10-25 9:31 ` Peter Maydell
2019-10-25 16:43 ` [EXTERNAL]Re: " Aleksandar Markovic
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