From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 517A6C5DF60 for ; Thu, 7 Nov 2019 17:11:24 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id CAAE3206BA for ; Thu, 7 Nov 2019 17:11:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CAAE3206BA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mellanox.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 789F51BFD7; Thu, 7 Nov 2019 18:10:31 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 27D131BFB3 for ; Thu, 7 Nov 2019 18:10:23 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from viacheslavo@mellanox.com) with ESMTPS (AES256-SHA encrypted); 7 Nov 2019 19:10:18 +0200 Received: from pegasus11.mtr.labs.mlnx (pegasus11.mtr.labs.mlnx [10.210.16.104]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id xA7HAI98022109; Thu, 7 Nov 2019 19:10:18 +0200 Received: from pegasus11.mtr.labs.mlnx (localhost [127.0.0.1]) by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id xA7HAImC017949; Thu, 7 Nov 2019 17:10:18 GMT Received: (from viacheslavo@localhost) by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id xA7HAI8l017948; Thu, 7 Nov 2019 17:10:18 GMT X-Authentication-Warning: pegasus11.mtr.labs.mlnx: viacheslavo set sender to viacheslavo@mellanox.com using -f From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: matan@mellanox.com, rasland@mellanox.com, thomas@monjalon.net, orika@mellanox.com, Yongseok Koh Date: Thu, 7 Nov 2019 17:09:51 +0000 Message-Id: <1573146604-17803-7-git-send-email-viacheslavo@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1573146604-17803-1-git-send-email-viacheslavo@mellanox.com> References: <1572940915-29416-1-git-send-email-viacheslavo@mellanox.com> <1573146604-17803-1-git-send-email-viacheslavo@mellanox.com> Subject: [dpdk-dev] [PATCH v3 06/19] net/mlx5: update meta register matcher set X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Introduce the dedicated matcher register field setup routine. Update the code to use this unified one. Signed-off-by: Yongseok Koh Signed-off-by: Viacheslav Ovsiienko Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_flow_dv.c | 171 +++++++++++++++++++--------------------- 1 file changed, 82 insertions(+), 89 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index b7e8e0a..170726f 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -4905,6 +4905,78 @@ struct field_modify_info modify_tcp[] = { } /** + * Add metadata register item to matcher + * + * @param[in, out] matcher + * Flow matcher. + * @param[in, out] key + * Flow matcher value. + * @param[in] reg_type + * Type of device metadata register + * @param[in] value + * Register value + * @param[in] mask + * Register mask + */ +static void +flow_dv_match_meta_reg(void *matcher, void *key, + enum modify_reg reg_type, + uint32_t data, uint32_t mask) +{ + void *misc2_m = + MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2); + void *misc2_v = + MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2); + + data &= mask; + switch (reg_type) { + case REG_A: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data); + break; + case REG_B: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data); + break; + case REG_C_0: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data); + break; + case REG_C_1: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data); + break; + case REG_C_2: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data); + break; + case REG_C_3: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data); + break; + case REG_C_4: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data); + break; + case REG_C_5: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data); + break; + case REG_C_6: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data); + break; + case REG_C_7: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data); + break; + default: + assert(false); + break; + } +} + +/** * Add META item to matcher * * @param[in, out] matcher @@ -4922,21 +4994,15 @@ struct field_modify_info modify_tcp[] = { { const struct rte_flow_item_meta *meta_m; const struct rte_flow_item_meta *meta_v; - void *misc2_m = - MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2); - void *misc2_v = - MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2); meta_m = (const void *)item->mask; if (!meta_m) meta_m = &rte_flow_item_meta_mask; meta_v = (const void *)item->spec; - if (meta_v) { - MLX5_SET(fte_match_set_misc2, misc2_m, - metadata_reg_a, meta_m->data); - MLX5_SET(fte_match_set_misc2, misc2_v, - metadata_reg_a, meta_v->data & meta_m->data); - } + if (meta_v) + flow_dv_match_meta_reg(matcher, key, REG_A, + rte_cpu_to_be_32(meta_v->data), + rte_cpu_to_be_32(meta_m->data)); } /** @@ -4953,13 +5019,7 @@ struct field_modify_info modify_tcp[] = { flow_dv_translate_item_meta_vport(void *matcher, void *key, uint32_t value, uint32_t mask) { - void *misc2_m = - MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2); - void *misc2_v = - MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2); - - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, value); + flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask); } /** @@ -4973,81 +5033,14 @@ struct field_modify_info modify_tcp[] = { * Flow pattern to translate. */ static void -flow_dv_translate_item_tag(void *matcher, void *key, - const struct rte_flow_item *item) +flow_dv_translate_mlx5_item_tag(void *matcher, void *key, + const struct rte_flow_item *item) { - void *misc2_m = - MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2); - void *misc2_v = - MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2); const struct mlx5_rte_flow_item_tag *tag_v = item->spec; const struct mlx5_rte_flow_item_tag *tag_m = item->mask; enum modify_reg reg = tag_v->id; - rte_be32_t value = tag_v->data; - rte_be32_t mask = tag_m->data; - switch (reg) { - case REG_A: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, - rte_be_to_cpu_32(value)); - break; - case REG_B: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, - rte_be_to_cpu_32(value)); - break; - case REG_C_0: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, - rte_be_to_cpu_32(value)); - break; - case REG_C_1: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, - rte_be_to_cpu_32(value)); - break; - case REG_C_2: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, - rte_be_to_cpu_32(value)); - break; - case REG_C_3: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, - rte_be_to_cpu_32(value)); - break; - case REG_C_4: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, - rte_be_to_cpu_32(value)); - break; - case REG_C_5: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, - rte_be_to_cpu_32(value)); - break; - case REG_C_6: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, - rte_be_to_cpu_32(value)); - break; - case REG_C_7: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, - rte_be_to_cpu_32(value)); - break; - } + flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data); } /** @@ -6179,8 +6172,8 @@ struct field_modify_info modify_tcp[] = { last_item = MLX5_FLOW_LAYER_ICMP6; break; case MLX5_RTE_FLOW_ITEM_TYPE_TAG: - flow_dv_translate_item_tag(match_mask, match_value, - items); + flow_dv_translate_mlx5_item_tag(match_mask, + match_value, items); last_item = MLX5_FLOW_ITEM_TAG; break; case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE: -- 1.8.3.1