* [PATCH 1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
@ 2019-11-12 16:38 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-11-12 16:38 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Not sure where the single pipe only restriction came for fbc1.
Nothing I can see that would prevent this.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 -
drivers/gpu/drm/i915/display/intel_fbc.c | 47 --------------------
drivers/gpu/drm/i915/display/intel_fbc.h | 1 -
drivers/gpu/drm/i915/i915_drv.h | 1 -
4 files changed, 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5f3340554149..81287ff438db 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17798,8 +17798,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
}
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
-
- intel_fbc_init_pipe_state(dev_priv);
}
void intel_display_resume(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 92c7eb243559..e5f4e9f23308 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -419,25 +419,6 @@ static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
fbc->no_fbc_reason = reason;
}
-static bool multiple_pipes_ok(struct intel_crtc *crtc,
- struct intel_plane_state *plane_state)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
- enum pipe pipe = crtc->pipe;
-
- /* Don't even bother tracking anything we don't need. */
- if (!no_fbc_on_multiple_pipes(dev_priv))
- return true;
-
- if (plane_state->uapi.visible)
- fbc->visible_pipes_mask |= (1 << pipe);
- else
- fbc->visible_pipes_mask &= ~(1 << pipe);
-
- return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
-}
-
static int find_compression_threshold(struct drm_i915_private *dev_priv,
struct drm_mm_node *node,
int size,
@@ -867,18 +848,12 @@ void intel_fbc_pre_update(struct intel_crtc *crtc,
mutex_lock(&fbc->lock);
- if (!multiple_pipes_ok(crtc, plane_state)) {
- reason = "more than one pipe active";
- goto deactivate;
- }
-
if (!fbc->enabled || fbc->crtc != crtc)
goto unlock;
intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
fbc->flip_pending = true;
-deactivate:
intel_fbc_deactivate(dev_priv, reason);
unlock:
mutex_unlock(&fbc->lock);
@@ -1244,28 +1219,6 @@ void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
schedule_work(&fbc->underrun_work);
}
-/**
- * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
- * @dev_priv: i915 device instance
- *
- * The FBC code needs to track CRTC visibility since the older platforms can't
- * have FBC enabled while multiple pipes are used. This function does the
- * initial setup at driver load to make sure FBC is matching the real hardware.
- */
-void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
-{
- struct intel_crtc *crtc;
-
- /* Don't even bother tracking anything if we don't need. */
- if (!no_fbc_on_multiple_pipes(dev_priv))
- return;
-
- for_each_intel_crtc(&dev_priv->drm, crtc)
- if (intel_crtc_active(crtc) &&
- crtc->base.primary->state->visible)
- dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
-}
-
/*
* The DDX driver changes its behavior depending on the value it reads from
* i915.enable_fbc, so sanitize it by translating the default value into either
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 50272eda8d43..ba8eeefd4d9a 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -24,7 +24,6 @@ void intel_fbc_pre_update(struct intel_crtc *crtc,
struct intel_plane_state *plane_state);
void intel_fbc_post_update(struct intel_crtc *crtc);
void intel_fbc_init(struct drm_i915_private *dev_priv);
-void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
void intel_fbc_enable(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b82ff0bc6d0c..d94dd1a7ae5d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -366,7 +366,6 @@ struct intel_fbc {
unsigned threshold;
unsigned int possible_framebuffer_bits;
unsigned int busy_bits;
- unsigned int visible_pipes_mask;
struct intel_crtc *crtc;
struct drm_mm_node compressed_fb;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
@ 2019-11-12 16:38 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-11-12 16:38 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Not sure where the single pipe only restriction came for fbc1.
Nothing I can see that would prevent this.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 -
drivers/gpu/drm/i915/display/intel_fbc.c | 47 --------------------
drivers/gpu/drm/i915/display/intel_fbc.h | 1 -
drivers/gpu/drm/i915/i915_drv.h | 1 -
4 files changed, 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5f3340554149..81287ff438db 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17798,8 +17798,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
}
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
-
- intel_fbc_init_pipe_state(dev_priv);
}
void intel_display_resume(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 92c7eb243559..e5f4e9f23308 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -419,25 +419,6 @@ static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
fbc->no_fbc_reason = reason;
}
-static bool multiple_pipes_ok(struct intel_crtc *crtc,
- struct intel_plane_state *plane_state)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
- enum pipe pipe = crtc->pipe;
-
- /* Don't even bother tracking anything we don't need. */
- if (!no_fbc_on_multiple_pipes(dev_priv))
- return true;
-
- if (plane_state->uapi.visible)
- fbc->visible_pipes_mask |= (1 << pipe);
- else
- fbc->visible_pipes_mask &= ~(1 << pipe);
-
- return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
-}
-
static int find_compression_threshold(struct drm_i915_private *dev_priv,
struct drm_mm_node *node,
int size,
@@ -867,18 +848,12 @@ void intel_fbc_pre_update(struct intel_crtc *crtc,
mutex_lock(&fbc->lock);
- if (!multiple_pipes_ok(crtc, plane_state)) {
- reason = "more than one pipe active";
- goto deactivate;
- }
-
if (!fbc->enabled || fbc->crtc != crtc)
goto unlock;
intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
fbc->flip_pending = true;
-deactivate:
intel_fbc_deactivate(dev_priv, reason);
unlock:
mutex_unlock(&fbc->lock);
@@ -1244,28 +1219,6 @@ void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
schedule_work(&fbc->underrun_work);
}
-/**
- * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
- * @dev_priv: i915 device instance
- *
- * The FBC code needs to track CRTC visibility since the older platforms can't
- * have FBC enabled while multiple pipes are used. This function does the
- * initial setup at driver load to make sure FBC is matching the real hardware.
- */
-void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
-{
- struct intel_crtc *crtc;
-
- /* Don't even bother tracking anything if we don't need. */
- if (!no_fbc_on_multiple_pipes(dev_priv))
- return;
-
- for_each_intel_crtc(&dev_priv->drm, crtc)
- if (intel_crtc_active(crtc) &&
- crtc->base.primary->state->visible)
- dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
-}
-
/*
* The DDX driver changes its behavior depending on the value it reads from
* i915.enable_fbc, so sanitize it by translating the default value into either
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 50272eda8d43..ba8eeefd4d9a 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -24,7 +24,6 @@ void intel_fbc_pre_update(struct intel_crtc *crtc,
struct intel_plane_state *plane_state);
void intel_fbc_post_update(struct intel_crtc *crtc);
void intel_fbc_init(struct drm_i915_private *dev_priv);
-void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
void intel_fbc_enable(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b82ff0bc6d0c..d94dd1a7ae5d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -366,7 +366,6 @@ struct intel_fbc {
unsigned threshold;
unsigned int possible_framebuffer_bits;
unsigned int busy_bits;
- unsigned int visible_pipes_mask;
struct intel_crtc *crtc;
struct drm_mm_node compressed_fb;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/4] drm/i915: Relocate intel_crtc_active()
@ 2019-11-12 16:38 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-11-12 16:38 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move intel_crtc_active() next to its only remaining
user (pre-g4x wm code).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 19 -------------------
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++++++++
3 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 81287ff438db..e7e5497e6f2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1040,25 +1040,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
NULL, best_clock);
}
-bool intel_crtc_active(struct intel_crtc *crtc)
-{
- /* Be paranoid as we can arrive here with only partial
- * state retrieved from the hardware during setup.
- *
- * We can ditch the adjusted_mode.crtc_clock check as soon
- * as Haswell has gained clock readout/fastboot support.
- *
- * We can ditch the crtc->primary->state->fb check as soon as we can
- * properly reconstruct framebuffers.
- *
- * FIXME: The intel_crtc->active here should be switched to
- * crtc->state->active once we have proper CRTC states wired up
- * for atomic.
- */
- return crtc->active && crtc->base.primary->state->fb &&
- crtc->config->hw.adjusted_mode.crtc_clock;
-}
-
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index a5ec5eeff056..d18dc260fe83 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -558,7 +558,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
struct dpll *best_clock);
int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
-bool intel_crtc_active(struct intel_crtc *crtc);
bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2d389e437e87..d5e9b935f4e7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -806,6 +806,25 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
return plane_state->uapi.visible;
}
+static bool intel_crtc_active(struct intel_crtc *crtc)
+{
+ /* Be paranoid as we can arrive here with only partial
+ * state retrieved from the hardware during setup.
+ *
+ * We can ditch the adjusted_mode.crtc_clock check as soon
+ * as Haswell has gained clock readout/fastboot support.
+ *
+ * We can ditch the crtc->primary->state->fb check as soon as we can
+ * properly reconstruct framebuffers.
+ *
+ * FIXME: The intel_crtc->active here should be switched to
+ * crtc->state->active once we have proper CRTC states wired up
+ * for atomic.
+ */
+ return crtc->active && crtc->base.primary->state->fb &&
+ crtc->config->hw.adjusted_mode.crtc_clock;
+}
+
static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
{
struct intel_crtc *crtc, *enabled = NULL;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915: Relocate intel_crtc_active()
@ 2019-11-12 16:38 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-11-12 16:38 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move intel_crtc_active() next to its only remaining
user (pre-g4x wm code).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 19 -------------------
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++++++++
3 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 81287ff438db..e7e5497e6f2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1040,25 +1040,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
NULL, best_clock);
}
-bool intel_crtc_active(struct intel_crtc *crtc)
-{
- /* Be paranoid as we can arrive here with only partial
- * state retrieved from the hardware during setup.
- *
- * We can ditch the adjusted_mode.crtc_clock check as soon
- * as Haswell has gained clock readout/fastboot support.
- *
- * We can ditch the crtc->primary->state->fb check as soon as we can
- * properly reconstruct framebuffers.
- *
- * FIXME: The intel_crtc->active here should be switched to
- * crtc->state->active once we have proper CRTC states wired up
- * for atomic.
- */
- return crtc->active && crtc->base.primary->state->fb &&
- crtc->config->hw.adjusted_mode.crtc_clock;
-}
-
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index a5ec5eeff056..d18dc260fe83 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -558,7 +558,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
struct dpll *best_clock);
int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
-bool intel_crtc_active(struct intel_crtc *crtc);
bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2d389e437e87..d5e9b935f4e7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -806,6 +806,25 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
return plane_state->uapi.visible;
}
+static bool intel_crtc_active(struct intel_crtc *crtc)
+{
+ /* Be paranoid as we can arrive here with only partial
+ * state retrieved from the hardware during setup.
+ *
+ * We can ditch the adjusted_mode.crtc_clock check as soon
+ * as Haswell has gained clock readout/fastboot support.
+ *
+ * We can ditch the crtc->primary->state->fb check as soon as we can
+ * properly reconstruct framebuffers.
+ *
+ * FIXME: The intel_crtc->active here should be switched to
+ * crtc->state->active once we have proper CRTC states wired up
+ * for atomic.
+ */
+ return crtc->active && crtc->base.primary->state->fb &&
+ crtc->config->hw.adjusted_mode.crtc_clock;
+}
+
static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
{
struct intel_crtc *crtc, *enabled = NULL;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/4] drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx()
@ 2019-11-12 16:38 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-11-12 16:38 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's start to eliminate intel_pipe_to_cpu_transcoder() so that
we can get rid of one more crtc->config usage (which we will want
to nuke as well).
In the case of assert_fdi_tx() we know that we're never
dealing with the EDP transcoder so we can simply replace
this with a cast.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e7e5497e6f2e..cabd88337822 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1141,11 +1141,15 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
enum pipe pipe, bool state)
{
bool cur_state;
- enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
- pipe);
if (HAS_DDI(dev_priv)) {
- /* DDI does not have a specific FDI_TX register */
+ /*
+ * DDI does not have a specific FDI_TX register.
+ *
+ * FDI is never hooked fed from EDP transcoder
+ * so pipe->transcoder cast is fine here.
+ */
+ enum transcoder cpu_transcoder = (enum transcoder)pipe;
u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
} else {
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx()
@ 2019-11-12 16:38 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-11-12 16:38 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's start to eliminate intel_pipe_to_cpu_transcoder() so that
we can get rid of one more crtc->config usage (which we will want
to nuke as well).
In the case of assert_fdi_tx() we know that we're never
dealing with the EDP transcoder so we can simply replace
this with a cast.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e7e5497e6f2e..cabd88337822 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1141,11 +1141,15 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
enum pipe pipe, bool state)
{
bool cur_state;
- enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
- pipe);
if (HAS_DDI(dev_priv)) {
- /* DDI does not have a specific FDI_TX register */
+ /*
+ * DDI does not have a specific FDI_TX register.
+ *
+ * FDI is never hooked fed from EDP transcoder
+ * so pipe->transcoder cast is fine here.
+ */
+ enum transcoder cpu_transcoder = (enum transcoder)pipe;
u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
} else {
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/4] drm/i915: Pass cpu transcoder to assert_pipe()
@ 2019-11-12 16:38 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-11-12 16:38 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to eliminate intel_pipe_to_cpu_transcoder() (and its
crtc->config usage) let's pass the cpu transcoder to
assert_pipe() so we don't have to do the pipe->cpu transcoder
lookup on HSW+.
On VLV/CHV this can get called during eDP init, which
happens before crtc->config->cpu_transcoder is even
populated. So currently we're always reading PIPECONF(A)
there even if we're trying to check the state of some
other pipe.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++------------
drivers/gpu/drm/i915/display/intel_display.h | 9 +++--
2 files changed, 18 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cabd88337822..6d2112f5bdd0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1040,14 +1040,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
NULL, best_clock);
}
-enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
- enum pipe pipe)
-{
- struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
-
- return crtc->config->cpu_transcoder;
-}
-
static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
@@ -1266,11 +1258,9 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
}
void assert_pipe(struct drm_i915_private *dev_priv,
- enum pipe pipe, bool state)
+ enum transcoder cpu_transcoder, bool state)
{
bool cur_state;
- enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
- pipe);
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
@@ -1290,8 +1280,9 @@ void assert_pipe(struct drm_i915_private *dev_priv,
}
I915_STATE_WARN(cur_state != state,
- "pipe %c assertion failure (expected %s, current %s)\n",
- pipe_name(pipe), onoff(state), onoff(cur_state));
+ "transcoder %s assertion failure (expected %s, current %s)\n",
+ transcoder_name(cpu_transcoder),
+ onoff(state), onoff(cur_state));
}
static void assert_plane(struct intel_plane *plane, bool state)
@@ -1418,7 +1409,7 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- assert_pipe_disabled(dev_priv, pipe);
+ assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
/* PLL is protected by panel, make sure we can write it */
assert_panel_unlocked(dev_priv, pipe);
@@ -1467,7 +1458,7 @@ static void chv_enable_pll(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- assert_pipe_disabled(dev_priv, pipe);
+ assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
/* PLL is protected by panel, make sure we can write it */
assert_panel_unlocked(dev_priv, pipe);
@@ -1514,7 +1505,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
u32 dpll = crtc_state->dpll_hw_state.dpll;
int i;
- assert_pipe_disabled(dev_priv, crtc->pipe);
+ assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
/* PLL is protected by panel, make sure we can write it */
if (i9xx_has_pps(dev_priv))
@@ -1563,7 +1554,7 @@ static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
return;
/* Make sure the pipe isn't still relying on us */
- assert_pipe_disabled(dev_priv, pipe);
+ assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
POSTING_READ(DPLL(pipe));
@@ -1574,7 +1565,7 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
u32 val;
/* Make sure the pipe isn't still relying on us */
- assert_pipe_disabled(dev_priv, pipe);
+ assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
val = DPLL_INTEGRATED_REF_CLK_VLV |
DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
@@ -1591,7 +1582,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
u32 val;
/* Make sure the pipe isn't still relying on us */
- assert_pipe_disabled(dev_priv, pipe);
+ assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
val = DPLL_SSC_REF_CLK_CHV |
DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
@@ -4617,7 +4608,7 @@ static void ironlake_fdi_link_train(struct intel_crtc *crtc,
u32 temp, tries;
/* FDI needs bits from pipe first */
- assert_pipe_enabled(dev_priv, pipe);
+ assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
for train result */
@@ -6805,7 +6796,7 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
* according to register description and PRM.
*/
WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
- assert_pipe_disabled(dev_priv, crtc->pipe);
+ assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
@@ -7116,7 +7107,7 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
if (!old_crtc_state->gmch_pfit.control)
return;
- assert_pipe_disabled(dev_priv, crtc->pipe);
+ assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
I915_READ(PFIT_CONTROL));
@@ -8128,6 +8119,7 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
return -ENOMEM;
pipe_config->uapi.crtc = &crtc->base;
+ pipe_config->cpu_transcoder = (enum transcoder)pipe;
pipe_config->pixel_multiplier = 1;
pipe_config->dpll = *dpll;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d18dc260fe83..f33096876a9a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -510,8 +510,6 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
enum port port);
int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
-enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
- enum pipe pipe);
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
@@ -613,9 +611,10 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
enum pipe pipe, bool state);
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
-void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
-#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
-#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
+void assert_pipe(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder, bool state);
+#define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
+#define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
* WARN_ON()) for hw state sanity checks to check for unexpected conditions
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: Pass cpu transcoder to assert_pipe()
@ 2019-11-12 16:38 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-11-12 16:38 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to eliminate intel_pipe_to_cpu_transcoder() (and its
crtc->config usage) let's pass the cpu transcoder to
assert_pipe() so we don't have to do the pipe->cpu transcoder
lookup on HSW+.
On VLV/CHV this can get called during eDP init, which
happens before crtc->config->cpu_transcoder is even
populated. So currently we're always reading PIPECONF(A)
there even if we're trying to check the state of some
other pipe.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++------------
drivers/gpu/drm/i915/display/intel_display.h | 9 +++--
2 files changed, 18 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cabd88337822..6d2112f5bdd0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1040,14 +1040,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
NULL, best_clock);
}
-enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
- enum pipe pipe)
-{
- struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
-
- return crtc->config->cpu_transcoder;
-}
-
static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
@@ -1266,11 +1258,9 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
}
void assert_pipe(struct drm_i915_private *dev_priv,
- enum pipe pipe, bool state)
+ enum transcoder cpu_transcoder, bool state)
{
bool cur_state;
- enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
- pipe);
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
@@ -1290,8 +1280,9 @@ void assert_pipe(struct drm_i915_private *dev_priv,
}
I915_STATE_WARN(cur_state != state,
- "pipe %c assertion failure (expected %s, current %s)\n",
- pipe_name(pipe), onoff(state), onoff(cur_state));
+ "transcoder %s assertion failure (expected %s, current %s)\n",
+ transcoder_name(cpu_transcoder),
+ onoff(state), onoff(cur_state));
}
static void assert_plane(struct intel_plane *plane, bool state)
@@ -1418,7 +1409,7 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- assert_pipe_disabled(dev_priv, pipe);
+ assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
/* PLL is protected by panel, make sure we can write it */
assert_panel_unlocked(dev_priv, pipe);
@@ -1467,7 +1458,7 @@ static void chv_enable_pll(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- assert_pipe_disabled(dev_priv, pipe);
+ assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
/* PLL is protected by panel, make sure we can write it */
assert_panel_unlocked(dev_priv, pipe);
@@ -1514,7 +1505,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
u32 dpll = crtc_state->dpll_hw_state.dpll;
int i;
- assert_pipe_disabled(dev_priv, crtc->pipe);
+ assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
/* PLL is protected by panel, make sure we can write it */
if (i9xx_has_pps(dev_priv))
@@ -1563,7 +1554,7 @@ static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
return;
/* Make sure the pipe isn't still relying on us */
- assert_pipe_disabled(dev_priv, pipe);
+ assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
POSTING_READ(DPLL(pipe));
@@ -1574,7 +1565,7 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
u32 val;
/* Make sure the pipe isn't still relying on us */
- assert_pipe_disabled(dev_priv, pipe);
+ assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
val = DPLL_INTEGRATED_REF_CLK_VLV |
DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
@@ -1591,7 +1582,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
u32 val;
/* Make sure the pipe isn't still relying on us */
- assert_pipe_disabled(dev_priv, pipe);
+ assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
val = DPLL_SSC_REF_CLK_CHV |
DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
@@ -4617,7 +4608,7 @@ static void ironlake_fdi_link_train(struct intel_crtc *crtc,
u32 temp, tries;
/* FDI needs bits from pipe first */
- assert_pipe_enabled(dev_priv, pipe);
+ assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
for train result */
@@ -6805,7 +6796,7 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
* according to register description and PRM.
*/
WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
- assert_pipe_disabled(dev_priv, crtc->pipe);
+ assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
@@ -7116,7 +7107,7 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
if (!old_crtc_state->gmch_pfit.control)
return;
- assert_pipe_disabled(dev_priv, crtc->pipe);
+ assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
I915_READ(PFIT_CONTROL));
@@ -8128,6 +8119,7 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
return -ENOMEM;
pipe_config->uapi.crtc = &crtc->base;
+ pipe_config->cpu_transcoder = (enum transcoder)pipe;
pipe_config->pixel_multiplier = 1;
pipe_config->dpll = *dpll;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d18dc260fe83..f33096876a9a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -510,8 +510,6 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
enum port port);
int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
-enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
- enum pipe pipe);
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
@@ -613,9 +611,10 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
enum pipe pipe, bool state);
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
-void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
-#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
-#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
+void assert_pipe(struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder, bool state);
+#define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
+#define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
* WARN_ON()) for hw state sanity checks to check for unexpected conditions
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
@ 2019-11-12 21:45 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-11-12 21:45 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
URL : https://patchwork.freedesktop.org/series/69366/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
Okay!
Commit: drm/i915: Relocate intel_crtc_active()
Okay!
Commit: drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx()
Okay!
Commit: drm/i915: Pass cpu transcoder to assert_pipe()
+drivers/gpu/drm/i915/display/intel_dp.c:3040:9: int enum pipe versus
+drivers/gpu/drm/i915/display/intel_dp.c:3040:9: int enum transcoder
+drivers/gpu/drm/i915/display/intel_dp.c:3040:9: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_dp.c:3080:9: int enum pipe versus
+drivers/gpu/drm/i915/display/intel_dp.c:3080:9: int enum transcoder
+drivers/gpu/drm/i915/display/intel_dp.c:3080:9: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_tv.c:1530:9: int enum pipe versus
+drivers/gpu/drm/i915/display/intel_tv.c:1530:9: int enum transcoder
+drivers/gpu/drm/i915/display/intel_tv.c:1530:9: warning: mixing different enum types
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
@ 2019-11-12 21:45 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-11-12 21:45 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
URL : https://patchwork.freedesktop.org/series/69366/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
Okay!
Commit: drm/i915: Relocate intel_crtc_active()
Okay!
Commit: drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx()
Okay!
Commit: drm/i915: Pass cpu transcoder to assert_pipe()
+drivers/gpu/drm/i915/display/intel_dp.c:3040:9: int enum pipe versus
+drivers/gpu/drm/i915/display/intel_dp.c:3040:9: int enum transcoder
+drivers/gpu/drm/i915/display/intel_dp.c:3040:9: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_dp.c:3080:9: int enum pipe versus
+drivers/gpu/drm/i915/display/intel_dp.c:3080:9: int enum transcoder
+drivers/gpu/drm/i915/display/intel_dp.c:3080:9: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_tv.c:1530:9: int enum pipe versus
+drivers/gpu/drm/i915/display/intel_tv.c:1530:9: int enum transcoder
+drivers/gpu/drm/i915/display/intel_tv.c:1530:9: warning: mixing different enum types
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
@ 2019-11-12 22:17 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-11-12 22:17 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
URL : https://patchwork.freedesktop.org/series/69366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7323 -> Patchwork_15241
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/index.html
Known issues
------------
Here are the changes found in Patchwork_15241 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_busy@basic-flip-pipe-b:
- fi-skl-6770hq: [PASS][1] -> [DMESG-WARN][2] ([fdo#105541])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111045] / [fdo#111096])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-copy:
- fi-glk-dsi: [INCOMPLETE][5] ([fdo#103359] / [k.org#198133]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-skl-6770hq: [DMESG-WARN][7] ([fdo#105541]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
[fdo#110343]: https://bugs.freedesktop.org/show_bug.cgi?id=110343
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (51 -> 46)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7323 -> Patchwork_15241
CI-20190529: 20190529
CI_DRM_7323: aac244f23bf1eaf986c5df9e529863b34e52bee8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5273: 602003c3d751c72fc309a0e64d4193f6da720f6b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15241: f783f15d590106ebbbc9e7ba64b3fa8519b00c4a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f783f15d5901 drm/i915: Pass cpu transcoder to assert_pipe()
c805924f6a73 drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx()
aea2d6ba7337 drm/i915: Relocate intel_crtc_active()
d8e3b4babc16 drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
@ 2019-11-12 22:17 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-11-12 22:17 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
URL : https://patchwork.freedesktop.org/series/69366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7323 -> Patchwork_15241
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/index.html
Known issues
------------
Here are the changes found in Patchwork_15241 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_busy@basic-flip-pipe-b:
- fi-skl-6770hq: [PASS][1] -> [DMESG-WARN][2] ([fdo#105541])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111045] / [fdo#111096])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-copy:
- fi-glk-dsi: [INCOMPLETE][5] ([fdo#103359] / [k.org#198133]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-skl-6770hq: [DMESG-WARN][7] ([fdo#105541]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
[fdo#110343]: https://bugs.freedesktop.org/show_bug.cgi?id=110343
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (51 -> 46)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7323 -> Patchwork_15241
CI-20190529: 20190529
CI_DRM_7323: aac244f23bf1eaf986c5df9e529863b34e52bee8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5273: 602003c3d751c72fc309a0e64d4193f6da720f6b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15241: f783f15d590106ebbbc9e7ba64b3fa8519b00c4a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f783f15d5901 drm/i915: Pass cpu transcoder to assert_pipe()
c805924f6a73 drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx()
aea2d6ba7337 drm/i915: Relocate intel_crtc_active()
d8e3b4babc16 drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/4] drm/i915: Relocate intel_crtc_active()
@ 2019-11-13 6:29 ` Lucas De Marchi
0 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2019-11-13 6:29 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Intel Graphics
On Tue, Nov 12, 2019 at 8:38 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move intel_crtc_active() next to its only remaining
> user (pre-g4x wm code).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 19 -------------------
> drivers/gpu/drm/i915/display/intel_display.h | 1 -
> drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++++++++
> 3 files changed, 19 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 81287ff438db..e7e5497e6f2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1040,25 +1040,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
> NULL, best_clock);
> }
>
> -bool intel_crtc_active(struct intel_crtc *crtc)
> -{
> - /* Be paranoid as we can arrive here with only partial
> - * state retrieved from the hardware during setup.
> - *
> - * We can ditch the adjusted_mode.crtc_clock check as soon
> - * as Haswell has gained clock readout/fastboot support.
> - *
> - * We can ditch the crtc->primary->state->fb check as soon as we can
> - * properly reconstruct framebuffers.
> - *
> - * FIXME: The intel_crtc->active here should be switched to
> - * crtc->state->active once we have proper CRTC states wired up
> - * for atomic.
> - */
> - return crtc->active && crtc->base.primary->state->fb &&
> - crtc->config->hw.adjusted_mode.crtc_clock;
> -}
> -
> enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index a5ec5eeff056..d18dc260fe83 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -558,7 +558,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
> struct dpll *best_clock);
> int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
>
> -bool intel_crtc_active(struct intel_crtc *crtc);
> bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
> void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
> void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2d389e437e87..d5e9b935f4e7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -806,6 +806,25 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
> return plane_state->uapi.visible;
> }
>
> +static bool intel_crtc_active(struct intel_crtc *crtc)
maybe shouldn't have an intel_ prefix... ?
anyway
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> +{
> + /* Be paranoid as we can arrive here with only partial
> + * state retrieved from the hardware during setup.
> + *
> + * We can ditch the adjusted_mode.crtc_clock check as soon
> + * as Haswell has gained clock readout/fastboot support.
> + *
> + * We can ditch the crtc->primary->state->fb check as soon as we can
> + * properly reconstruct framebuffers.
> + *
> + * FIXME: The intel_crtc->active here should be switched to
> + * crtc->state->active once we have proper CRTC states wired up
> + * for atomic.
> + */
> + return crtc->active && crtc->base.primary->state->fb &&
> + crtc->config->hw.adjusted_mode.crtc_clock;
> +}
> +
> static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
> {
> struct intel_crtc *crtc, *enabled = NULL;
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Relocate intel_crtc_active()
@ 2019-11-13 6:29 ` Lucas De Marchi
0 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2019-11-13 6:29 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Intel Graphics
On Tue, Nov 12, 2019 at 8:38 AM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move intel_crtc_active() next to its only remaining
> user (pre-g4x wm code).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 19 -------------------
> drivers/gpu/drm/i915/display/intel_display.h | 1 -
> drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++++++++
> 3 files changed, 19 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 81287ff438db..e7e5497e6f2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1040,25 +1040,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
> NULL, best_clock);
> }
>
> -bool intel_crtc_active(struct intel_crtc *crtc)
> -{
> - /* Be paranoid as we can arrive here with only partial
> - * state retrieved from the hardware during setup.
> - *
> - * We can ditch the adjusted_mode.crtc_clock check as soon
> - * as Haswell has gained clock readout/fastboot support.
> - *
> - * We can ditch the crtc->primary->state->fb check as soon as we can
> - * properly reconstruct framebuffers.
> - *
> - * FIXME: The intel_crtc->active here should be switched to
> - * crtc->state->active once we have proper CRTC states wired up
> - * for atomic.
> - */
> - return crtc->active && crtc->base.primary->state->fb &&
> - crtc->config->hw.adjusted_mode.crtc_clock;
> -}
> -
> enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index a5ec5eeff056..d18dc260fe83 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -558,7 +558,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
> struct dpll *best_clock);
> int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
>
> -bool intel_crtc_active(struct intel_crtc *crtc);
> bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
> void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
> void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2d389e437e87..d5e9b935f4e7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -806,6 +806,25 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
> return plane_state->uapi.visible;
> }
>
> +static bool intel_crtc_active(struct intel_crtc *crtc)
maybe shouldn't have an intel_ prefix... ?
anyway
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> +{
> + /* Be paranoid as we can arrive here with only partial
> + * state retrieved from the hardware during setup.
> + *
> + * We can ditch the adjusted_mode.crtc_clock check as soon
> + * as Haswell has gained clock readout/fastboot support.
> + *
> + * We can ditch the crtc->primary->state->fb check as soon as we can
> + * properly reconstruct framebuffers.
> + *
> + * FIXME: The intel_crtc->active here should be switched to
> + * crtc->state->active once we have proper CRTC states wired up
> + * for atomic.
> + */
> + return crtc->active && crtc->base.primary->state->fb &&
> + crtc->config->hw.adjusted_mode.crtc_clock;
> +}
> +
> static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
> {
> struct intel_crtc *crtc, *enabled = NULL;
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
@ 2019-11-13 10:24 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-11-13 10:24 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
URL : https://patchwork.freedesktop.org/series/69366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7323_full -> Patchwork_15241_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_15241_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs0-s3:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-apl3/igt@gem_ctx_isolation@vcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-apl1/igt@gem_ctx_isolation@vcs0-s3.html
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_exec_balancer@smoke.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb5/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_nop@basic-sequential:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([fdo#111747])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@gem_exec_nop@basic-sequential.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb6/igt@gem_exec_nop@basic-sequential.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112080]) +13 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_exec_parallel@vcs1-fds.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb8/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([fdo#110789] / [fdo#111870])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw1/igt@gem_userptr_blits@sync-unmap-after-close.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-hsw4/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#104108]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl9/igt@i915_pm_backlight@fade_with_suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl1/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: [PASS][19] -> [SKIP][20] ([fdo#109271])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb7/igt@i915_pm_rc6_residency@rc6-accuracy.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-snb1/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_selftest@live_hangcheck:
- shard-hsw: [PASS][21] -> [DMESG-FAIL][22] ([fdo#111991])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw4/igt@i915_selftest@live_hangcheck.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-hsw8/igt@i915_selftest@live_hangcheck.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-skl: [PASS][23] -> [DMESG-WARN][24] ([fdo#106107])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl5/igt@kms_color@pipe-a-ctm-0-75.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl6/igt@kms_color@pipe-a-ctm-0-75.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen:
- shard-skl: [PASS][25] -> [FAIL][26] ([fdo#103232])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-apl: [PASS][27] -> [FAIL][28] ([fdo#105363])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-apl1/igt@kms_flip@flip-vs-expired-vblank.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-apl3/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#105363])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-hsw: [PASS][31] -> [INCOMPLETE][32] ([fdo#103540])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw1/igt@kms_flip@flip-vs-suspend-interruptible.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-hsw2/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@basic:
- shard-tglb: [PASS][33] -> [FAIL][34] ([fdo# 112163] / [fdo#103167])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb2/igt@kms_frontbuffer_tracking@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][35] -> [FAIL][36] ([fdo#103167]) +5 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-tglb: [PASS][37] -> [FAIL][38] ([fdo#103167])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-iclb: [PASS][39] -> [FAIL][40] ([fdo#103167] / [fdo#110378])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
- shard-skl: [PASS][41] -> [FAIL][42] ([fdo#103167])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][43] -> [DMESG-WARN][44] ([fdo#108566]) +4 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-tglb: [PASS][45] -> [INCOMPLETE][46] ([fdo#111832] / [fdo#111850]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][47] -> [FAIL][48] ([fdo#108145] / [fdo#110403])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][49] -> [SKIP][50] ([fdo#109642] / [fdo#111068])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb7/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][51] -> [SKIP][52] ([fdo#109441]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb8/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][53] -> [FAIL][54] ([fdo#99912])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl6/igt@kms_setmode@basic.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-kbl1/igt@kms_setmode@basic.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][55] -> [SKIP][56] ([fdo#109276]) +19 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][57] ([fdo#112080]) -> [PASS][58] +12 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb3/igt@gem_busy@busy-vcs1.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb2/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [DMESG-WARN][59] ([fdo#108566]) -> [PASS][60] +5 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl7/igt@gem_ctx_isolation@rcs0-s3.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [SKIP][61] ([fdo#109276] / [fdo#112080]) -> [PASS][62] +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb6/igt@gem_ctx_persistence@vcs1-queued.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb1/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_exec_parallel@basic:
- shard-tglb: [INCOMPLETE][63] ([fdo#111887]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@gem_exec_parallel@basic.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb7/igt@gem_exec_parallel@basic.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [SKIP][65] ([fdo#109276]) -> [PASS][66] +18 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb6/igt@gem_exec_schedule@independent-bsd2.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb1/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][67] ([fdo#112146]) -> [PASS][68] +7 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_sync@basic-each:
- shard-tglb: [INCOMPLETE][69] ([fdo#111647] / [fdo#111998]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb6/igt@gem_sync@basic-each.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb6/igt@gem_sync@basic-each.html
* igt@gem_sync@basic-store-all:
- shard-tglb: [INCOMPLETE][71] ([fdo#111647]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb6/igt@gem_sync@basic-store-all.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb7/igt@gem_sync@basic-store-all.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-tglb: [INCOMPLETE][73] ([fdo#111832] / [fdo#111850]) -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb1/igt@i915_pm_rpm@system-suspend-modeset.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb1/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@i915_selftest@live_execlists:
- shard-glk: [INCOMPLETE][75] ([fdo#103359] / [k.org#198133]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-glk5/igt@i915_selftest@live_execlists.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-glk2/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- shard-snb: [INCOMPLETE][77] ([fdo#105411]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb5/igt@i915_selftest@live_hangcheck.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-snb7/igt@i915_selftest@live_hangcheck.html
* igt@kms_color@pipe-b-ctm-0-5:
- shard-skl: [DMESG-WARN][79] ([fdo#106107]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl9/igt@kms_color@pipe-b-ctm-0-5.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl1/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [DMESG-WARN][81] ([fdo#108566]) -> [PASS][82] +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [FAIL][83] ([fdo#105363]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
- shard-tglb: [FAIL][85] ([fdo#103167]) -> [PASS][86] +4 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
- shard-iclb: [FAIL][87] ([fdo#103167]) -> [PASS][88] +7 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][89] ([fdo#109441]) -> [PASS][90] +2 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb6/igt@kms_psr@psr2_basic.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb2/igt@kms_psr@psr2_basic.html
* igt@kms_psr@suspend:
- shard-skl: [INCOMPLETE][91] ([fdo#108972]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl9/igt@kms_psr@suspend.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl2/igt@kms_psr@suspend.html
* igt@kms_vblank@pipe-b-wait-busy-hang:
- shard-snb: [SKIP][93] ([fdo#109271]) -> [PASS][94] +4 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb6/igt@kms_vblank@pipe-b-wait-busy-hang.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-snb5/igt@kms_vblank@pipe-b-wait-busy-hang.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-tglb: [INCOMPLETE][95] ([fdo#111850]) -> [PASS][96] +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb8/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv-switch:
- shard-iclb: [SKIP][97] ([fdo#109276] / [fdo#112080]) -> [FAIL][98] ([fdo#111329])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
* igt@gem_exec_schedule@deep-bsd1:
- shard-tglb: [FAIL][99] ([fdo#111646]) -> [INCOMPLETE][100] ([fdo#111671]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb3/igt@gem_exec_schedule@deep-bsd1.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb3/igt@gem_exec_schedule@deep-bsd1.html
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [SKIP][101] ([fdo#109276]) -> [FAIL][102] ([fdo#111330]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb5/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][103] ([fdo#111330]) -> [SKIP][104] ([fdo#109276])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_mocs_settings@mocs-reset-bsd2.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb7/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-tglb: [FAIL][105] ([fdo#111703]) -> [INCOMPLETE][106] ([fdo#111832] / [fdo#111850])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb9/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [DMESG-WARN][107] ([fdo#107724]) -> [SKIP][108] ([fdo#109441])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@kms_psr@psr2_suspend.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
@ 2019-11-13 10:24 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-11-13 10:24 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction
URL : https://patchwork.freedesktop.org/series/69366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7323_full -> Patchwork_15241_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_15241_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs0-s3:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-apl3/igt@gem_ctx_isolation@vcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-apl1/igt@gem_ctx_isolation@vcs0-s3.html
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_exec_balancer@smoke.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb5/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_nop@basic-sequential:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([fdo#111747])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@gem_exec_nop@basic-sequential.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb6/igt@gem_exec_nop@basic-sequential.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112080]) +13 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_exec_parallel@vcs1-fds.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb8/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([fdo#110789] / [fdo#111870])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw1/igt@gem_userptr_blits@sync-unmap-after-close.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-hsw4/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#104108]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl9/igt@i915_pm_backlight@fade_with_suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl1/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: [PASS][19] -> [SKIP][20] ([fdo#109271])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb7/igt@i915_pm_rc6_residency@rc6-accuracy.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-snb1/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_selftest@live_hangcheck:
- shard-hsw: [PASS][21] -> [DMESG-FAIL][22] ([fdo#111991])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw4/igt@i915_selftest@live_hangcheck.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-hsw8/igt@i915_selftest@live_hangcheck.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-skl: [PASS][23] -> [DMESG-WARN][24] ([fdo#106107])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl5/igt@kms_color@pipe-a-ctm-0-75.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl6/igt@kms_color@pipe-a-ctm-0-75.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen:
- shard-skl: [PASS][25] -> [FAIL][26] ([fdo#103232])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-apl: [PASS][27] -> [FAIL][28] ([fdo#105363])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-apl1/igt@kms_flip@flip-vs-expired-vblank.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-apl3/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#105363])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-hsw: [PASS][31] -> [INCOMPLETE][32] ([fdo#103540])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw1/igt@kms_flip@flip-vs-suspend-interruptible.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-hsw2/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@basic:
- shard-tglb: [PASS][33] -> [FAIL][34] ([fdo# 112163] / [fdo#103167])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb2/igt@kms_frontbuffer_tracking@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][35] -> [FAIL][36] ([fdo#103167]) +5 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-tglb: [PASS][37] -> [FAIL][38] ([fdo#103167])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-iclb: [PASS][39] -> [FAIL][40] ([fdo#103167] / [fdo#110378])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
- shard-skl: [PASS][41] -> [FAIL][42] ([fdo#103167])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][43] -> [DMESG-WARN][44] ([fdo#108566]) +4 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-tglb: [PASS][45] -> [INCOMPLETE][46] ([fdo#111832] / [fdo#111850]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][47] -> [FAIL][48] ([fdo#108145] / [fdo#110403])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][49] -> [SKIP][50] ([fdo#109642] / [fdo#111068])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb7/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][51] -> [SKIP][52] ([fdo#109441]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb8/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][53] -> [FAIL][54] ([fdo#99912])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl6/igt@kms_setmode@basic.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-kbl1/igt@kms_setmode@basic.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][55] -> [SKIP][56] ([fdo#109276]) +19 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][57] ([fdo#112080]) -> [PASS][58] +12 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb3/igt@gem_busy@busy-vcs1.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb2/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [DMESG-WARN][59] ([fdo#108566]) -> [PASS][60] +5 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl7/igt@gem_ctx_isolation@rcs0-s3.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [SKIP][61] ([fdo#109276] / [fdo#112080]) -> [PASS][62] +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb6/igt@gem_ctx_persistence@vcs1-queued.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb1/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_exec_parallel@basic:
- shard-tglb: [INCOMPLETE][63] ([fdo#111887]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@gem_exec_parallel@basic.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb7/igt@gem_exec_parallel@basic.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [SKIP][65] ([fdo#109276]) -> [PASS][66] +18 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb6/igt@gem_exec_schedule@independent-bsd2.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb1/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][67] ([fdo#112146]) -> [PASS][68] +7 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_sync@basic-each:
- shard-tglb: [INCOMPLETE][69] ([fdo#111647] / [fdo#111998]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb6/igt@gem_sync@basic-each.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb6/igt@gem_sync@basic-each.html
* igt@gem_sync@basic-store-all:
- shard-tglb: [INCOMPLETE][71] ([fdo#111647]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb6/igt@gem_sync@basic-store-all.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb7/igt@gem_sync@basic-store-all.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-tglb: [INCOMPLETE][73] ([fdo#111832] / [fdo#111850]) -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb1/igt@i915_pm_rpm@system-suspend-modeset.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb1/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@i915_selftest@live_execlists:
- shard-glk: [INCOMPLETE][75] ([fdo#103359] / [k.org#198133]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-glk5/igt@i915_selftest@live_execlists.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-glk2/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- shard-snb: [INCOMPLETE][77] ([fdo#105411]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb5/igt@i915_selftest@live_hangcheck.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-snb7/igt@i915_selftest@live_hangcheck.html
* igt@kms_color@pipe-b-ctm-0-5:
- shard-skl: [DMESG-WARN][79] ([fdo#106107]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl9/igt@kms_color@pipe-b-ctm-0-5.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl1/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [DMESG-WARN][81] ([fdo#108566]) -> [PASS][82] +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [FAIL][83] ([fdo#105363]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
- shard-tglb: [FAIL][85] ([fdo#103167]) -> [PASS][86] +4 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
- shard-iclb: [FAIL][87] ([fdo#103167]) -> [PASS][88] +7 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][89] ([fdo#109441]) -> [PASS][90] +2 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb6/igt@kms_psr@psr2_basic.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb2/igt@kms_psr@psr2_basic.html
* igt@kms_psr@suspend:
- shard-skl: [INCOMPLETE][91] ([fdo#108972]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl9/igt@kms_psr@suspend.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-skl2/igt@kms_psr@suspend.html
* igt@kms_vblank@pipe-b-wait-busy-hang:
- shard-snb: [SKIP][93] ([fdo#109271]) -> [PASS][94] +4 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb6/igt@kms_vblank@pipe-b-wait-busy-hang.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-snb5/igt@kms_vblank@pipe-b-wait-busy-hang.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-tglb: [INCOMPLETE][95] ([fdo#111850]) -> [PASS][96] +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb8/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv-switch:
- shard-iclb: [SKIP][97] ([fdo#109276] / [fdo#112080]) -> [FAIL][98] ([fdo#111329])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
* igt@gem_exec_schedule@deep-bsd1:
- shard-tglb: [FAIL][99] ([fdo#111646]) -> [INCOMPLETE][100] ([fdo#111671]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb3/igt@gem_exec_schedule@deep-bsd1.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb3/igt@gem_exec_schedule@deep-bsd1.html
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [SKIP][101] ([fdo#109276]) -> [FAIL][102] ([fdo#111330]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb5/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][103] ([fdo#111330]) -> [SKIP][104] ([fdo#109276])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_mocs_settings@mocs-reset-bsd2.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-iclb7/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-tglb: [FAIL][105] ([fdo#111703]) -> [INCOMPLETE][106] ([fdo#111832] / [fdo#111850])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb9/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [DMESG-WARN][107] ([fdo#107724]) -> [SKIP][108] ([fdo#109441])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@kms_psr@psr2_suspend.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15241/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx()
2019-11-12 16:38 ` [Intel-gfx] " Ville Syrjala
(?)
@ 2019-12-10 18:19 ` Souza, Jose
2019-12-10 19:55 ` Ville Syrjälä
-1 siblings, 1 reply; 22+ messages in thread
From: Souza, Jose @ 2019-12-10 18:19 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Tue, 2019-11-12 at 18:38 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's start to eliminate intel_pipe_to_cpu_transcoder() so that
> we can get rid of one more crtc->config usage (which we will want
> to nuke as well).
>
> In the case of assert_fdi_tx() we know that we're never
> dealing with the EDP transcoder so we can simply replace
> this with a cast.
There still one EDP transcoder case when running in a HSW:
haswell_crtc_enable()
lpt_pch_enable()
lpt_enable_pch_transcoder()
assert_fdi_tx_enabled()
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e7e5497e6f2e..cabd88337822 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1141,11 +1141,15 @@ static void assert_fdi_tx(struct
> drm_i915_private *dev_priv,
> enum pipe pipe, bool state)
> {
> bool cur_state;
> - enum transcoder cpu_transcoder =
> intel_pipe_to_cpu_transcoder(dev_priv,
> - p
> ipe);
>
> if (HAS_DDI(dev_priv)) {
> - /* DDI does not have a specific FDI_TX register */
> + /*
> + * DDI does not have a specific FDI_TX register.
> + *
> + * FDI is never hooked fed from EDP transcoder
> + * so pipe->transcoder cast is fine here.
> + */
> + enum transcoder cpu_transcoder = (enum transcoder)pipe;
> u32 val =
> I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
> } else {
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Pass cpu transcoder to assert_pipe()
2019-11-12 16:38 ` [Intel-gfx] " Ville Syrjala
(?)
@ 2019-12-10 18:23 ` Souza, Jose
2019-12-10 19:58 ` Ville Syrjälä
-1 siblings, 1 reply; 22+ messages in thread
From: Souza, Jose @ 2019-12-10 18:23 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Tue, 2019-11-12 at 18:38 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In order to eliminate intel_pipe_to_cpu_transcoder() (and its
> crtc->config usage) let's pass the cpu transcoder to
> assert_pipe() so we don't have to do the pipe->cpu transcoder
> lookup on HSW+.
>
> On VLV/CHV this can get called during eDP init, which
> happens before crtc->config->cpu_transcoder is even
> populated. So currently we're always reading PIPECONF(A)
> there even if we're trying to check the state of some
> other pipe.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++--------
> ----
> drivers/gpu/drm/i915/display/intel_display.h | 9 +++--
> 2 files changed, 18 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index cabd88337822..6d2112f5bdd0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1040,14 +1040,6 @@ bool bxt_find_best_dpll(struct
> intel_crtc_state *crtc_state,
> NULL, best_clock);
> }
>
> -enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private
> *dev_priv,
> - enum pipe pipe)
> -{
> - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
> pipe);
> -
> - return crtc->config->cpu_transcoder;
> -}
> -
> static bool pipe_scanline_is_moving(struct drm_i915_private
> *dev_priv,
> enum pipe pipe)
> {
> @@ -1266,11 +1258,9 @@ void assert_panel_unlocked(struct
> drm_i915_private *dev_priv, enum pipe pipe)
> }
>
> void assert_pipe(struct drm_i915_private *dev_priv,
> - enum pipe pipe, bool state)
> + enum transcoder cpu_transcoder, bool state)
> {
> bool cur_state;
> - enum transcoder cpu_transcoder =
> intel_pipe_to_cpu_transcoder(dev_priv,
> - p
> ipe);
> enum intel_display_power_domain power_domain;
> intel_wakeref_t wakeref;
>
> @@ -1290,8 +1280,9 @@ void assert_pipe(struct drm_i915_private
> *dev_priv,
> }
>
> I915_STATE_WARN(cur_state != state,
> - "pipe %c assertion failure (expected %s, current %s)\n",
> - pipe_name(pipe), onoff(state),
> onoff(cur_state));
> + "transcoder %s assertion failure (expected %s,
> current %s)\n",
> + transcoder_name(cpu_transcoder),
> + onoff(state), onoff(cur_state));
> }
>
> static void assert_plane(struct intel_plane *plane, bool state)
> @@ -1418,7 +1409,7 @@ static void vlv_enable_pll(struct intel_crtc
> *crtc,
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> - assert_pipe_disabled(dev_priv, pipe);
> + assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
>
> /* PLL is protected by panel, make sure we can write it */
> assert_panel_unlocked(dev_priv, pipe);
> @@ -1467,7 +1458,7 @@ static void chv_enable_pll(struct intel_crtc
> *crtc,
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> - assert_pipe_disabled(dev_priv, pipe);
> + assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
>
> /* PLL is protected by panel, make sure we can write it */
> assert_panel_unlocked(dev_priv, pipe);
> @@ -1514,7 +1505,7 @@ static void i9xx_enable_pll(struct intel_crtc
> *crtc,
> u32 dpll = crtc_state->dpll_hw_state.dpll;
> int i;
>
> - assert_pipe_disabled(dev_priv, crtc->pipe);
> + assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
>
> /* PLL is protected by panel, make sure we can write it */
> if (i9xx_has_pps(dev_priv))
> @@ -1563,7 +1554,7 @@ static void i9xx_disable_pll(const struct
> intel_crtc_state *crtc_state)
> return;
>
> /* Make sure the pipe isn't still relying on us */
> - assert_pipe_disabled(dev_priv, pipe);
> + assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
>
> I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
> POSTING_READ(DPLL(pipe));
> @@ -1574,7 +1565,7 @@ static void vlv_disable_pll(struct
> drm_i915_private *dev_priv, enum pipe pipe)
> u32 val;
>
> /* Make sure the pipe isn't still relying on us */
> - assert_pipe_disabled(dev_priv, pipe);
> + assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
>
> val = DPLL_INTEGRATED_REF_CLK_VLV |
> DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> @@ -1591,7 +1582,7 @@ static void chv_disable_pll(struct
> drm_i915_private *dev_priv, enum pipe pipe)
> u32 val;
>
> /* Make sure the pipe isn't still relying on us */
> - assert_pipe_disabled(dev_priv, pipe);
> + assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
>
> val = DPLL_SSC_REF_CLK_CHV |
> DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> @@ -4617,7 +4608,7 @@ static void ironlake_fdi_link_train(struct
> intel_crtc *crtc,
> u32 temp, tries;
>
> /* FDI needs bits from pipe first */
> - assert_pipe_enabled(dev_priv, pipe);
> + assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
>
> /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
> for train result */
> @@ -6805,7 +6796,7 @@ static void i9xx_pfit_enable(const struct
> intel_crtc_state *crtc_state)
> * according to register description and PRM.
> */
> WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
> - assert_pipe_disabled(dev_priv, crtc->pipe);
> + assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
>
> I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
> I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
> @@ -7116,7 +7107,7 @@ static void i9xx_pfit_disable(const struct
> intel_crtc_state *old_crtc_state)
> if (!old_crtc_state->gmch_pfit.control)
> return;
>
> - assert_pipe_disabled(dev_priv, crtc->pipe);
> + assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
>
> DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
> I915_READ(PFIT_CONTROL));
> @@ -8128,6 +8119,7 @@ int vlv_force_pll_on(struct drm_i915_private
> *dev_priv, enum pipe pipe,
> return -ENOMEM;
>
> pipe_config->uapi.crtc = &crtc->base;
> + pipe_config->cpu_transcoder = (enum transcoder)pipe;
> pipe_config->pixel_multiplier = 1;
> pipe_config->dpll = *dpll;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index d18dc260fe83..f33096876a9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -510,8 +510,6 @@ enum tc_port intel_port_to_tc(struct
> drm_i915_private *dev_priv,
> enum port port);
> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void
> *data,
> struct drm_file *file_priv);
> -enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private
> *dev_priv,
> - enum pipe pipe);
> u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
>
> int ironlake_get_lanes_required(int target_clock, int link_bw, int
> bpp);
> @@ -613,9 +611,10 @@ void assert_fdi_rx_pll(struct drm_i915_private
> *dev_priv,
> enum pipe pipe, bool state);
> #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p,
> true)
> #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p,
> false)
> -void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> bool state);
> -#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
> -#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> +void assert_pipe(struct drm_i915_private *dev_priv,
> + enum transcoder cpu_transcoder, bool state);
> +#define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
> +#define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
Maybe while doing all those already rename it to
assert_transcoder_enabled/disabled()?
Also why not just squash with the previous patch?
Other than that:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than
> WARN() and
> * WARN_ON()) for hw state sanity checks to check for unexpected
> conditions
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx()
2019-12-10 18:19 ` Souza, Jose
@ 2019-12-10 19:55 ` Ville Syrjälä
2019-12-10 20:10 ` Souza, Jose
0 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjälä @ 2019-12-10 19:55 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Tue, Dec 10, 2019 at 06:19:24PM +0000, Souza, Jose wrote:
> On Tue, 2019-11-12 at 18:38 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Let's start to eliminate intel_pipe_to_cpu_transcoder() so that
> > we can get rid of one more crtc->config usage (which we will want
> > to nuke as well).
> >
> > In the case of assert_fdi_tx() we know that we're never
> > dealing with the EDP transcoder so we can simply replace
> > this with a cast.
>
> There still one EDP transcoder case when running in a HSW:
>
> haswell_crtc_enable()
> lpt_pch_enable()
> lpt_enable_pch_transcoder()
> assert_fdi_tx_enabled()
The transcoder will never EDP. But this casting back and forth
is a bit ugly. Maybe I should just kill these FDI TX asserts
from the hsw/bdw code...
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 10 +++++++---
> > 1 file changed, 7 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index e7e5497e6f2e..cabd88337822 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1141,11 +1141,15 @@ static void assert_fdi_tx(struct
> > drm_i915_private *dev_priv,
> > enum pipe pipe, bool state)
> > {
> > bool cur_state;
> > - enum transcoder cpu_transcoder =
> > intel_pipe_to_cpu_transcoder(dev_priv,
> > - p
> > ipe);
> >
> > if (HAS_DDI(dev_priv)) {
> > - /* DDI does not have a specific FDI_TX register */
> > + /*
> > + * DDI does not have a specific FDI_TX register.
> > + *
> > + * FDI is never hooked fed from EDP transcoder
> > + * so pipe->transcoder cast is fine here.
> > + */
> > + enum transcoder cpu_transcoder = (enum transcoder)pipe;
> > u32 val =
> > I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
> > } else {
--
Ville Syrjälä
Intel
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Pass cpu transcoder to assert_pipe()
2019-12-10 18:23 ` Souza, Jose
@ 2019-12-10 19:58 ` Ville Syrjälä
2019-12-10 20:14 ` Souza, Jose
0 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjälä @ 2019-12-10 19:58 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Tue, Dec 10, 2019 at 06:23:36PM +0000, Souza, Jose wrote:
> On Tue, 2019-11-12 at 18:38 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > In order to eliminate intel_pipe_to_cpu_transcoder() (and its
> > crtc->config usage) let's pass the cpu transcoder to
> > assert_pipe() so we don't have to do the pipe->cpu transcoder
> > lookup on HSW+.
> >
> > On VLV/CHV this can get called during eDP init, which
> > happens before crtc->config->cpu_transcoder is even
> > populated. So currently we're always reading PIPECONF(A)
> > there even if we're trying to check the state of some
> > other pipe.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++--------
> > ----
> > drivers/gpu/drm/i915/display/intel_display.h | 9 +++--
> > 2 files changed, 18 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index cabd88337822..6d2112f5bdd0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1040,14 +1040,6 @@ bool bxt_find_best_dpll(struct
> > intel_crtc_state *crtc_state,
> > NULL, best_clock);
> > }
> >
> > -enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private
> > *dev_priv,
> > - enum pipe pipe)
> > -{
> > - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
> > pipe);
> > -
> > - return crtc->config->cpu_transcoder;
> > -}
> > -
> > static bool pipe_scanline_is_moving(struct drm_i915_private
> > *dev_priv,
> > enum pipe pipe)
> > {
> > @@ -1266,11 +1258,9 @@ void assert_panel_unlocked(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > }
> >
> > void assert_pipe(struct drm_i915_private *dev_priv,
> > - enum pipe pipe, bool state)
> > + enum transcoder cpu_transcoder, bool state)
> > {
> > bool cur_state;
> > - enum transcoder cpu_transcoder =
> > intel_pipe_to_cpu_transcoder(dev_priv,
> > - p
> > ipe);
> > enum intel_display_power_domain power_domain;
> > intel_wakeref_t wakeref;
> >
> > @@ -1290,8 +1280,9 @@ void assert_pipe(struct drm_i915_private
> > *dev_priv,
> > }
> >
> > I915_STATE_WARN(cur_state != state,
> > - "pipe %c assertion failure (expected %s, current %s)\n",
> > - pipe_name(pipe), onoff(state),
> > onoff(cur_state));
> > + "transcoder %s assertion failure (expected %s,
> > current %s)\n",
> > + transcoder_name(cpu_transcoder),
> > + onoff(state), onoff(cur_state));
> > }
> >
> > static void assert_plane(struct intel_plane *plane, bool state)
> > @@ -1418,7 +1409,7 @@ static void vlv_enable_pll(struct intel_crtc
> > *crtc,
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe;
> >
> > - assert_pipe_disabled(dev_priv, pipe);
> > + assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
> >
> > /* PLL is protected by panel, make sure we can write it */
> > assert_panel_unlocked(dev_priv, pipe);
> > @@ -1467,7 +1458,7 @@ static void chv_enable_pll(struct intel_crtc
> > *crtc,
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe;
> >
> > - assert_pipe_disabled(dev_priv, pipe);
> > + assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
> >
> > /* PLL is protected by panel, make sure we can write it */
> > assert_panel_unlocked(dev_priv, pipe);
> > @@ -1514,7 +1505,7 @@ static void i9xx_enable_pll(struct intel_crtc
> > *crtc,
> > u32 dpll = crtc_state->dpll_hw_state.dpll;
> > int i;
> >
> > - assert_pipe_disabled(dev_priv, crtc->pipe);
> > + assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
> >
> > /* PLL is protected by panel, make sure we can write it */
> > if (i9xx_has_pps(dev_priv))
> > @@ -1563,7 +1554,7 @@ static void i9xx_disable_pll(const struct
> > intel_crtc_state *crtc_state)
> > return;
> >
> > /* Make sure the pipe isn't still relying on us */
> > - assert_pipe_disabled(dev_priv, pipe);
> > + assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
> >
> > I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
> > POSTING_READ(DPLL(pipe));
> > @@ -1574,7 +1565,7 @@ static void vlv_disable_pll(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > u32 val;
> >
> > /* Make sure the pipe isn't still relying on us */
> > - assert_pipe_disabled(dev_priv, pipe);
> > + assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
> >
> > val = DPLL_INTEGRATED_REF_CLK_VLV |
> > DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> > @@ -1591,7 +1582,7 @@ static void chv_disable_pll(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > u32 val;
> >
> > /* Make sure the pipe isn't still relying on us */
> > - assert_pipe_disabled(dev_priv, pipe);
> > + assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
> >
> > val = DPLL_SSC_REF_CLK_CHV |
> > DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> > @@ -4617,7 +4608,7 @@ static void ironlake_fdi_link_train(struct
> > intel_crtc *crtc,
> > u32 temp, tries;
> >
> > /* FDI needs bits from pipe first */
> > - assert_pipe_enabled(dev_priv, pipe);
> > + assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
> >
> > /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
> > for train result */
> > @@ -6805,7 +6796,7 @@ static void i9xx_pfit_enable(const struct
> > intel_crtc_state *crtc_state)
> > * according to register description and PRM.
> > */
> > WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
> > - assert_pipe_disabled(dev_priv, crtc->pipe);
> > + assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
> >
> > I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
> > I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
> > @@ -7116,7 +7107,7 @@ static void i9xx_pfit_disable(const struct
> > intel_crtc_state *old_crtc_state)
> > if (!old_crtc_state->gmch_pfit.control)
> > return;
> >
> > - assert_pipe_disabled(dev_priv, crtc->pipe);
> > + assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
> >
> > DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
> > I915_READ(PFIT_CONTROL));
> > @@ -8128,6 +8119,7 @@ int vlv_force_pll_on(struct drm_i915_private
> > *dev_priv, enum pipe pipe,
> > return -ENOMEM;
> >
> > pipe_config->uapi.crtc = &crtc->base;
> > + pipe_config->cpu_transcoder = (enum transcoder)pipe;
> > pipe_config->pixel_multiplier = 1;
> > pipe_config->dpll = *dpll;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> > b/drivers/gpu/drm/i915/display/intel_display.h
> > index d18dc260fe83..f33096876a9a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -510,8 +510,6 @@ enum tc_port intel_port_to_tc(struct
> > drm_i915_private *dev_priv,
> > enum port port);
> > int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void
> > *data,
> > struct drm_file *file_priv);
> > -enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private
> > *dev_priv,
> > - enum pipe pipe);
> > u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
> >
> > int ironlake_get_lanes_required(int target_clock, int link_bw, int
> > bpp);
> > @@ -613,9 +611,10 @@ void assert_fdi_rx_pll(struct drm_i915_private
> > *dev_priv,
> > enum pipe pipe, bool state);
> > #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p,
> > true)
> > #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p,
> > false)
> > -void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> > bool state);
> > -#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
> > -#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> > +void assert_pipe(struct drm_i915_private *dev_priv,
> > + enum transcoder cpu_transcoder, bool state);
> > +#define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
> > +#define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
>
> Maybe while doing all those already rename it to
> assert_transcoder_enabled/disabled()?
Perhaps. Although then it's inconsistent with
intel_{enable,disable}_pipe() so should maybe rename those
as well. I think I'll leave all that for another day.
>
> Also why not just squash with the previous patch?
Why? The two patches are touching two totally different things.
>
> Other than that:
>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> >
> > /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than
> > WARN() and
> > * WARN_ON()) for hw state sanity checks to check for unexpected
> > conditions
--
Ville Syrjälä
Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx()
2019-12-10 19:55 ` Ville Syrjälä
@ 2019-12-10 20:10 ` Souza, Jose
0 siblings, 0 replies; 22+ messages in thread
From: Souza, Jose @ 2019-12-10 20:10 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Tue, 2019-12-10 at 21:55 +0200, Ville Syrjälä wrote:
> On Tue, Dec 10, 2019 at 06:19:24PM +0000, Souza, Jose wrote:
> > On Tue, 2019-11-12 at 18:38 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Let's start to eliminate intel_pipe_to_cpu_transcoder() so that
> > > we can get rid of one more crtc->config usage (which we will want
> > > to nuke as well).
> > >
> > > In the case of assert_fdi_tx() we know that we're never
> > > dealing with the EDP transcoder so we can simply replace
> > > this with a cast.
> >
> > There still one EDP transcoder case when running in a HSW:
> >
> > haswell_crtc_enable()
> > lpt_pch_enable()
> > lpt_enable_pch_transcoder()
> > assert_fdi_tx_enabled()
>
> The transcoder will never EDP. But this casting back and forth
> is a bit ugly. Maybe I should just kill these FDI TX asserts
> from the hsw/bdw code...
Oh misread crt with crtc, so has_pch_encoder will not be set for edp.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 10 +++++++---
> > > 1 file changed, 7 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index e7e5497e6f2e..cabd88337822 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -1141,11 +1141,15 @@ static void assert_fdi_tx(struct
> > > drm_i915_private *dev_priv,
> > > enum pipe pipe, bool state)
> > > {
> > > bool cur_state;
> > > - enum transcoder cpu_transcoder =
> > > intel_pipe_to_cpu_transcoder(dev_priv,
> > > - p
> > > ipe);
> > >
> > > if (HAS_DDI(dev_priv)) {
> > > - /* DDI does not have a specific FDI_TX register */
> > > + /*
> > > + * DDI does not have a specific FDI_TX register.
> > > + *
> > > + * FDI is never hooked fed from EDP transcoder
> > > + * so pipe->transcoder cast is fine here.
> > > + */
> > > + enum transcoder cpu_transcoder = (enum transcoder)pipe;
> > > u32 val =
> > > I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > > cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
> > > } else {
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Pass cpu transcoder to assert_pipe()
2019-12-10 19:58 ` Ville Syrjälä
@ 2019-12-10 20:14 ` Souza, Jose
0 siblings, 0 replies; 22+ messages in thread
From: Souza, Jose @ 2019-12-10 20:14 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Tue, 2019-12-10 at 21:58 +0200, Ville Syrjälä wrote:
> On Tue, Dec 10, 2019 at 06:23:36PM +0000, Souza, Jose wrote:
> > On Tue, 2019-11-12 at 18:38 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > In order to eliminate intel_pipe_to_cpu_transcoder() (and its
> > > crtc->config usage) let's pass the cpu transcoder to
> > > assert_pipe() so we don't have to do the pipe->cpu transcoder
> > > lookup on HSW+.
> > >
> > > On VLV/CHV this can get called during eDP init, which
> > > happens before crtc->config->cpu_transcoder is even
> > > populated. So currently we're always reading PIPECONF(A)
> > > there even if we're trying to check the state of some
> > > other pipe.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++----
> > > ----
> > > ----
> > > drivers/gpu/drm/i915/display/intel_display.h | 9 +++--
> > > 2 files changed, 18 insertions(+), 27 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index cabd88337822..6d2112f5bdd0 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -1040,14 +1040,6 @@ bool bxt_find_best_dpll(struct
> > > intel_crtc_state *crtc_state,
> > > NULL, best_clock);
> > > }
> > >
> > > -enum transcoder intel_pipe_to_cpu_transcoder(struct
> > > drm_i915_private
> > > *dev_priv,
> > > - enum pipe pipe)
> > > -{
> > > - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
> > > pipe);
> > > -
> > > - return crtc->config->cpu_transcoder;
> > > -}
> > > -
> > > static bool pipe_scanline_is_moving(struct drm_i915_private
> > > *dev_priv,
> > > enum pipe pipe)
> > > {
> > > @@ -1266,11 +1258,9 @@ void assert_panel_unlocked(struct
> > > drm_i915_private *dev_priv, enum pipe pipe)
> > > }
> > >
> > > void assert_pipe(struct drm_i915_private *dev_priv,
> > > - enum pipe pipe, bool state)
> > > + enum transcoder cpu_transcoder, bool state)
> > > {
> > > bool cur_state;
> > > - enum transcoder cpu_transcoder =
> > > intel_pipe_to_cpu_transcoder(dev_priv,
> > > - p
> > > ipe);
> > > enum intel_display_power_domain power_domain;
> > > intel_wakeref_t wakeref;
> > >
> > > @@ -1290,8 +1280,9 @@ void assert_pipe(struct drm_i915_private
> > > *dev_priv,
> > > }
> > >
> > > I915_STATE_WARN(cur_state != state,
> > > - "pipe %c assertion failure (expected %s, current %s)\n",
> > > - pipe_name(pipe), onoff(state),
> > > onoff(cur_state));
> > > + "transcoder %s assertion failure (expected %s,
> > > current %s)\n",
> > > + transcoder_name(cpu_transcoder),
> > > + onoff(state), onoff(cur_state));
> > > }
> > >
> > > static void assert_plane(struct intel_plane *plane, bool state)
> > > @@ -1418,7 +1409,7 @@ static void vlv_enable_pll(struct
> > > intel_crtc
> > > *crtc,
> > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > enum pipe pipe = crtc->pipe;
> > >
> > > - assert_pipe_disabled(dev_priv, pipe);
> > > + assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
> > >
> > > /* PLL is protected by panel, make sure we can write it */
> > > assert_panel_unlocked(dev_priv, pipe);
> > > @@ -1467,7 +1458,7 @@ static void chv_enable_pll(struct
> > > intel_crtc
> > > *crtc,
> > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > enum pipe pipe = crtc->pipe;
> > >
> > > - assert_pipe_disabled(dev_priv, pipe);
> > > + assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
> > >
> > > /* PLL is protected by panel, make sure we can write it */
> > > assert_panel_unlocked(dev_priv, pipe);
> > > @@ -1514,7 +1505,7 @@ static void i9xx_enable_pll(struct
> > > intel_crtc
> > > *crtc,
> > > u32 dpll = crtc_state->dpll_hw_state.dpll;
> > > int i;
> > >
> > > - assert_pipe_disabled(dev_priv, crtc->pipe);
> > > + assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
> > >
> > > /* PLL is protected by panel, make sure we can write it */
> > > if (i9xx_has_pps(dev_priv))
> > > @@ -1563,7 +1554,7 @@ static void i9xx_disable_pll(const struct
> > > intel_crtc_state *crtc_state)
> > > return;
> > >
> > > /* Make sure the pipe isn't still relying on us */
> > > - assert_pipe_disabled(dev_priv, pipe);
> > > + assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
> > >
> > > I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
> > > POSTING_READ(DPLL(pipe));
> > > @@ -1574,7 +1565,7 @@ static void vlv_disable_pll(struct
> > > drm_i915_private *dev_priv, enum pipe pipe)
> > > u32 val;
> > >
> > > /* Make sure the pipe isn't still relying on us */
> > > - assert_pipe_disabled(dev_priv, pipe);
> > > + assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
> > >
> > > val = DPLL_INTEGRATED_REF_CLK_VLV |
> > > DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> > > @@ -1591,7 +1582,7 @@ static void chv_disable_pll(struct
> > > drm_i915_private *dev_priv, enum pipe pipe)
> > > u32 val;
> > >
> > > /* Make sure the pipe isn't still relying on us */
> > > - assert_pipe_disabled(dev_priv, pipe);
> > > + assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
> > >
> > > val = DPLL_SSC_REF_CLK_CHV |
> > > DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> > > @@ -4617,7 +4608,7 @@ static void ironlake_fdi_link_train(struct
> > > intel_crtc *crtc,
> > > u32 temp, tries;
> > >
> > > /* FDI needs bits from pipe first */
> > > - assert_pipe_enabled(dev_priv, pipe);
> > > + assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
> > >
> > > /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
> > > for train result */
> > > @@ -6805,7 +6796,7 @@ static void i9xx_pfit_enable(const struct
> > > intel_crtc_state *crtc_state)
> > > * according to register description and PRM.
> > > */
> > > WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
> > > - assert_pipe_disabled(dev_priv, crtc->pipe);
> > > + assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
> > >
> > > I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
> > > I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
> > > @@ -7116,7 +7107,7 @@ static void i9xx_pfit_disable(const struct
> > > intel_crtc_state *old_crtc_state)
> > > if (!old_crtc_state->gmch_pfit.control)
> > > return;
> > >
> > > - assert_pipe_disabled(dev_priv, crtc->pipe);
> > > + assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
> > >
> > > DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
> > > I915_READ(PFIT_CONTROL));
> > > @@ -8128,6 +8119,7 @@ int vlv_force_pll_on(struct
> > > drm_i915_private
> > > *dev_priv, enum pipe pipe,
> > > return -ENOMEM;
> > >
> > > pipe_config->uapi.crtc = &crtc->base;
> > > + pipe_config->cpu_transcoder = (enum transcoder)pipe;
> > > pipe_config->pixel_multiplier = 1;
> > > pipe_config->dpll = *dpll;
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> > > b/drivers/gpu/drm/i915/display/intel_display.h
> > > index d18dc260fe83..f33096876a9a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > > @@ -510,8 +510,6 @@ enum tc_port intel_port_to_tc(struct
> > > drm_i915_private *dev_priv,
> > > enum port port);
> > > int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev,
> > > void
> > > *data,
> > > struct drm_file *file_priv);
> > > -enum transcoder intel_pipe_to_cpu_transcoder(struct
> > > drm_i915_private
> > > *dev_priv,
> > > - enum pipe pipe);
> > > u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
> > >
> > > int ironlake_get_lanes_required(int target_clock, int link_bw,
> > > int
> > > bpp);
> > > @@ -613,9 +611,10 @@ void assert_fdi_rx_pll(struct
> > > drm_i915_private
> > > *dev_priv,
> > > enum pipe pipe, bool state);
> > > #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p,
> > > true)
> > > #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p,
> > > false)
> > > -void assert_pipe(struct drm_i915_private *dev_priv, enum pipe
> > > pipe,
> > > bool state);
> > > -#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
> > > -#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> > > +void assert_pipe(struct drm_i915_private *dev_priv,
> > > + enum transcoder cpu_transcoder, bool state);
> > > +#define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
> > > +#define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
> >
> > Maybe while doing all those already rename it to
> > assert_transcoder_enabled/disabled()?
>
> Perhaps. Although then it's inconsistent with
> intel_{enable,disable}_pipe() so should maybe rename those
> as well. I think I'll leave all that for another day.
Okay
>
> > Also why not just squash with the previous patch?
>
> Why? The two patches are touching two totally different things.
Both are getting rid of intel_pipe_to_cpu_transcoder()...
Anyways now that I'm sure the previous one is not wrong for HSW both
looks good.
>
> > Other than that:
> >
> > Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> >
> > >
> > > /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than
> > > WARN() and
> > > * WARN_ON()) for hw state sanity checks to check for unexpected
> > > conditions
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^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2019-12-10 20:14 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-12 16:38 [PATCH 1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction Ville Syrjala
2019-11-12 16:38 ` [Intel-gfx] " Ville Syrjala
2019-11-12 16:38 ` [PATCH 2/4] drm/i915: Relocate intel_crtc_active() Ville Syrjala
2019-11-12 16:38 ` [Intel-gfx] " Ville Syrjala
2019-11-13 6:29 ` Lucas De Marchi
2019-11-13 6:29 ` [Intel-gfx] " Lucas De Marchi
2019-11-12 16:38 ` [PATCH 3/4] drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx() Ville Syrjala
2019-11-12 16:38 ` [Intel-gfx] " Ville Syrjala
2019-12-10 18:19 ` Souza, Jose
2019-12-10 19:55 ` Ville Syrjälä
2019-12-10 20:10 ` Souza, Jose
2019-11-12 16:38 ` [PATCH 4/4] drm/i915: Pass cpu transcoder to assert_pipe() Ville Syrjala
2019-11-12 16:38 ` [Intel-gfx] " Ville Syrjala
2019-12-10 18:23 ` Souza, Jose
2019-12-10 19:58 ` Ville Syrjälä
2019-12-10 20:14 ` Souza, Jose
2019-11-12 21:45 ` ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/fbc: Nuke bogus single pipe fbc1 restriction Patchwork
2019-11-12 21:45 ` [Intel-gfx] " Patchwork
2019-11-12 22:17 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-12 22:17 ` [Intel-gfx] " Patchwork
2019-11-13 10:24 ` ✓ Fi.CI.IGT: " Patchwork
2019-11-13 10:24 ` [Intel-gfx] " Patchwork
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