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+ int i; + + for (i = 0; i < 100; i++) { + x = 0; + /* + * The value before the transaction is important, so make the + * operand input/output. + */ + asm volatile("xbegin 2f; movb $1, %0; xend; 2:" : "+m" (x) : : "eax"); + if (x) { + return true; + } + } + return false; +} + +int main(int ac, char **av) +{ + if (!this_cpu_has(X86_FEATURE_RTM)) { + report_skip("TSX not available"); + return 0; + } + if (!this_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { + report_skip("ARCH_CAPABILITIES not available"); + return 0; + } + if (!(rdmsr(MSR_IA32_ARCH_CAPABILITIES) & ARCH_CAP_TSX_CTRL_MSR)) { + report_skip("TSX_CTRL not available"); + return 0; + } + + report("TSX_CTRL should be 0", rdmsr(MSR_IA32_TSX_CTRL) == 0); + report("Transactions do not abort", try_transaction()); + + wrmsr(MSR_IA32_TSX_CTRL, TSX_CTRL_CPUID_CLEAR); + report("TSX_CTRL hides RTM", !this_cpu_has(X86_FEATURE_RTM)); + report("TSX_CTRL hides HLE", !this_cpu_has(X86_FEATURE_HLE)); + + /* Microcode might hide HLE unconditionally */ + wrmsr(MSR_IA32_TSX_CTRL, 0); + report("TSX_CTRL=0 unhides RTM", this_cpu_has(X86_FEATURE_RTM)); + + wrmsr(MSR_IA32_TSX_CTRL, TSX_CTRL_RTM_DISABLE); + report("TSX_CTRL causes transactions to abort", !try_transaction()); + + wrmsr(MSR_IA32_TSX_CTRL, 0); + report("TSX_CTRL=0 causes transactions to succeed", try_transaction()); + + return report_summary(); +} + diff --git a/x86/vmexit.c b/x86/vmexit.c index 81b743b..acdcbdc 100644 --- a/x86/vmexit.c +++ b/x86/vmexit.c @@ -434,6 +434,17 @@ static void tscdeadline(void) while (x == 0) barrier(); } +static void wr_tsx_ctrl_msr(void) +{ + wrmsr(MSR_IA32_TSX_CTRL, 0); +} + +static int has_tsx_ctrl(void) +{ + return this_cpu_has(X86_FEATURE_ARCH_CAPABILITIES) + && (rdmsr(MSR_IA32_ARCH_CAPABILITIES) & ARCH_CAP_TSX_CTRL_MSR); +} + static void wr_ibrs_msr(void) { wrmsr(MSR_IA32_SPEC_CTRL, 1); @@ -478,6 +489,7 @@ static struct test tests[] = { { ipi_halt, "ipi_halt", is_smp, .parallel = 0, }, { ple_round_robin, "ple_round_robin", .parallel = 1 }, { wr_kernel_gs_base, "wr_kernel_gs_base", .parallel = 1 }, + { wr_tsx_ctrl_msr, "wr_tsx_ctrl_msr", has_tsx_ctrl, .parallel = 1, }, { wr_ibrs_msr, "wr_ibrs_msr", has_spec_ctrl, .parallel = 1 }, { wr_ibpb_msr, "wr_ibpb_msr", has_ibpb, .parallel = 1 }, { wr_tsc_adjust_msr, "wr_tsc_adjust_msr", .parallel = 1 }, -- 1.8.3.1