From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DE04C432C0 for ; Fri, 29 Nov 2019 19:29:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EC57A20869 for ; Fri, 29 Nov 2019 19:29:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="O9gNjYxO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727139AbfK2T3S (ORCPT ); Fri, 29 Nov 2019 14:29:18 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:29186 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726926AbfK2T3S (ORCPT ); Fri, 29 Nov 2019 14:29:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575055756; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=A1Y9WHtaAY4UzSoPOoSv2m/ifwl+YEceF+RKR3CTCTk=; b=O9gNjYxOUQ12tnh1P0LHg/Erwx0svVyadT/hVz8Bp8+G768XlqqOut7i0mYJLPdG/nZU1o joxvHRoiVnxylAXa3KmUCvvgCXg2OEfUw/GFYcSeEfyFBSf5e26vanUGbtwnwmDGc+CZZx n0R4SIl0GxPYSKxJYJbuBn0hyEaWF1c= Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-315-srfpYF2yOWyKf07-Mzj33A-1; Fri, 29 Nov 2019 14:29:14 -0500 Received: by mail-pl1-f200.google.com with SMTP id x9so13220116plv.2 for ; Fri, 29 Nov 2019 11:29:13 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=+RGhDPWZi/m+uC+dFG9W5dCj6ubdgxgz1OjCUZFmMIs=; b=QeQu0HJr+BnhSVlLSItKRLz8Y367lya7myqL813Do6YV/uKrwIybPhv04yvqxKD3eT em94Vm/EyP/byyhdOaQ3TKLzd/M3qiF8SB8lfQXa2ScKyhnR/x1s0bTdyC4RQi/ROSTJ 2YPFxpdJ9EMWJ3378YQAqcr6ZGFHXqnF36NEVrH68KxCSmfPLwhS3WkA0qJ2k8WsSZgY FUyv8J8E3fP02hS+mrhbpu0F/zjGFRPeL1kiEp7nDIWBFwarj7GcNppTC8C+FsDcri+M XL8imZeog5ndVZJgZWGwzox4uq34DLi7UrQ2nW9TTWA50hgjeYmxNhFQiiryTRy01BdE PH7g== X-Gm-Message-State: APjAAAVo1BI2rWtlJSZBA7zubs6Kd4cpBzCe83WdIfP4LGEcOBA2jM81 CjPgz7vZO8ZhBYgcGGQJFCEaN2oKbp1NzuMm2bmyWC4AFBCanfBEfahhRrP8FOp9wu4dXalew3s 08iIU8bN9aa49JVfEzPVzBEJT X-Received: by 2002:a17:90a:b38c:: with SMTP id e12mr20373963pjr.89.1575055752564; Fri, 29 Nov 2019 11:29:12 -0800 (PST) X-Google-Smtp-Source: APXvYqxbsJq68B0VFjsjCP+XCq0F6XFF9siQwhdXf0KacvnZ7i830WNBU2oxnas4e3iBnGfWl5c1rw== X-Received: by 2002:a17:90a:b38c:: with SMTP id e12mr20373930pjr.89.1575055752286; Fri, 29 Nov 2019 11:29:12 -0800 (PST) Received: from localhost ([122.177.85.74]) by smtp.gmail.com with ESMTPSA id k10sm14560656pjs.31.2019.11.29.11.29.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 29 Nov 2019 11:29:11 -0800 (PST) From: Bhupesh Sharma To: linux-kernel@vger.kernel.org Cc: bhsharma@redhat.com, bhupesh.linux@gmail.com, x86@kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kexec@lists.infradead.org, Boris Petkov , Ingo Molnar , Thomas Gleixner , Jonathan Corbet , James Morse , Mark Rutland , Will Deacon , Steve Capper , Catalin Marinas , Ard Biesheuvel , Michael Ellerman , Paul Mackerras , Benjamin Herrenschmidt , Dave Anderson , Kazuhito Hagio Subject: [RESEND PATCH v5 0/5] Append new variables to vmcoreinfo (TCR_EL1.T1SZ for arm64 and MAX_PHYSMEM_BITS for all archs) Date: Sat, 30 Nov 2019 00:58:41 +0530 Message-Id: <1575055726-23464-1-git-send-email-bhsharma@redhat.com> X-Mailer: git-send-email 2.7.4 X-MC-Unique: srfpYF2yOWyKf07-Mzj33A-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org - Resending the v5 version as Will Deacon reported that the patchset was split into two seperate threads while sending out. It was an issue with my 'msmtp' settings which is now fixed. Changes since v4: ---------------- - v4 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-November/023961.html - Addressed comments from Dave and added patches for documenting new variables appended to vmcoreinfo documentation. - Added testing report shared by Akashi for PATCH 2/5. Changes since v3: ---------------- - v3 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-March/022590.html - Addressed comments from James and exported TCR_EL1.T1SZ in vmcoreinfo instead of PTRS_PER_PGD. - Added a new patch (via [PATCH 3/3]), which fixes a simple typo in 'Documentation/arm64/memory.rst' Changes since v2: ---------------- - v2 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-March/022531.html - Protected 'MAX_PHYSMEM_BITS' vmcoreinfo variable under CONFIG_SPARSEMEM ifdef sections, as suggested by Kazu. - Updated vmcoreinfo documentation to add description about 'MAX_PHYSMEM_BITS' variable (via [PATCH 3/3]). Changes since v1: ---------------- - v1 was sent out as a single patch which can be seen here: http://lists.infradead.org/pipermail/kexec/2019-February/022411.html - v2 breaks the single patch into two independent patches: [PATCH 1/2] appends 'PTRS_PER_PGD' to vmcoreinfo for arm64 arch, whereas [PATCH 2/2] appends 'MAX_PHYSMEM_BITS' to vmcoreinfo in core kernel code = (all archs) This patchset primarily fixes the regression reported in user-space utilities like 'makedumpfile' and 'crash-utility' on arm64 architecture with the availability of 52-bit address space feature in underlying kernel. These regressions have been reported both on CPUs which don't support ARMv8.2 extensions (i.e. LVA, LPA) and are running newer kernels and also on prototype platforms (like ARMv8 FVP simulator model) which support ARMv8.2 extensions and are running newer kernels. The reason for these regressions is that right now user-space tools have no direct access to these values (since these are not exported from the kernel) and hence need to rely on a best-guess method of determining value of 'vabits_actual' and 'MAX_PHYSMEM_BITS' supported by underlying kernel. Exporting these values via vmcoreinfo will help user-land in such cases. In addition, as per suggestion from makedumpfile maintainer (Kazu), it makes more sense to append 'MAX_PHYSMEM_BITS' to vmcoreinfo in the core code itself rather than in arm64 arch-specific code, so that the user-space code for other archs can also benefit from this addition to the vmcoreinfo and use it as a standard way of determining 'SECTIONS_SHIFT' value in user-land. Cc: Boris Petkov Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Jonathan Corbet Cc: James Morse Cc: Mark Rutland Cc: Will Deacon Cc: Steve Capper Cc: Catalin Marinas Cc: Ard Biesheuvel Cc: Michael Ellerman Cc: Paul Mackerras Cc: Benjamin Herrenschmidt Cc: Dave Anderson Cc: Kazuhito Hagio Cc: x86@kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: kexec@lists.infradead.org Bhupesh Sharma (5): crash_core, vmcoreinfo: Append 'MAX_PHYSMEM_BITS' to vmcoreinfo arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo Documentation/arm64: Fix a simple typo in memory.rst Documentation/vmcoreinfo: Add documentation for 'MAX_PHYSMEM_BITS' Documentation/vmcoreinfo: Add documentation for 'TCR_EL1.T1SZ' Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++ Documentation/arm64/memory.rst | 2 +- arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/kernel/crash_core.c | 9 +++++++++ kernel/crash_core.c | 1 + 5 files changed, 23 insertions(+), 1 deletion(-) --=20 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F4B6C432C0 for ; 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Fri, 29 Nov 2019 11:29:12 -0800 (PST) Received: from localhost ([122.177.85.74]) by smtp.gmail.com with ESMTPSA id k10sm14560656pjs.31.2019.11.29.11.29.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 29 Nov 2019 11:29:11 -0800 (PST) From: Bhupesh Sharma To: linux-kernel@vger.kernel.org Subject: [RESEND PATCH v5 0/5] Append new variables to vmcoreinfo (TCR_EL1.T1SZ for arm64 and MAX_PHYSMEM_BITS for all archs) Date: Sat, 30 Nov 2019 00:58:41 +0530 Message-Id: <1575055726-23464-1-git-send-email-bhsharma@redhat.com> X-Mailer: git-send-email 2.7.4 X-MC-Unique: j78ZccCYMGurMAEOMz3F_g-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-doc@vger.kernel.org, bhsharma@redhat.com, Paul Mackerras , Will Deacon , Ingo Molnar , Jonathan Corbet , x86@kernel.org, Catalin Marinas , Dave Anderson , Thomas Gleixner , bhupesh.linux@gmail.com, linux-arm-kernel@lists.infradead.org, Kazuhito Hagio , Ard Biesheuvel , Steve Capper , kexec@lists.infradead.org, James Morse , Boris Petkov , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" - Resending the v5 version as Will Deacon reported that the patchset was split into two seperate threads while sending out. It was an issue with my 'msmtp' settings which is now fixed. Changes since v4: ---------------- - v4 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-November/023961.html - Addressed comments from Dave and added patches for documenting new variables appended to vmcoreinfo documentation. - Added testing report shared by Akashi for PATCH 2/5. Changes since v3: ---------------- - v3 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-March/022590.html - Addressed comments from James and exported TCR_EL1.T1SZ in vmcoreinfo instead of PTRS_PER_PGD. - Added a new patch (via [PATCH 3/3]), which fixes a simple typo in 'Documentation/arm64/memory.rst' Changes since v2: ---------------- - v2 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-March/022531.html - Protected 'MAX_PHYSMEM_BITS' vmcoreinfo variable under CONFIG_SPARSEMEM ifdef sections, as suggested by Kazu. - Updated vmcoreinfo documentation to add description about 'MAX_PHYSMEM_BITS' variable (via [PATCH 3/3]). Changes since v1: ---------------- - v1 was sent out as a single patch which can be seen here: http://lists.infradead.org/pipermail/kexec/2019-February/022411.html - v2 breaks the single patch into two independent patches: [PATCH 1/2] appends 'PTRS_PER_PGD' to vmcoreinfo for arm64 arch, whereas [PATCH 2/2] appends 'MAX_PHYSMEM_BITS' to vmcoreinfo in core kernel code = (all archs) This patchset primarily fixes the regression reported in user-space utilities like 'makedumpfile' and 'crash-utility' on arm64 architecture with the availability of 52-bit address space feature in underlying kernel. These regressions have been reported both on CPUs which don't support ARMv8.2 extensions (i.e. LVA, LPA) and are running newer kernels and also on prototype platforms (like ARMv8 FVP simulator model) which support ARMv8.2 extensions and are running newer kernels. The reason for these regressions is that right now user-space tools have no direct access to these values (since these are not exported from the kernel) and hence need to rely on a best-guess method of determining value of 'vabits_actual' and 'MAX_PHYSMEM_BITS' supported by underlying kernel. Exporting these values via vmcoreinfo will help user-land in such cases. In addition, as per suggestion from makedumpfile maintainer (Kazu), it makes more sense to append 'MAX_PHYSMEM_BITS' to vmcoreinfo in the core code itself rather than in arm64 arch-specific code, so that the user-space code for other archs can also benefit from this addition to the vmcoreinfo and use it as a standard way of determining 'SECTIONS_SHIFT' value in user-land. Cc: Boris Petkov Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Jonathan Corbet Cc: James Morse Cc: Mark Rutland Cc: Will Deacon Cc: Steve Capper Cc: Catalin Marinas Cc: Ard Biesheuvel Cc: Michael Ellerman Cc: Paul Mackerras Cc: Benjamin Herrenschmidt Cc: Dave Anderson Cc: Kazuhito Hagio Cc: x86@kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: kexec@lists.infradead.org Bhupesh Sharma (5): crash_core, vmcoreinfo: Append 'MAX_PHYSMEM_BITS' to vmcoreinfo arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo Documentation/arm64: Fix a simple typo in memory.rst Documentation/vmcoreinfo: Add documentation for 'MAX_PHYSMEM_BITS' Documentation/vmcoreinfo: Add documentation for 'TCR_EL1.T1SZ' Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++ Documentation/arm64/memory.rst | 2 +- arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/kernel/crash_core.c | 9 +++++++++ kernel/crash_core.c | 1 + 5 files changed, 23 insertions(+), 1 deletion(-) --=20 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E604DC43215 for ; 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Fri, 29 Nov 2019 11:29:11 -0800 (PST) From: Bhupesh Sharma To: linux-kernel@vger.kernel.org Subject: [RESEND PATCH v5 0/5] Append new variables to vmcoreinfo (TCR_EL1.T1SZ for arm64 and MAX_PHYSMEM_BITS for all archs) Date: Sat, 30 Nov 2019 00:58:41 +0530 Message-Id: <1575055726-23464-1-git-send-email-bhsharma@redhat.com> X-Mailer: git-send-email 2.7.4 X-MC-Unique: F2HJEzReOOCXyAqzo5CXeA-1 X-Mimecast-Spam-Score: 0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191129_112917_394173_7FB32472 X-CRM114-Status: GOOD ( 16.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-doc@vger.kernel.org, Benjamin Herrenschmidt , bhsharma@redhat.com, Paul Mackerras , Will Deacon , Ingo Molnar , Jonathan Corbet , Michael Ellerman , x86@kernel.org, Catalin Marinas , Dave Anderson , Thomas Gleixner , bhupesh.linux@gmail.com, linux-arm-kernel@lists.infradead.org, Kazuhito Hagio , Ard Biesheuvel , Steve Capper , kexec@lists.infradead.org, James Morse , Boris Petkov , linuxppc-dev@lists.ozlabs.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org - Resending the v5 version as Will Deacon reported that the patchset was split into two seperate threads while sending out. It was an issue with my 'msmtp' settings which is now fixed. Changes since v4: ---------------- - v4 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-November/023961.html - Addressed comments from Dave and added patches for documenting new variables appended to vmcoreinfo documentation. - Added testing report shared by Akashi for PATCH 2/5. Changes since v3: ---------------- - v3 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-March/022590.html - Addressed comments from James and exported TCR_EL1.T1SZ in vmcoreinfo instead of PTRS_PER_PGD. - Added a new patch (via [PATCH 3/3]), which fixes a simple typo in 'Documentation/arm64/memory.rst' Changes since v2: ---------------- - v2 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-March/022531.html - Protected 'MAX_PHYSMEM_BITS' vmcoreinfo variable under CONFIG_SPARSEMEM ifdef sections, as suggested by Kazu. - Updated vmcoreinfo documentation to add description about 'MAX_PHYSMEM_BITS' variable (via [PATCH 3/3]). Changes since v1: ---------------- - v1 was sent out as a single patch which can be seen here: http://lists.infradead.org/pipermail/kexec/2019-February/022411.html - v2 breaks the single patch into two independent patches: [PATCH 1/2] appends 'PTRS_PER_PGD' to vmcoreinfo for arm64 arch, whereas [PATCH 2/2] appends 'MAX_PHYSMEM_BITS' to vmcoreinfo in core kernel code (all archs) This patchset primarily fixes the regression reported in user-space utilities like 'makedumpfile' and 'crash-utility' on arm64 architecture with the availability of 52-bit address space feature in underlying kernel. These regressions have been reported both on CPUs which don't support ARMv8.2 extensions (i.e. LVA, LPA) and are running newer kernels and also on prototype platforms (like ARMv8 FVP simulator model) which support ARMv8.2 extensions and are running newer kernels. The reason for these regressions is that right now user-space tools have no direct access to these values (since these are not exported from the kernel) and hence need to rely on a best-guess method of determining value of 'vabits_actual' and 'MAX_PHYSMEM_BITS' supported by underlying kernel. Exporting these values via vmcoreinfo will help user-land in such cases. In addition, as per suggestion from makedumpfile maintainer (Kazu), it makes more sense to append 'MAX_PHYSMEM_BITS' to vmcoreinfo in the core code itself rather than in arm64 arch-specific code, so that the user-space code for other archs can also benefit from this addition to the vmcoreinfo and use it as a standard way of determining 'SECTIONS_SHIFT' value in user-land. Cc: Boris Petkov Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Jonathan Corbet Cc: James Morse Cc: Mark Rutland Cc: Will Deacon Cc: Steve Capper Cc: Catalin Marinas Cc: Ard Biesheuvel Cc: Michael Ellerman Cc: Paul Mackerras Cc: Benjamin Herrenschmidt Cc: Dave Anderson Cc: Kazuhito Hagio Cc: x86@kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: kexec@lists.infradead.org Bhupesh Sharma (5): crash_core, vmcoreinfo: Append 'MAX_PHYSMEM_BITS' to vmcoreinfo arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo Documentation/arm64: Fix a simple typo in memory.rst Documentation/vmcoreinfo: Add documentation for 'MAX_PHYSMEM_BITS' Documentation/vmcoreinfo: Add documentation for 'TCR_EL1.T1SZ' Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++ Documentation/arm64/memory.rst | 2 +- arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/kernel/crash_core.c | 9 +++++++++ kernel/crash_core.c | 1 + 5 files changed, 23 insertions(+), 1 deletion(-) -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from us-smtp-2.mimecast.com ([205.139.110.61] helo=us-smtp-delivery-1.mimecast.com) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1ialx9-0005iC-KD for kexec@lists.infradead.org; Fri, 29 Nov 2019 19:29:21 +0000 Received: by mail-pl1-f199.google.com with SMTP id k8so13216318plt.7 for ; Fri, 29 Nov 2019 11:29:13 -0800 (PST) From: Bhupesh Sharma Subject: [RESEND PATCH v5 0/5] Append new variables to vmcoreinfo (TCR_EL1.T1SZ for arm64 and MAX_PHYSMEM_BITS for all archs) Date: Sat, 30 Nov 2019 00:58:41 +0530 Message-Id: <1575055726-23464-1-git-send-email-bhsharma@redhat.com> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kexec" Errors-To: kexec-bounces+dwmw2=infradead.org@lists.infradead.org To: linux-kernel@vger.kernel.org Cc: Mark Rutland , linux-doc@vger.kernel.org, Benjamin Herrenschmidt , bhsharma@redhat.com, Paul Mackerras , Will Deacon , Ingo Molnar , Jonathan Corbet , Michael Ellerman , x86@kernel.org, Catalin Marinas , Dave Anderson , Thomas Gleixner , bhupesh.linux@gmail.com, linux-arm-kernel@lists.infradead.org, Kazuhito Hagio , Ard Biesheuvel , Steve Capper , kexec@lists.infradead.org, James Morse , Boris Petkov , linuxppc-dev@lists.ozlabs.org - Resending the v5 version as Will Deacon reported that the patchset was split into two seperate threads while sending out. It was an issue with my 'msmtp' settings which is now fixed. Changes since v4: ---------------- - v4 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-November/023961.html - Addressed comments from Dave and added patches for documenting new variables appended to vmcoreinfo documentation. - Added testing report shared by Akashi for PATCH 2/5. Changes since v3: ---------------- - v3 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-March/022590.html - Addressed comments from James and exported TCR_EL1.T1SZ in vmcoreinfo instead of PTRS_PER_PGD. - Added a new patch (via [PATCH 3/3]), which fixes a simple typo in 'Documentation/arm64/memory.rst' Changes since v2: ---------------- - v2 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-March/022531.html - Protected 'MAX_PHYSMEM_BITS' vmcoreinfo variable under CONFIG_SPARSEMEM ifdef sections, as suggested by Kazu. - Updated vmcoreinfo documentation to add description about 'MAX_PHYSMEM_BITS' variable (via [PATCH 3/3]). Changes since v1: ---------------- - v1 was sent out as a single patch which can be seen here: http://lists.infradead.org/pipermail/kexec/2019-February/022411.html - v2 breaks the single patch into two independent patches: [PATCH 1/2] appends 'PTRS_PER_PGD' to vmcoreinfo for arm64 arch, whereas [PATCH 2/2] appends 'MAX_PHYSMEM_BITS' to vmcoreinfo in core kernel code (all archs) This patchset primarily fixes the regression reported in user-space utilities like 'makedumpfile' and 'crash-utility' on arm64 architecture with the availability of 52-bit address space feature in underlying kernel. These regressions have been reported both on CPUs which don't support ARMv8.2 extensions (i.e. LVA, LPA) and are running newer kernels and also on prototype platforms (like ARMv8 FVP simulator model) which support ARMv8.2 extensions and are running newer kernels. The reason for these regressions is that right now user-space tools have no direct access to these values (since these are not exported from the kernel) and hence need to rely on a best-guess method of determining value of 'vabits_actual' and 'MAX_PHYSMEM_BITS' supported by underlying kernel. Exporting these values via vmcoreinfo will help user-land in such cases. In addition, as per suggestion from makedumpfile maintainer (Kazu), it makes more sense to append 'MAX_PHYSMEM_BITS' to vmcoreinfo in the core code itself rather than in arm64 arch-specific code, so that the user-space code for other archs can also benefit from this addition to the vmcoreinfo and use it as a standard way of determining 'SECTIONS_SHIFT' value in user-land. Cc: Boris Petkov Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Jonathan Corbet Cc: James Morse Cc: Mark Rutland Cc: Will Deacon Cc: Steve Capper Cc: Catalin Marinas Cc: Ard Biesheuvel Cc: Michael Ellerman Cc: Paul Mackerras Cc: Benjamin Herrenschmidt Cc: Dave Anderson Cc: Kazuhito Hagio Cc: x86@kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: kexec@lists.infradead.org Bhupesh Sharma (5): crash_core, vmcoreinfo: Append 'MAX_PHYSMEM_BITS' to vmcoreinfo arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo Documentation/arm64: Fix a simple typo in memory.rst Documentation/vmcoreinfo: Add documentation for 'MAX_PHYSMEM_BITS' Documentation/vmcoreinfo: Add documentation for 'TCR_EL1.T1SZ' Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++ Documentation/arm64/memory.rst | 2 +- arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/kernel/crash_core.c | 9 +++++++++ kernel/crash_core.c | 1 + 5 files changed, 23 insertions(+), 1 deletion(-) -- 2.7.4 _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec