From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Rafael J. Wysocki" Subject: Re: [FOR DISCUSSION 0/9] Dove PMU support Date: Thu, 19 Mar 2015 22:59:20 +0100 Message-ID: <1575145.KH9tPKGaeR@vostro.rjw.lan> References: <20150312183020.GU8656@n2100.arm.linux.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7Bit Return-path: In-Reply-To: <20150312183020.GU8656@n2100.arm.linux.org.uk> Sender: linux-pm-owner@vger.kernel.org To: Russell King - ARM Linux Cc: Andrew Lunn , Jason Cooper , Sebastian Hesselbarth , Mark Rutland , devicetree@vger.kernel.org, Pawel Moll , Len Brown , Ian Campbell , Greg Kroah-Hartman , linux-pm@vger.kernel.org, Rob Herring , Kumar Gala , linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org On Thursday, March 12, 2015 06:30:21 PM Russell King - ARM Linux wrote: > This is a re-posting of the patch set which I posted almost 10 months > ago to support the Dove PMU, with a few additional changes. This set > is based upon 3.19. > > In this set are: > > * two patches which Rafael originally acked, but there was indecision > last time around how to handle them due to potential conflicts with > work that Ulf was doing. These patches have been updated to apply > cleanly to 3.19. I don't know if people want to take these as > fixes to the PM domain code or not (hence why I'm posting this > series during the merge window - if it weren't for this, I'd hold > it off.) > > * what I regard as a fix to the PM domain code; as a result of a > previous commit, the PM domain code mismatches the runtime PM state, > which leads to the PM domain being unexpectedly left on. This patch > has been re-worked to try an alternative approach, syncing the PM > domain state with the runtime PM state after the probe has completed. > > * the addition of the core Dove PMU driver, which consists of a reset, > IRQ controller, and power domains. The reset and power domain code > has to be closely related due to the power up/down requirements of > the GPU/VPU subsystems needing to be performed atomically. (This > requirement prevents it using the MFD infrastructure, because we > would need to hold spinlocks while calling several different > sub-drivers.) > > * addition of the RTC interrupt, so we can now receive and act on > alarms generated by the Dove RTC. > > * addition of the DT descriptions for the GPU and VPU power domains. > These patches do not themselves add the DT descriptions for these > units, so these patches serve as illustrations how these should be > described. > I can apply patches [1-3/9] from this series if that helps. Rafael From mboxrd@z Thu Jan 1 00:00:00 1970 From: rjw@rjwysocki.net (Rafael J. Wysocki) Date: Thu, 19 Mar 2015 22:59:20 +0100 Subject: [FOR DISCUSSION 0/9] Dove PMU support In-Reply-To: <20150312183020.GU8656@n2100.arm.linux.org.uk> References: <20150312183020.GU8656@n2100.arm.linux.org.uk> Message-ID: <1575145.KH9tPKGaeR@vostro.rjw.lan> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thursday, March 12, 2015 06:30:21 PM Russell King - ARM Linux wrote: > This is a re-posting of the patch set which I posted almost 10 months > ago to support the Dove PMU, with a few additional changes. This set > is based upon 3.19. > > In this set are: > > * two patches which Rafael originally acked, but there was indecision > last time around how to handle them due to potential conflicts with > work that Ulf was doing. These patches have been updated to apply > cleanly to 3.19. I don't know if people want to take these as > fixes to the PM domain code or not (hence why I'm posting this > series during the merge window - if it weren't for this, I'd hold > it off.) > > * what I regard as a fix to the PM domain code; as a result of a > previous commit, the PM domain code mismatches the runtime PM state, > which leads to the PM domain being unexpectedly left on. This patch > has been re-worked to try an alternative approach, syncing the PM > domain state with the runtime PM state after the probe has completed. > > * the addition of the core Dove PMU driver, which consists of a reset, > IRQ controller, and power domains. The reset and power domain code > has to be closely related due to the power up/down requirements of > the GPU/VPU subsystems needing to be performed atomically. (This > requirement prevents it using the MFD infrastructure, because we > would need to hold spinlocks while calling several different > sub-drivers.) > > * addition of the RTC interrupt, so we can now receive and act on > alarms generated by the Dove RTC. > > * addition of the DT descriptions for the GPU and VPU power domains. > These patches do not themselves add the DT descriptions for these > units, so these patches serve as illustrations how these should be > described. > I can apply patches [1-3/9] from this series if that helps. Rafael