From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AE63C432C0 for ; Tue, 3 Dec 2019 05:20:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E3E6A20684 for ; Tue, 3 Dec 2019 05:20:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="BxUbdzs8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727207AbfLCFUc (ORCPT ); Tue, 3 Dec 2019 00:20:32 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:53182 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727091AbfLCFUW (ORCPT ); Tue, 3 Dec 2019 00:20:22 -0500 X-UUID: b043a17ac2754401ab48507795c373b4-20191203 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=NgsysKXbS5nlDOD3N4g0hN4iMinhHgqdb3oRzZLJHmA=; b=BxUbdzs8rfhBzS3w1ACTcIaHIYptfsfdrqnb0K3WCO1NQl4CY0A3IuoTC0UjXkwN10/5Z4NlccmV+XX72UoQEFQwZGK+QhJbsGqTPZEiPQKudXPdMPECKMwuYRTelK5oCs8pW5JcLh0A97qnOaMRjmSzx9bfCN/yQgPepdI9XDU=; X-UUID: b043a17ac2754401ab48507795c373b4-20191203 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1826436254; Tue, 03 Dec 2019 13:20:11 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 Dec 2019 13:19:17 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 3 Dec 2019 13:19:52 +0800 Message-ID: <1575350410.31483.5.camel@mtksdaap41> Subject: Re: [PATCH v2] drm/mediatek: add ctm property support From: CK Hu To: CC: Philipp Zabel , Rob Herring , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Tue, 3 Dec 2019 13:20:10 +0800 In-Reply-To: <1575277423-31182-1-git-send-email-yongqiang.niu@mediatek.com> References: <1575277423-31182-1-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 91EF239877E5336093CDE7FE8F20BECC4E7AD49A185B12DDB0DBD8016543D4DC2000:8 X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SGksIFlvbmdxaWFuZzoNCg0KT24gTW9uLCAyMDE5LTEyLTAyIGF0IDE3OjAzICswODAwLCB5b25n cWlhbmcubml1QG1lZGlhdGVrLmNvbSB3cm90ZToNCj4gRnJvbTogWW9uZ3FpYW5nIE5pdSA8eW9u Z3FpYW5nLm5pdUBtZWRpYXRlay5jb20+DQo+IA0KPiBhZGQgY3RtIHByb3BlcnR5IHN1cHBvcnQN Cj4gDQo+IENoYW5nZS1JZDogSTgxMTFkYTdiMzA5YjE4MDljNjMwMmU3NzQ4ZGQ5ZmQwNmRjOTdi ZGUNCg0KUmVtb3ZlIHRoaXMgQ2hhbmdlLUlkLg0KDQo+IFNpZ25lZC1vZmYtYnk6IFlvbmdxaWFu ZyBOaXUgPHlvbmdxaWFuZy5uaXVAbWVkaWF0ZWsuY29tPg0KPiAtLS0NCj4gIGRyaXZlcnMvZ3B1 L2RybS9tZWRpYXRlay9tdGtfZHJtX2NydGMuYyAgICAgfCAxNSArKysrKystDQo+ICBkcml2ZXJz L2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jIHwgNjEgKysrKysrKysrKysrKysr KysrKysrKysrKysrKy0NCj4gIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9j b21wLmggfCAxMSArKysrKysNCj4gIDMgZmlsZXMgY2hhbmdlZCwgODQgaW5zZXJ0aW9ucygrKSwg MyBkZWxldGlvbnMoLSkNCj4gDQo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0 ZWsvbXRrX2RybV9jcnRjLmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9jcnRj LmMNCj4gaW5kZXggNGZiMzQ2Yy4uMTJkYzY4NCAxMDA2NDQNCj4gLS0tIGEvZHJpdmVycy9ncHUv ZHJtL21lZGlhdGVrL210a19kcm1fY3J0Yy5jDQo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9tdGtfZHJtX2NydGMuYw0KPiBAQCAtNjY2LDEwICs2NjYsMTMgQEAgc3RhdGljIHZvaWQg bXRrX2RybV9jcnRjX2F0b21pY19mbHVzaChzdHJ1Y3QgZHJtX2NydGMgKmNydGMsDQo+ICAJaW50 IGk7DQo+ICANCj4gIAlpZiAoY3J0Yy0+c3RhdGUtPmNvbG9yX21nbXRfY2hhbmdlZCkNCj4gLQkJ Zm9yIChpID0gMDsgaSA8IG10a19jcnRjLT5kZHBfY29tcF9ucjsgaSsrKQ0KPiArCQlmb3IgKGkg PSAwOyBpIDwgbXRrX2NydGMtPmRkcF9jb21wX25yOyBpKyspIHsNCj4gIAkJCW10a19kZHBfZ2Ft bWFfc2V0KG10a19jcnRjLT5kZHBfY29tcFtpXSwNCj4gIAkJCQkJICBjcnRjLT5zdGF0ZSwNCj4g IAkJCQkJICBtdGtfY3J0Y19zdGF0ZS0+Y21kcV9oYW5kbGUpOw0KPiArCQkJbXRrX2RkcF9jdG1f c2V0KG10a19jcnRjLT5kZHBfY29tcFtpXSwgY3J0Yy0+c3RhdGUpOw0KDQpTb3JyeSwgSSdtIG5v dCBub3RpY2VkIHRoYXQgdGhlIGNvZGUgaGVyZSB3b3VsZCBub3Qgd3JpdGUgcmVnaXN0ZXIgaW4N CnZibGFuayBwZXJpb2QuIElmIGN0bSBjb3VsZCBiZSBzZXQgb3V0IG9mIHZibGFuayBwZXJpb2Qs IHBsYWNlIHRoZSBjb2RlDQpoZXJlIGFuZCBkbyBub3QgbmVlZCB0byBzdXBwb3J0IGNtZHEuIElm IGN0bSBzaG91bGQgYmUgc2V0IGluc2lkZSB2YmxhbmsNCnBlcmlvZCwgbW92ZSB0aGUgY29kZSB0 byBtdGtfY3J0Y19kZHBfY29uZmlnKCkgYW5kIHN1cHBvcnQgY21kcQ0KaW50ZXJmYWNlLg0KDQo+ ICsJCX0NCj4gKw0KPiAgI2lmZGVmIENPTkZJR19NVEtfQ01EUQ0KPiAgCWlmIChtdGtfY3J0Yy0+ Y21kcV9jbGllbnQpIHsNCj4gIAkJZHJtX2F0b21pY19zdGF0ZV9nZXQob2xkX2F0b21pY19zdGF0 ZSk7DQo+IEBAIC04MTksNiArODIyLDggQEAgaW50IG10a19kcm1fY3J0Y19jcmVhdGUoc3RydWN0 IGRybV9kZXZpY2UgKmRybV9kZXYsDQo+ICAJaW50IHBpcGUgPSBwcml2LT5udW1fcGlwZXM7DQo+ ICAJaW50IHJldDsNCj4gIAlpbnQgaTsNCj4gKwlib29sIGhhc19jdG0gPSBmYWxzZTsNCj4gKwl1 aW50IGdhbW1hX2x1dF9zaXplID0gMDsNCj4gIA0KPiAgCWlmICghcGF0aCkNCj4gIAkJcmV0dXJu IDA7DQo+IEBAIC04NzAsNiArODc1LDEyIEBAIGludCBtdGtfZHJtX2NydGNfY3JlYXRlKHN0cnVj dCBkcm1fZGV2aWNlICpkcm1fZGV2LA0KPiAgCQl9DQo+ICANCj4gIAkJbXRrX2NydGMtPmRkcF9j b21wW2ldID0gY29tcDsNCj4gKw0KPiArCQlpZiAoY29tcF9pZCA9PSBERFBfQ09NUE9ORU5UX0ND T1JSKQ0KPiArCQkJaGFzX2N0bSA9IHRydWU7DQo+ICsNCj4gKwkJaWYgKGNvbXBfaWQgPT0gRERQ X0NPTVBPTkVOVF9HQU1NQSkNCj4gKwkJCWdhbW1hX2x1dF9zaXplID0gTVRLX0xVVF9TSVpFOw0K PiAgCX0NCj4gIA0KPiAgCWZvciAoaSA9IDA7IGkgPCBtdGtfY3J0Yy0+ZGRwX2NvbXBfbnI7IGkr KykNCj4gQEAgLTg5MSw3ICs5MDIsNyBAQCBpbnQgbXRrX2RybV9jcnRjX2NyZWF0ZShzdHJ1Y3Qg ZHJtX2RldmljZSAqZHJtX2RldiwNCj4gIAlpZiAocmV0IDwgMCkNCj4gIAkJcmV0dXJuIHJldDsN Cj4gIAlkcm1fbW9kZV9jcnRjX3NldF9nYW1tYV9zaXplKCZtdGtfY3J0Yy0+YmFzZSwgTVRLX0xV VF9TSVpFKTsNCj4gLQlkcm1fY3J0Y19lbmFibGVfY29sb3JfbWdtdCgmbXRrX2NydGMtPmJhc2Us IDAsIGZhbHNlLCBNVEtfTFVUX1NJWkUpOw0KPiArCWRybV9jcnRjX2VuYWJsZV9jb2xvcl9tZ210 KCZtdGtfY3J0Yy0+YmFzZSwgMCwgaGFzX2N0bSwgZ2FtbWFfbHV0X3NpemUpOw0KPiAgCXByaXYt Pm51bV9waXBlcysrOw0KPiAgI2lmZGVmIENPTkZJR19NVEtfQ01EUQ0KPiAgCW10a19jcnRjLT5j bWRxX2NsaWVudCA9DQo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRr X2RybV9kZHBfY29tcC5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2Nv bXAuYw0KPiBpbmRleCA5Y2MxMmFmLi4yZmQ1MmJhIDEwMDY0NA0KPiAtLS0gYS9kcml2ZXJzL2dw dS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jDQo+ICsrKyBiL2RyaXZlcnMvZ3B1L2Ry bS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmMNCj4gQEAgLTM4LDcgKzM4LDE1IEBADQo+ICAj ZGVmaW5lIENDT1JSX0VOCQkJCUJJVCgwKQ0KPiAgI2RlZmluZSBESVNQX0NDT1JSX0NGRwkJCQkw eDAwMjANCj4gICNkZWZpbmUgQ0NPUlJfUkVMQVlfTU9ERQkJCUJJVCgwKQ0KPiArI2RlZmluZSBD Q09SUl9FTkdJTkVfRU4JCQkJQklUKDEpDQo+ICsjZGVmaW5lIENDT1JSX0dBTU1BX09GRgkJCQlC SVQoMikNCj4gKyNkZWZpbmUgQ0NPUlJfV0dBTVVUX1NSQ19DTElQCQkJQklUKDMpDQo+ICAjZGVm aW5lIERJU1BfQ0NPUlJfU0laRQkJCQkweDAwMzANCj4gKyNkZWZpbmUgRElTUF9DQ09SUl9DT0VG XzAJCQkweDAwODANCj4gKyNkZWZpbmUgRElTUF9DQ09SUl9DT0VGXzEJCQkweDAwODQNCj4gKyNk ZWZpbmUgRElTUF9DQ09SUl9DT0VGXzIJCQkweDAwODgNCj4gKyNkZWZpbmUgRElTUF9DQ09SUl9D T0VGXzMJCQkweDAwOEMNCj4gKyNkZWZpbmUgRElTUF9DQ09SUl9DT0VGXzQJCQkweDAwOTANCj4g IA0KPiAgI2RlZmluZSBESVNQX0RJVEhFUl9FTgkJCQkweDAwMDANCj4gICNkZWZpbmUgRElUSEVS X0VOCQkJCUJJVCgwKQ0KPiBAQCAtMTg3LDcgKzE5NSw3IEBAIHN0YXRpYyB2b2lkIG10a19jY29y cl9jb25maWcoc3RydWN0IG10a19kZHBfY29tcCAqY29tcCwgdW5zaWduZWQgaW50IHcsDQo+ICAJ CQkgICAgIHVuc2lnbmVkIGludCBicGMsIHN0cnVjdCBjbWRxX3BrdCAqY21kcV9wa3QpDQo+ICB7 DQo+ICAJbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgaCA8PCAxNiB8IHcsIGNvbXAsIERJU1BfQ0NP UlJfU0laRSk7DQo+IC0JbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgQ0NPUlJfUkVMQVlfTU9ERSwg Y29tcCwgRElTUF9DQ09SUl9DRkcpOw0KPiArCW10a19kZHBfd3JpdGUoY21kcV9wa3QsIENDT1JS X0VOR0lORV9FTiwgY29tcCwgRElTUF9DQ09SUl9DRkcpOw0KPiAgfQ0KPiAgDQo+ICBzdGF0aWMg dm9pZCBtdGtfY2NvcnJfc3RhcnQoc3RydWN0IG10a19kZHBfY29tcCAqY29tcCkNCj4gQEAgLTIw MCw2ICsyMDgsNTYgQEAgc3RhdGljIHZvaWQgbXRrX2Njb3JyX3N0b3Aoc3RydWN0IG10a19kZHBf Y29tcCAqY29tcCkNCj4gIAl3cml0ZWxfcmVsYXhlZCgweDAsIGNvbXAtPnJlZ3MgKyBESVNQX0ND T1JSX0VOKTsNCj4gIH0NCj4gIA0KPiArLyogQ29udmVydHMgYSBEUk0gUzMxLjMyIHZhbHVlIHRv IHRoZSBIVyBTMC4xMSBmb3JtYXQuICovDQo+ICtzdGF0aWMgdTE2IG10a19jdG1fczMxXzMyX3Rv X3MwXzExKHU2NCBpbikNCj4gK3sNCj4gKwl1MTYgcjsNCj4gKw0KPiArCS8qIFNpZ24gYml0LiAq Lw0KPiArCXIgPSBpbiAmIEJJVF9VTEwoNjMpID8gQklUKDExKSA6IDA7DQo+ICsNCj4gKwlpZiAo KGluICYgR0VOTUFTS19VTEwoNjIsIDMzKSkgPiAwKSB7DQoNCmlmICgoaW4gJiBHRU5NQVNLX1VM TCg2MiwgMzIpKSA+IDApIHsNCg0KPiArCQkvKiBXZSBoYXZlIHplcm8gaW50ZWdlciBiaXRzIHNv IHdlIGNhbiBvbmx5IHNhdHVyYXRlIGhlcmUuICovDQo+ICsJCXIgfD0gR0VOTUFTSygxMCwgMCk7 DQo+ICsJfSBlbHNlIHsNCj4gKwkJLyogT3RoZXJ3aXNlIHRha2UgdGhlIDkgbW9zdCBpbXBvcnRh bnQgZnJhY3Rpb25hbCBiaXRzLiAqLw0KPiArCQlyIHw9IChpbiA+PiAyMikgJiBHRU5NQVNLKDEw LCAwKTsNCg0KciB8PSAoaW4gPj4gMjEpICYgR0VOTUFTSygxMCwgMCk7DQoNClJlZ2FyZHMsDQpD Sw0KDQo+ICsJfQ0KPiArDQo+ICsJcmV0dXJuIHI7DQo+ICt9DQo+ICsNCj4gK3N0YXRpYyB2b2lk IG10a19jY29ycl9jdG1fc2V0KHN0cnVjdCBtdGtfZGRwX2NvbXAgKmNvbXAsDQo+ICsJCQkgICAg ICBzdHJ1Y3QgZHJtX2NydGNfc3RhdGUgKnN0YXRlDQo+ICsJCQkgICAgICBzdHJ1Y3QgY21kcV9w a3QgKmNtZHFfcGt0KQ0KPiArew0KPiArCXN0cnVjdCBkcm1fcHJvcGVydHlfYmxvYiAqYmxvYiA9 IHN0YXRlLT5jdG07DQo+ICsJc3RydWN0IGRybV9jb2xvcl9jdG0gKmN0bTsNCj4gKwljb25zdCB1 NjQgKmlucHV0Ow0KPiArCXVpbnQxNl90IGNvZWZmc1s5XSA9IHsgMCB9Ow0KPiArCWludCBpOw0K PiArDQo+ICsJaWYgKCFibG9iKQ0KPiArCQlyZXR1cm47DQo+ICsNCj4gKwljdG0gPSAoc3RydWN0 IGRybV9jb2xvcl9jdG0gKilibG9iLT5kYXRhOw0KPiArCWlucHV0ID0gY3RtLT5tYXRyaXg7DQo+ ICsNCj4gKwlmb3IgKGkgPSAwOyBpIDwgQVJSQVlfU0laRShjb2VmZnMpOyBpKyspDQo+ICsJCWNv ZWZmc1tpXSA9IG10a19jdG1fczMxXzMyX3RvX3MwXzExKGlucHV0W2ldKTsNCj4gKw0KPiArCW10 a19kZHBfd3JpdGUoY21kcV9wa3QsIGNvZWZmc1swXSA8PCAxNiB8IGNvZWZmc1sxXSwNCj4gKwkJ ICAgICAgY29tcCwgRElTUF9DQ09SUl9DT0VGXzApOw0KPiArCW10a19kZHBfd3JpdGUoY21kcV9w a3QsIGNvZWZmc1syXSA8PCAxNiB8IGNvZWZmc1szXSwNCj4gKwkJICAgICAgY29tcCwgRElTUF9D Q09SUl9DT0VGXzEpOw0KPiArCW10a19kZHBfd3JpdGUoY21kcV9wa3QsIGNvZWZmc1s0XSA8PCAx NiB8IGNvZWZmc1s1XSwNCj4gKwkJICAgICAgY29tcCwgRElTUF9DQ09SUl9DT0VGXzIpOw0KPiAr CW10a19kZHBfd3JpdGUoY21kcV9wa3QsIGNvZWZmc1s2XSA8PCAxNiB8IGNvZWZmc1s3XSwNCj4g KwkJICAgICAgY29tcCwgRElTUF9DQ09SUl9DT0VGXzMpOw0KPiArCW10a19kZHBfd3JpdGUoY21k cV9wa3QsIGNvZWZmc1s4XSA8PCAxNiwNCj4gKwkJICAgICAgY29tcCwgRElTUF9DQ09SUl9DT0VG XzQpOw0KPiArfQ0KPiArDQo+ICBzdGF0aWMgdm9pZCBtdGtfZGl0aGVyX2NvbmZpZyhzdHJ1Y3Qg bXRrX2RkcF9jb21wICpjb21wLCB1bnNpZ25lZCBpbnQgdywNCj4gIAkJCSAgICAgIHVuc2lnbmVk IGludCBoLCB1bnNpZ25lZCBpbnQgdnJlZnJlc2gsDQo+ICAJCQkgICAgICB1bnNpZ25lZCBpbnQg YnBjLCBzdHJ1Y3QgY21kcV9wa3QgKmNtZHFfcGt0KQ0KPiBAQCAtMjY5LDYgKzMyNyw3IEBAIHN0 YXRpYyB2b2lkIG10a19nYW1tYV9zZXQoc3RydWN0IG10a19kZHBfY29tcCAqY29tcCwNCj4gIAku Y29uZmlnID0gbXRrX2Njb3JyX2NvbmZpZywNCj4gIAkuc3RhcnQgPSBtdGtfY2NvcnJfc3RhcnQs DQo+ICAJLnN0b3AgPSBtdGtfY2NvcnJfc3RvcCwNCj4gKwkuY3RtX3NldCA9IG10a19jY29ycl9j dG1fc2V0LA0KPiAgfTsNCj4gIA0KPiAgc3RhdGljIGNvbnN0IHN0cnVjdCBtdGtfZGRwX2NvbXBf ZnVuY3MgZGRwX2RpdGhlciA9IHsNCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9tdGtfZHJtX2RkcF9jb21wLmggYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2Ry bV9kZHBfY29tcC5oDQo+IGluZGV4IDViMGEzZDQuLjRlM2U1YWEgMTAwNjQ0DQo+IC0tLSBhL2Ry aXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmgNCj4gKysrIGIvZHJpdmVy cy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2NvbXAuaA0KPiBAQCAtOTUsNiArOTUsOSBA QCBzdHJ1Y3QgbXRrX2RkcF9jb21wX2Z1bmNzIHsNCj4gIAkJCSAgc3RydWN0IGNtZHFfcGt0ICpj bWRxX3BrdCk7DQo+ICAJdm9pZCAoKmJnY2xyX2luX29uKShzdHJ1Y3QgbXRrX2RkcF9jb21wICpj b21wKTsNCj4gIAl2b2lkICgqYmdjbHJfaW5fb2ZmKShzdHJ1Y3QgbXRrX2RkcF9jb21wICpjb21w KTsNCj4gKwl2b2lkICgqY3RtX3NldCkoc3RydWN0IG10a19kZHBfY29tcCAqY29tcCwNCj4gKwkJ CXN0cnVjdCBkcm1fY3J0Y19zdGF0ZSAqc3RhdGUNCj4gKwkJCXN0cnVjdCBjbWRxX3BrdCAqY21k cV9wa3QpOw0KPiAgfTsNCj4gIA0KPiAgc3RydWN0IG10a19kZHBfY29tcCB7DQo+IEBAIC0yMTMs NiArMjE2LDE0IEBAIHN0YXRpYyBpbmxpbmUgdm9pZCBtdGtfZGRwX2NvbXBfYmdjbHJfaW5fb2Zm KHN0cnVjdCBtdGtfZGRwX2NvbXAgKmNvbXApDQo+ICAJCWNvbXAtPmZ1bmNzLT5iZ2Nscl9pbl9v ZmYoY29tcCk7DQo+ICB9DQo+ICANCj4gK3N0YXRpYyBpbmxpbmUgdm9pZCBtdGtfZGRwX2N0bV9z ZXQoc3RydWN0IG10a19kZHBfY29tcCAqY29tcCwNCj4gKwkJCQkgICBzdHJ1Y3QgZHJtX2NydGNf c3RhdGUgKnN0YXRlDQo+ICsJCQkJICAgc3RydWN0IGNtZHFfcGt0ICpjbWRxX3BrdCkNCj4gK3sN Cj4gKwlpZiAoY29tcC0+ZnVuY3MgJiYgY29tcC0+ZnVuY3MtPmN0bV9zZXQpDQo+ICsJCWNvbXAt PmZ1bmNzLT5jdG1fc2V0KGNvbXAsIHN0YXRlKTsNCj4gK30NCj4gKw0KPiAgaW50IG10a19kZHBf Y29tcF9nZXRfaWQoc3RydWN0IGRldmljZV9ub2RlICpub2RlLA0KPiAgCQkJZW51bSBtdGtfZGRw X2NvbXBfdHlwZSBjb21wX3R5cGUpOw0KPiAgaW50IG10a19kZHBfY29tcF9pbml0KHN0cnVjdCBk ZXZpY2UgKmRldiwgc3RydWN0IGRldmljZV9ub2RlICpjb21wX25vZGUsDQoNCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37656C432C3 for ; Tue, 3 Dec 2019 05:20:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F3D2420684 for ; Tue, 3 Dec 2019 05:20:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="gzP3ps8V"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="LnApxK2Z" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F3D2420684 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RHIbi6x/UzprrIty+YfONXoxNpJpewfFlTv9ZDCWlik=; b=gzP3ps8VUQQwes g9PtFj7uI6mRDXU3eLQxuXRtygSkE1FFm0SfSkvO2iY+pGk2ut8/L5wDEHIDwQYkFVaeS9z0x2fsJ cILrvxkxiM6RgcB5Rbw3fB8YEX9R559QdhWCDypIxChIBM6N6e9spTRU8Pi9d1j0vc5QPpzYWTlZv 4wPfO+3CCRQ92qM/HYWQJZHl66Rn76l7ISv0DtmIKsTvN0KOo9nRSelG8cKSCSXUQnp1b0O+1ADyO QQNgmZBbASeqClLGyyxFX3dQgJsJzC5sJFj3unYsbOmU5oluGj7BpgsqyIPMNsjUFvrQs7ZmCtyAI h+aA7gyUaO6iB84oR+rA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1ic0cA-0003uu-RT; Tue, 03 Dec 2019 05:20:46 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1ic0bl-0003Pb-PE; Tue, 03 Dec 2019 05:20:23 +0000 X-UUID: fb7964764351465bbb1b4289d50576fd-20191202 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=NgsysKXbS5nlDOD3N4g0hN4iMinhHgqdb3oRzZLJHmA=; b=LnApxK2ZNDZdG0RU7npCaFrBisXrUbPhSb6Npf/hRTDIDjcuhjthLEhRMZarOBeUMCmRNz28qiE20zM9p0JRn4UHRKZeFNZZ4Cqe3YMHX3RbwauAotmcuSJh1eI3OH5jGURQ9noK7RqhpUZVHtJV2f3pYoO1cUcwgfT6H4sqp/4=; X-UUID: fb7964764351465bbb1b4289d50576fd-20191202 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1558830226; Mon, 02 Dec 2019 21:20:15 -0800 Received: from MTKMBS31N2.mediatek.inc (172.27.4.87) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 2 Dec 2019 21:20:24 -0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 Dec 2019 13:19:17 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 3 Dec 2019 13:19:52 +0800 Message-ID: <1575350410.31483.5.camel@mtksdaap41> Subject: Re: [PATCH v2] drm/mediatek: add ctm property support From: CK Hu To: Date: Tue, 3 Dec 2019 13:20:10 +0800 In-Reply-To: <1575277423-31182-1-git-send-email-yongqiang.niu@mediatek.com> References: <1575277423-31182-1-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 91EF239877E5336093CDE7FE8F20BECC4E7AD49A185B12DDB0DBD8016543D4DC2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191202_212021_865336_3E450BF4 X-CRM114-Status: GOOD ( 20.88 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, Yongqiang: On Mon, 2019-12-02 at 17:03 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > add ctm property support > > Change-Id: I8111da7b309b1809c6302e7748dd9fd06dc97bde Remove this Change-Id. > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 15 ++++++- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 61 ++++++++++++++++++++++++++++- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 11 ++++++ > 3 files changed, 84 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index 4fb346c..12dc684 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -666,10 +666,13 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, > int i; > > if (crtc->state->color_mgmt_changed) > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], > crtc->state, > mtk_crtc_state->cmdq_handle); > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); Sorry, I'm not noticed that the code here would not write register in vblank period. If ctm could be set out of vblank period, place the code here and do not need to support cmdq. If ctm should be set inside vblank period, move the code to mtk_crtc_ddp_config() and support cmdq interface. > + } > + > #ifdef CONFIG_MTK_CMDQ > if (mtk_crtc->cmdq_client) { > drm_atomic_state_get(old_atomic_state); > @@ -819,6 +822,8 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > int pipe = priv->num_pipes; > int ret; > int i; > + bool has_ctm = false; > + uint gamma_lut_size = 0; > > if (!path) > return 0; > @@ -870,6 +875,12 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > } > > mtk_crtc->ddp_comp[i] = comp; > + > + if (comp_id == DDP_COMPONENT_CCORR) > + has_ctm = true; > + > + if (comp_id == DDP_COMPONENT_GAMMA) > + gamma_lut_size = MTK_LUT_SIZE; > } > > for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) > @@ -891,7 +902,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > if (ret < 0) > return ret; > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); > priv->num_pipes++; > #ifdef CONFIG_MTK_CMDQ > mtk_crtc->cmdq_client = > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 9cc12af..2fd52ba 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -38,7 +38,15 @@ > #define CCORR_EN BIT(0) > #define DISP_CCORR_CFG 0x0020 > #define CCORR_RELAY_MODE BIT(0) > +#define CCORR_ENGINE_EN BIT(1) > +#define CCORR_GAMMA_OFF BIT(2) > +#define CCORR_WGAMUT_SRC_CLIP BIT(3) > #define DISP_CCORR_SIZE 0x0030 > +#define DISP_CCORR_COEF_0 0x0080 > +#define DISP_CCORR_COEF_1 0x0084 > +#define DISP_CCORR_COEF_2 0x0088 > +#define DISP_CCORR_COEF_3 0x008C > +#define DISP_CCORR_COEF_4 0x0090 > > #define DISP_DITHER_EN 0x0000 > #define DITHER_EN BIT(0) > @@ -187,7 +195,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > { > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE); > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG); > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG); > } > > static void mtk_ccorr_start(struct mtk_ddp_comp *comp) > @@ -200,6 +208,56 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp) > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN); > } > > +/* Converts a DRM S31.32 value to the HW S0.11 format. */ > +static u16 mtk_ctm_s31_32_to_s0_11(u64 in) > +{ > + u16 r; > + > + /* Sign bit. */ > + r = in & BIT_ULL(63) ? BIT(11) : 0; > + > + if ((in & GENMASK_ULL(62, 33)) > 0) { if ((in & GENMASK_ULL(62, 32)) > 0) { > + /* We have zero integer bits so we can only saturate here. */ > + r |= GENMASK(10, 0); > + } else { > + /* Otherwise take the 9 most important fractional bits. */ > + r |= (in >> 22) & GENMASK(10, 0); r |= (in >> 21) & GENMASK(10, 0); Regards, CK > + } > + > + return r; > +} > + > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp, > + struct drm_crtc_state *state > + struct cmdq_pkt *cmdq_pkt) > +{ > + struct drm_property_blob *blob = state->ctm; > + struct drm_color_ctm *ctm; > + const u64 *input; > + uint16_t coeffs[9] = { 0 }; > + int i; > + > + if (!blob) > + return; > + > + ctm = (struct drm_color_ctm *)blob->data; > + input = ctm->matrix; > + > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) > + coeffs[i] = mtk_ctm_s31_32_to_s0_11(input[i]); > + > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > + comp, DISP_CCORR_COEF_0); > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > + comp, DISP_CCORR_COEF_1); > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > + comp, DISP_CCORR_COEF_2); > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > + comp, DISP_CCORR_COEF_3); > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > + comp, DISP_CCORR_COEF_4); > +} > + > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -269,6 +327,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp, > .config = mtk_ccorr_config, > .start = mtk_ccorr_start, > .stop = mtk_ccorr_stop, > + .ctm_set = mtk_ccorr_ctm_set, > }; > > static const struct mtk_ddp_comp_funcs ddp_dither = { > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index 5b0a3d4..4e3e5aa 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -95,6 +95,9 @@ struct mtk_ddp_comp_funcs { > struct cmdq_pkt *cmdq_pkt); > void (*bgclr_in_on)(struct mtk_ddp_comp *comp); > void (*bgclr_in_off)(struct mtk_ddp_comp *comp); > + void (*ctm_set)(struct mtk_ddp_comp *comp, > + struct drm_crtc_state *state > + struct cmdq_pkt *cmdq_pkt); > }; > > struct mtk_ddp_comp { > @@ -213,6 +216,14 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp) > comp->funcs->bgclr_in_off(comp); > } > > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp, > + struct drm_crtc_state *state > + struct cmdq_pkt *cmdq_pkt) > +{ > + if (comp->funcs && comp->funcs->ctm_set) > + comp->funcs->ctm_set(comp, state); > +} > + > int mtk_ddp_comp_get_id(struct device_node *node, > enum mtk_ddp_comp_type comp_type); > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node, _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE7B8C432C3 for ; Tue, 3 Dec 2019 05:20:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9521020684 for ; Tue, 3 Dec 2019 05:20:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="CnEDhUB8"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="LnApxK2Z" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9521020684 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MBcD3bNiW+zxbDWmHsQbtb4bQbvxgZCA4055DWVsWnQ=; b=CnEDhUB8X7xNmQ SjMJVRQAB3Ya472OvT5WJ3aEu2T8+EJ1GDNvvXTxLkj1DpJH8JBDFKARd2iNor79iWKbKRiIOxpbm dRa5R/uQWLmyH9urilDFYQPG2WxbIXivE5cRDXLIFDH0CJsY9Yz82x0LetE9aeYzH19VSzXbeekRt /tqcHD8s9EDCJjgos+NnJ5kwrj8cSncec8x1aC+Zjso3HMtfQIBUaLUa/Utcgh5c8HO0oz1keMfUi q4M2KSr0CR2SVvFHAJVLMqg1YbCjOdkrviqbwpOR6HDAcyruRU0e3HZQP9KUBjwB51cAkhRJJv+gR hy1hEeJ8tYYx5OJAxZgw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1ic0bw-0003bg-G7; Tue, 03 Dec 2019 05:20:32 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1ic0bl-0003Pb-PE; Tue, 03 Dec 2019 05:20:23 +0000 X-UUID: fb7964764351465bbb1b4289d50576fd-20191202 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=NgsysKXbS5nlDOD3N4g0hN4iMinhHgqdb3oRzZLJHmA=; b=LnApxK2ZNDZdG0RU7npCaFrBisXrUbPhSb6Npf/hRTDIDjcuhjthLEhRMZarOBeUMCmRNz28qiE20zM9p0JRn4UHRKZeFNZZ4Cqe3YMHX3RbwauAotmcuSJh1eI3OH5jGURQ9noK7RqhpUZVHtJV2f3pYoO1cUcwgfT6H4sqp/4=; X-UUID: fb7964764351465bbb1b4289d50576fd-20191202 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1558830226; Mon, 02 Dec 2019 21:20:15 -0800 Received: from MTKMBS31N2.mediatek.inc (172.27.4.87) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 2 Dec 2019 21:20:24 -0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 Dec 2019 13:19:17 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 3 Dec 2019 13:19:52 +0800 Message-ID: <1575350410.31483.5.camel@mtksdaap41> Subject: Re: [PATCH v2] drm/mediatek: add ctm property support From: CK Hu To: Date: Tue, 3 Dec 2019 13:20:10 +0800 In-Reply-To: <1575277423-31182-1-git-send-email-yongqiang.niu@mediatek.com> References: <1575277423-31182-1-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 91EF239877E5336093CDE7FE8F20BECC4E7AD49A185B12DDB0DBD8016543D4DC2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191202_212021_865336_3E450BF4 X-CRM114-Status: GOOD ( 20.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Yongqiang: On Mon, 2019-12-02 at 17:03 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > add ctm property support > > Change-Id: I8111da7b309b1809c6302e7748dd9fd06dc97bde Remove this Change-Id. > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 15 ++++++- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 61 ++++++++++++++++++++++++++++- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 11 ++++++ > 3 files changed, 84 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index 4fb346c..12dc684 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -666,10 +666,13 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, > int i; > > if (crtc->state->color_mgmt_changed) > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], > crtc->state, > mtk_crtc_state->cmdq_handle); > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); Sorry, I'm not noticed that the code here would not write register in vblank period. If ctm could be set out of vblank period, place the code here and do not need to support cmdq. If ctm should be set inside vblank period, move the code to mtk_crtc_ddp_config() and support cmdq interface. > + } > + > #ifdef CONFIG_MTK_CMDQ > if (mtk_crtc->cmdq_client) { > drm_atomic_state_get(old_atomic_state); > @@ -819,6 +822,8 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > int pipe = priv->num_pipes; > int ret; > int i; > + bool has_ctm = false; > + uint gamma_lut_size = 0; > > if (!path) > return 0; > @@ -870,6 +875,12 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > } > > mtk_crtc->ddp_comp[i] = comp; > + > + if (comp_id == DDP_COMPONENT_CCORR) > + has_ctm = true; > + > + if (comp_id == DDP_COMPONENT_GAMMA) > + gamma_lut_size = MTK_LUT_SIZE; > } > > for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) > @@ -891,7 +902,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > if (ret < 0) > return ret; > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); > priv->num_pipes++; > #ifdef CONFIG_MTK_CMDQ > mtk_crtc->cmdq_client = > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 9cc12af..2fd52ba 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -38,7 +38,15 @@ > #define CCORR_EN BIT(0) > #define DISP_CCORR_CFG 0x0020 > #define CCORR_RELAY_MODE BIT(0) > +#define CCORR_ENGINE_EN BIT(1) > +#define CCORR_GAMMA_OFF BIT(2) > +#define CCORR_WGAMUT_SRC_CLIP BIT(3) > #define DISP_CCORR_SIZE 0x0030 > +#define DISP_CCORR_COEF_0 0x0080 > +#define DISP_CCORR_COEF_1 0x0084 > +#define DISP_CCORR_COEF_2 0x0088 > +#define DISP_CCORR_COEF_3 0x008C > +#define DISP_CCORR_COEF_4 0x0090 > > #define DISP_DITHER_EN 0x0000 > #define DITHER_EN BIT(0) > @@ -187,7 +195,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > { > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE); > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG); > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG); > } > > static void mtk_ccorr_start(struct mtk_ddp_comp *comp) > @@ -200,6 +208,56 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp) > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN); > } > > +/* Converts a DRM S31.32 value to the HW S0.11 format. */ > +static u16 mtk_ctm_s31_32_to_s0_11(u64 in) > +{ > + u16 r; > + > + /* Sign bit. */ > + r = in & BIT_ULL(63) ? BIT(11) : 0; > + > + if ((in & GENMASK_ULL(62, 33)) > 0) { if ((in & GENMASK_ULL(62, 32)) > 0) { > + /* We have zero integer bits so we can only saturate here. */ > + r |= GENMASK(10, 0); > + } else { > + /* Otherwise take the 9 most important fractional bits. */ > + r |= (in >> 22) & GENMASK(10, 0); r |= (in >> 21) & GENMASK(10, 0); Regards, CK > + } > + > + return r; > +} > + > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp, > + struct drm_crtc_state *state > + struct cmdq_pkt *cmdq_pkt) > +{ > + struct drm_property_blob *blob = state->ctm; > + struct drm_color_ctm *ctm; > + const u64 *input; > + uint16_t coeffs[9] = { 0 }; > + int i; > + > + if (!blob) > + return; > + > + ctm = (struct drm_color_ctm *)blob->data; > + input = ctm->matrix; > + > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) > + coeffs[i] = mtk_ctm_s31_32_to_s0_11(input[i]); > + > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > + comp, DISP_CCORR_COEF_0); > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > + comp, DISP_CCORR_COEF_1); > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > + comp, DISP_CCORR_COEF_2); > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > + comp, DISP_CCORR_COEF_3); > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > + comp, DISP_CCORR_COEF_4); > +} > + > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -269,6 +327,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp, > .config = mtk_ccorr_config, > .start = mtk_ccorr_start, > .stop = mtk_ccorr_stop, > + .ctm_set = mtk_ccorr_ctm_set, > }; > > static const struct mtk_ddp_comp_funcs ddp_dither = { > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index 5b0a3d4..4e3e5aa 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -95,6 +95,9 @@ struct mtk_ddp_comp_funcs { > struct cmdq_pkt *cmdq_pkt); > void (*bgclr_in_on)(struct mtk_ddp_comp *comp); > void (*bgclr_in_off)(struct mtk_ddp_comp *comp); > + void (*ctm_set)(struct mtk_ddp_comp *comp, > + struct drm_crtc_state *state > + struct cmdq_pkt *cmdq_pkt); > }; > > struct mtk_ddp_comp { > @@ -213,6 +216,14 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp) > comp->funcs->bgclr_in_off(comp); > } > > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp, > + struct drm_crtc_state *state > + struct cmdq_pkt *cmdq_pkt) > +{ > + if (comp->funcs && comp->funcs->ctm_set) > + comp->funcs->ctm_set(comp, state); > +} > + > int mtk_ddp_comp_get_id(struct device_node *node, > enum mtk_ddp_comp_type comp_type); > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [PATCH v2] drm/mediatek: add ctm property support Date: Tue, 3 Dec 2019 13:20:10 +0800 Message-ID: <1575350410.31483.5.camel@mtksdaap41> References: <1575277423-31182-1-git-send-email-yongqiang.niu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1575277423-31182-1-git-send-email-yongqiang.niu@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: yongqiang.niu@mediatek.com Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org List-Id: dri-devel@lists.freedesktop.org Hi, Yongqiang: On Mon, 2019-12-02 at 17:03 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > add ctm property support > > Change-Id: I8111da7b309b1809c6302e7748dd9fd06dc97bde Remove this Change-Id. > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 15 ++++++- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 61 ++++++++++++++++++++++++++++- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 11 ++++++ > 3 files changed, 84 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index 4fb346c..12dc684 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -666,10 +666,13 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, > int i; > > if (crtc->state->color_mgmt_changed) > - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) > + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { > mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], > crtc->state, > mtk_crtc_state->cmdq_handle); > + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); Sorry, I'm not noticed that the code here would not write register in vblank period. If ctm could be set out of vblank period, place the code here and do not need to support cmdq. If ctm should be set inside vblank period, move the code to mtk_crtc_ddp_config() and support cmdq interface. > + } > + > #ifdef CONFIG_MTK_CMDQ > if (mtk_crtc->cmdq_client) { > drm_atomic_state_get(old_atomic_state); > @@ -819,6 +822,8 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > int pipe = priv->num_pipes; > int ret; > int i; > + bool has_ctm = false; > + uint gamma_lut_size = 0; > > if (!path) > return 0; > @@ -870,6 +875,12 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > } > > mtk_crtc->ddp_comp[i] = comp; > + > + if (comp_id == DDP_COMPONENT_CCORR) > + has_ctm = true; > + > + if (comp_id == DDP_COMPONENT_GAMMA) > + gamma_lut_size = MTK_LUT_SIZE; > } > > for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) > @@ -891,7 +902,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > if (ret < 0) > return ret; > drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); > - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); > + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); > priv->num_pipes++; > #ifdef CONFIG_MTK_CMDQ > mtk_crtc->cmdq_client = > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 9cc12af..2fd52ba 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -38,7 +38,15 @@ > #define CCORR_EN BIT(0) > #define DISP_CCORR_CFG 0x0020 > #define CCORR_RELAY_MODE BIT(0) > +#define CCORR_ENGINE_EN BIT(1) > +#define CCORR_GAMMA_OFF BIT(2) > +#define CCORR_WGAMUT_SRC_CLIP BIT(3) > #define DISP_CCORR_SIZE 0x0030 > +#define DISP_CCORR_COEF_0 0x0080 > +#define DISP_CCORR_COEF_1 0x0084 > +#define DISP_CCORR_COEF_2 0x0088 > +#define DISP_CCORR_COEF_3 0x008C > +#define DISP_CCORR_COEF_4 0x0090 > > #define DISP_DITHER_EN 0x0000 > #define DITHER_EN BIT(0) > @@ -187,7 +195,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > { > mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE); > - mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG); > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG); > } > > static void mtk_ccorr_start(struct mtk_ddp_comp *comp) > @@ -200,6 +208,56 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp) > writel_relaxed(0x0, comp->regs + DISP_CCORR_EN); > } > > +/* Converts a DRM S31.32 value to the HW S0.11 format. */ > +static u16 mtk_ctm_s31_32_to_s0_11(u64 in) > +{ > + u16 r; > + > + /* Sign bit. */ > + r = in & BIT_ULL(63) ? BIT(11) : 0; > + > + if ((in & GENMASK_ULL(62, 33)) > 0) { if ((in & GENMASK_ULL(62, 32)) > 0) { > + /* We have zero integer bits so we can only saturate here. */ > + r |= GENMASK(10, 0); > + } else { > + /* Otherwise take the 9 most important fractional bits. */ > + r |= (in >> 22) & GENMASK(10, 0); r |= (in >> 21) & GENMASK(10, 0); Regards, CK > + } > + > + return r; > +} > + > +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp, > + struct drm_crtc_state *state > + struct cmdq_pkt *cmdq_pkt) > +{ > + struct drm_property_blob *blob = state->ctm; > + struct drm_color_ctm *ctm; > + const u64 *input; > + uint16_t coeffs[9] = { 0 }; > + int i; > + > + if (!blob) > + return; > + > + ctm = (struct drm_color_ctm *)blob->data; > + input = ctm->matrix; > + > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) > + coeffs[i] = mtk_ctm_s31_32_to_s0_11(input[i]); > + > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > + comp, DISP_CCORR_COEF_0); > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > + comp, DISP_CCORR_COEF_1); > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > + comp, DISP_CCORR_COEF_2); > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > + comp, DISP_CCORR_COEF_3); > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > + comp, DISP_CCORR_COEF_4); > +} > + > static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -269,6 +327,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp, > .config = mtk_ccorr_config, > .start = mtk_ccorr_start, > .stop = mtk_ccorr_stop, > + .ctm_set = mtk_ccorr_ctm_set, > }; > > static const struct mtk_ddp_comp_funcs ddp_dither = { > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index 5b0a3d4..4e3e5aa 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -95,6 +95,9 @@ struct mtk_ddp_comp_funcs { > struct cmdq_pkt *cmdq_pkt); > void (*bgclr_in_on)(struct mtk_ddp_comp *comp); > void (*bgclr_in_off)(struct mtk_ddp_comp *comp); > + void (*ctm_set)(struct mtk_ddp_comp *comp, > + struct drm_crtc_state *state > + struct cmdq_pkt *cmdq_pkt); > }; > > struct mtk_ddp_comp { > @@ -213,6 +216,14 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp) > comp->funcs->bgclr_in_off(comp); > } > > +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp, > + struct drm_crtc_state *state > + struct cmdq_pkt *cmdq_pkt) > +{ > + if (comp->funcs && comp->funcs->ctm_set) > + comp->funcs->ctm_set(comp, state); > +} > + > int mtk_ddp_comp_get_id(struct device_node *node, > enum mtk_ddp_comp_type comp_type); > int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node, From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67068C432C0 for ; Tue, 3 Dec 2019 05:30:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3F0EC2068E for ; Tue, 3 Dec 2019 05:30:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3F0EC2068E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E6B789EB4; Tue, 3 Dec 2019 05:30:21 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [1.203.163.81]) by gabe.freedesktop.org (Postfix) with ESMTP id 8231C89EB4 for ; Tue, 3 Dec 2019 05:30:20 +0000 (UTC) X-UUID: b043a17ac2754401ab48507795c373b4-20191203 X-UUID: b043a17ac2754401ab48507795c373b4-20191203 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1826436254; Tue, 03 Dec 2019 13:20:11 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 Dec 2019 13:19:17 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 3 Dec 2019 13:19:52 +0800 Message-ID: <1575350410.31483.5.camel@mtksdaap41> Subject: Re: [PATCH v2] drm/mediatek: add ctm property support From: CK Hu To: Date: Tue, 3 Dec 2019 13:20:10 +0800 In-Reply-To: <1575277423-31182-1-git-send-email-yongqiang.niu@mediatek.com> References: <1575277423-31182-1-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 91EF239877E5336093CDE7FE8F20BECC4E7AD49A185B12DDB0DBD8016543D4DC2000:8 X-MTK: N X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=NgsysKXbS5nlDOD3N4g0hN4iMinhHgqdb3oRzZLJHmA=; b=BxUbdzs8rfhBzS3w1ACTcIaHIYptfsfdrqnb0K3WCO1NQl4CY0A3IuoTC0UjXkwN10/5Z4NlccmV+XX72UoQEFQwZGK+QhJbsGqTPZEiPQKudXPdMPECKMwuYRTelK5oCs8pW5JcLh0A97qnOaMRjmSzx9bfCN/yQgPepdI9XDU=; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Message-ID: <20191203052010.fwm8H-YvWbi29fSLLyU_jH3DJXlYtI_t8BVpU2uxJpo@z> SGksIFlvbmdxaWFuZzoNCg0KT24gTW9uLCAyMDE5LTEyLTAyIGF0IDE3OjAzICswODAwLCB5b25n cWlhbmcubml1QG1lZGlhdGVrLmNvbSB3cm90ZToNCj4gRnJvbTogWW9uZ3FpYW5nIE5pdSA8eW9u Z3FpYW5nLm5pdUBtZWRpYXRlay5jb20+DQo+IA0KPiBhZGQgY3RtIHByb3BlcnR5IHN1cHBvcnQN Cj4gDQo+IENoYW5nZS1JZDogSTgxMTFkYTdiMzA5YjE4MDljNjMwMmU3NzQ4ZGQ5ZmQwNmRjOTdi ZGUNCg0KUmVtb3ZlIHRoaXMgQ2hhbmdlLUlkLg0KDQo+IFNpZ25lZC1vZmYtYnk6IFlvbmdxaWFu ZyBOaXUgPHlvbmdxaWFuZy5uaXVAbWVkaWF0ZWsuY29tPg0KPiAtLS0NCj4gIGRyaXZlcnMvZ3B1 L2RybS9tZWRpYXRlay9tdGtfZHJtX2NydGMuYyAgICAgfCAxNSArKysrKystDQo+ICBkcml2ZXJz L2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jIHwgNjEgKysrKysrKysrKysrKysr KysrKysrKysrKysrKy0NCj4gIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9j b21wLmggfCAxMSArKysrKysNCj4gIDMgZmlsZXMgY2hhbmdlZCwgODQgaW5zZXJ0aW9ucygrKSwg MyBkZWxldGlvbnMoLSkNCj4gDQo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0 ZWsvbXRrX2RybV9jcnRjLmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9jcnRj LmMNCj4gaW5kZXggNGZiMzQ2Yy4uMTJkYzY4NCAxMDA2NDQNCj4gLS0tIGEvZHJpdmVycy9ncHUv ZHJtL21lZGlhdGVrL210a19kcm1fY3J0Yy5jDQo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9tdGtfZHJtX2NydGMuYw0KPiBAQCAtNjY2LDEwICs2NjYsMTMgQEAgc3RhdGljIHZvaWQg bXRrX2RybV9jcnRjX2F0b21pY19mbHVzaChzdHJ1Y3QgZHJtX2NydGMgKmNydGMsDQo+ICAJaW50 IGk7DQo+ICANCj4gIAlpZiAoY3J0Yy0+c3RhdGUtPmNvbG9yX21nbXRfY2hhbmdlZCkNCj4gLQkJ Zm9yIChpID0gMDsgaSA8IG10a19jcnRjLT5kZHBfY29tcF9ucjsgaSsrKQ0KPiArCQlmb3IgKGkg PSAwOyBpIDwgbXRrX2NydGMtPmRkcF9jb21wX25yOyBpKyspIHsNCj4gIAkJCW10a19kZHBfZ2Ft bWFfc2V0KG10a19jcnRjLT5kZHBfY29tcFtpXSwNCj4gIAkJCQkJICBjcnRjLT5zdGF0ZSwNCj4g IAkJCQkJICBtdGtfY3J0Y19zdGF0ZS0+Y21kcV9oYW5kbGUpOw0KPiArCQkJbXRrX2RkcF9jdG1f c2V0KG10a19jcnRjLT5kZHBfY29tcFtpXSwgY3J0Yy0+c3RhdGUpOw0KDQpTb3JyeSwgSSdtIG5v dCBub3RpY2VkIHRoYXQgdGhlIGNvZGUgaGVyZSB3b3VsZCBub3Qgd3JpdGUgcmVnaXN0ZXIgaW4N CnZibGFuayBwZXJpb2QuIElmIGN0bSBjb3VsZCBiZSBzZXQgb3V0IG9mIHZibGFuayBwZXJpb2Qs IHBsYWNlIHRoZSBjb2RlDQpoZXJlIGFuZCBkbyBub3QgbmVlZCB0byBzdXBwb3J0IGNtZHEuIElm IGN0bSBzaG91bGQgYmUgc2V0IGluc2lkZSB2YmxhbmsNCnBlcmlvZCwgbW92ZSB0aGUgY29kZSB0 byBtdGtfY3J0Y19kZHBfY29uZmlnKCkgYW5kIHN1cHBvcnQgY21kcQ0KaW50ZXJmYWNlLg0KDQo+ ICsJCX0NCj4gKw0KPiAgI2lmZGVmIENPTkZJR19NVEtfQ01EUQ0KPiAgCWlmIChtdGtfY3J0Yy0+ Y21kcV9jbGllbnQpIHsNCj4gIAkJZHJtX2F0b21pY19zdGF0ZV9nZXQob2xkX2F0b21pY19zdGF0 ZSk7DQo+IEBAIC04MTksNiArODIyLDggQEAgaW50IG10a19kcm1fY3J0Y19jcmVhdGUoc3RydWN0 IGRybV9kZXZpY2UgKmRybV9kZXYsDQo+ICAJaW50IHBpcGUgPSBwcml2LT5udW1fcGlwZXM7DQo+ ICAJaW50IHJldDsNCj4gIAlpbnQgaTsNCj4gKwlib29sIGhhc19jdG0gPSBmYWxzZTsNCj4gKwl1 aW50IGdhbW1hX2x1dF9zaXplID0gMDsNCj4gIA0KPiAgCWlmICghcGF0aCkNCj4gIAkJcmV0dXJu IDA7DQo+IEBAIC04NzAsNiArODc1LDEyIEBAIGludCBtdGtfZHJtX2NydGNfY3JlYXRlKHN0cnVj dCBkcm1fZGV2aWNlICpkcm1fZGV2LA0KPiAgCQl9DQo+ICANCj4gIAkJbXRrX2NydGMtPmRkcF9j b21wW2ldID0gY29tcDsNCj4gKw0KPiArCQlpZiAoY29tcF9pZCA9PSBERFBfQ09NUE9ORU5UX0ND T1JSKQ0KPiArCQkJaGFzX2N0bSA9IHRydWU7DQo+ICsNCj4gKwkJaWYgKGNvbXBfaWQgPT0gRERQ X0NPTVBPTkVOVF9HQU1NQSkNCj4gKwkJCWdhbW1hX2x1dF9zaXplID0gTVRLX0xVVF9TSVpFOw0K PiAgCX0NCj4gIA0KPiAgCWZvciAoaSA9IDA7IGkgPCBtdGtfY3J0Yy0+ZGRwX2NvbXBfbnI7IGkr KykNCj4gQEAgLTg5MSw3ICs5MDIsNyBAQCBpbnQgbXRrX2RybV9jcnRjX2NyZWF0ZShzdHJ1Y3Qg ZHJtX2RldmljZSAqZHJtX2RldiwNCj4gIAlpZiAocmV0IDwgMCkNCj4gIAkJcmV0dXJuIHJldDsN Cj4gIAlkcm1fbW9kZV9jcnRjX3NldF9nYW1tYV9zaXplKCZtdGtfY3J0Yy0+YmFzZSwgTVRLX0xV VF9TSVpFKTsNCj4gLQlkcm1fY3J0Y19lbmFibGVfY29sb3JfbWdtdCgmbXRrX2NydGMtPmJhc2Us IDAsIGZhbHNlLCBNVEtfTFVUX1NJWkUpOw0KPiArCWRybV9jcnRjX2VuYWJsZV9jb2xvcl9tZ210 KCZtdGtfY3J0Yy0+YmFzZSwgMCwgaGFzX2N0bSwgZ2FtbWFfbHV0X3NpemUpOw0KPiAgCXByaXYt Pm51bV9waXBlcysrOw0KPiAgI2lmZGVmIENPTkZJR19NVEtfQ01EUQ0KPiAgCW10a19jcnRjLT5j bWRxX2NsaWVudCA9DQo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRr X2RybV9kZHBfY29tcC5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2Nv bXAuYw0KPiBpbmRleCA5Y2MxMmFmLi4yZmQ1MmJhIDEwMDY0NA0KPiAtLS0gYS9kcml2ZXJzL2dw dS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jDQo+ICsrKyBiL2RyaXZlcnMvZ3B1L2Ry bS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmMNCj4gQEAgLTM4LDcgKzM4LDE1IEBADQo+ICAj ZGVmaW5lIENDT1JSX0VOCQkJCUJJVCgwKQ0KPiAgI2RlZmluZSBESVNQX0NDT1JSX0NGRwkJCQkw eDAwMjANCj4gICNkZWZpbmUgQ0NPUlJfUkVMQVlfTU9ERQkJCUJJVCgwKQ0KPiArI2RlZmluZSBD Q09SUl9FTkdJTkVfRU4JCQkJQklUKDEpDQo+ICsjZGVmaW5lIENDT1JSX0dBTU1BX09GRgkJCQlC SVQoMikNCj4gKyNkZWZpbmUgQ0NPUlJfV0dBTVVUX1NSQ19DTElQCQkJQklUKDMpDQo+ICAjZGVm aW5lIERJU1BfQ0NPUlJfU0laRQkJCQkweDAwMzANCj4gKyNkZWZpbmUgRElTUF9DQ09SUl9DT0VG XzAJCQkweDAwODANCj4gKyNkZWZpbmUgRElTUF9DQ09SUl9DT0VGXzEJCQkweDAwODQNCj4gKyNk ZWZpbmUgRElTUF9DQ09SUl9DT0VGXzIJCQkweDAwODgNCj4gKyNkZWZpbmUgRElTUF9DQ09SUl9D T0VGXzMJCQkweDAwOEMNCj4gKyNkZWZpbmUgRElTUF9DQ09SUl9DT0VGXzQJCQkweDAwOTANCj4g IA0KPiAgI2RlZmluZSBESVNQX0RJVEhFUl9FTgkJCQkweDAwMDANCj4gICNkZWZpbmUgRElUSEVS X0VOCQkJCUJJVCgwKQ0KPiBAQCAtMTg3LDcgKzE5NSw3IEBAIHN0YXRpYyB2b2lkIG10a19jY29y cl9jb25maWcoc3RydWN0IG10a19kZHBfY29tcCAqY29tcCwgdW5zaWduZWQgaW50IHcsDQo+ICAJ CQkgICAgIHVuc2lnbmVkIGludCBicGMsIHN0cnVjdCBjbWRxX3BrdCAqY21kcV9wa3QpDQo+ICB7 DQo+ICAJbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgaCA8PCAxNiB8IHcsIGNvbXAsIERJU1BfQ0NP UlJfU0laRSk7DQo+IC0JbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgQ0NPUlJfUkVMQVlfTU9ERSwg Y29tcCwgRElTUF9DQ09SUl9DRkcpOw0KPiArCW10a19kZHBfd3JpdGUoY21kcV9wa3QsIENDT1JS X0VOR0lORV9FTiwgY29tcCwgRElTUF9DQ09SUl9DRkcpOw0KPiAgfQ0KPiAgDQo+ICBzdGF0aWMg dm9pZCBtdGtfY2NvcnJfc3RhcnQoc3RydWN0IG10a19kZHBfY29tcCAqY29tcCkNCj4gQEAgLTIw MCw2ICsyMDgsNTYgQEAgc3RhdGljIHZvaWQgbXRrX2Njb3JyX3N0b3Aoc3RydWN0IG10a19kZHBf Y29tcCAqY29tcCkNCj4gIAl3cml0ZWxfcmVsYXhlZCgweDAsIGNvbXAtPnJlZ3MgKyBESVNQX0ND T1JSX0VOKTsNCj4gIH0NCj4gIA0KPiArLyogQ29udmVydHMgYSBEUk0gUzMxLjMyIHZhbHVlIHRv IHRoZSBIVyBTMC4xMSBmb3JtYXQuICovDQo+ICtzdGF0aWMgdTE2IG10a19jdG1fczMxXzMyX3Rv X3MwXzExKHU2NCBpbikNCj4gK3sNCj4gKwl1MTYgcjsNCj4gKw0KPiArCS8qIFNpZ24gYml0LiAq Lw0KPiArCXIgPSBpbiAmIEJJVF9VTEwoNjMpID8gQklUKDExKSA6IDA7DQo+ICsNCj4gKwlpZiAo KGluICYgR0VOTUFTS19VTEwoNjIsIDMzKSkgPiAwKSB7DQoNCmlmICgoaW4gJiBHRU5NQVNLX1VM TCg2MiwgMzIpKSA+IDApIHsNCg0KPiArCQkvKiBXZSBoYXZlIHplcm8gaW50ZWdlciBiaXRzIHNv IHdlIGNhbiBvbmx5IHNhdHVyYXRlIGhlcmUuICovDQo+ICsJCXIgfD0gR0VOTUFTSygxMCwgMCk7 DQo+ICsJfSBlbHNlIHsNCj4gKwkJLyogT3RoZXJ3aXNlIHRha2UgdGhlIDkgbW9zdCBpbXBvcnRh bnQgZnJhY3Rpb25hbCBiaXRzLiAqLw0KPiArCQlyIHw9IChpbiA+PiAyMikgJiBHRU5NQVNLKDEw LCAwKTsNCg0KciB8PSAoaW4gPj4gMjEpICYgR0VOTUFTSygxMCwgMCk7DQoNClJlZ2FyZHMsDQpD Sw0KDQo+ICsJfQ0KPiArDQo+ICsJcmV0dXJuIHI7DQo+ICt9DQo+ICsNCj4gK3N0YXRpYyB2b2lk IG10a19jY29ycl9jdG1fc2V0KHN0cnVjdCBtdGtfZGRwX2NvbXAgKmNvbXAsDQo+ICsJCQkgICAg ICBzdHJ1Y3QgZHJtX2NydGNfc3RhdGUgKnN0YXRlDQo+ICsJCQkgICAgICBzdHJ1Y3QgY21kcV9w a3QgKmNtZHFfcGt0KQ0KPiArew0KPiArCXN0cnVjdCBkcm1fcHJvcGVydHlfYmxvYiAqYmxvYiA9 IHN0YXRlLT5jdG07DQo+ICsJc3RydWN0IGRybV9jb2xvcl9jdG0gKmN0bTsNCj4gKwljb25zdCB1 NjQgKmlucHV0Ow0KPiArCXVpbnQxNl90IGNvZWZmc1s5XSA9IHsgMCB9Ow0KPiArCWludCBpOw0K PiArDQo+ICsJaWYgKCFibG9iKQ0KPiArCQlyZXR1cm47DQo+ICsNCj4gKwljdG0gPSAoc3RydWN0 IGRybV9jb2xvcl9jdG0gKilibG9iLT5kYXRhOw0KPiArCWlucHV0ID0gY3RtLT5tYXRyaXg7DQo+ ICsNCj4gKwlmb3IgKGkgPSAwOyBpIDwgQVJSQVlfU0laRShjb2VmZnMpOyBpKyspDQo+ICsJCWNv ZWZmc1tpXSA9IG10a19jdG1fczMxXzMyX3RvX3MwXzExKGlucHV0W2ldKTsNCj4gKw0KPiArCW10 a19kZHBfd3JpdGUoY21kcV9wa3QsIGNvZWZmc1swXSA8PCAxNiB8IGNvZWZmc1sxXSwNCj4gKwkJ ICAgICAgY29tcCwgRElTUF9DQ09SUl9DT0VGXzApOw0KPiArCW10a19kZHBfd3JpdGUoY21kcV9w a3QsIGNvZWZmc1syXSA8PCAxNiB8IGNvZWZmc1szXSwNCj4gKwkJICAgICAgY29tcCwgRElTUF9D Q09SUl9DT0VGXzEpOw0KPiArCW10a19kZHBfd3JpdGUoY21kcV9wa3QsIGNvZWZmc1s0XSA8PCAx NiB8IGNvZWZmc1s1XSwNCj4gKwkJICAgICAgY29tcCwgRElTUF9DQ09SUl9DT0VGXzIpOw0KPiAr CW10a19kZHBfd3JpdGUoY21kcV9wa3QsIGNvZWZmc1s2XSA8PCAxNiB8IGNvZWZmc1s3XSwNCj4g KwkJICAgICAgY29tcCwgRElTUF9DQ09SUl9DT0VGXzMpOw0KPiArCW10a19kZHBfd3JpdGUoY21k cV9wa3QsIGNvZWZmc1s4XSA8PCAxNiwNCj4gKwkJICAgICAgY29tcCwgRElTUF9DQ09SUl9DT0VG XzQpOw0KPiArfQ0KPiArDQo+ICBzdGF0aWMgdm9pZCBtdGtfZGl0aGVyX2NvbmZpZyhzdHJ1Y3Qg bXRrX2RkcF9jb21wICpjb21wLCB1bnNpZ25lZCBpbnQgdywNCj4gIAkJCSAgICAgIHVuc2lnbmVk IGludCBoLCB1bnNpZ25lZCBpbnQgdnJlZnJlc2gsDQo+ICAJCQkgICAgICB1bnNpZ25lZCBpbnQg YnBjLCBzdHJ1Y3QgY21kcV9wa3QgKmNtZHFfcGt0KQ0KPiBAQCAtMjY5LDYgKzMyNyw3IEBAIHN0 YXRpYyB2b2lkIG10a19nYW1tYV9zZXQoc3RydWN0IG10a19kZHBfY29tcCAqY29tcCwNCj4gIAku Y29uZmlnID0gbXRrX2Njb3JyX2NvbmZpZywNCj4gIAkuc3RhcnQgPSBtdGtfY2NvcnJfc3RhcnQs DQo+ICAJLnN0b3AgPSBtdGtfY2NvcnJfc3RvcCwNCj4gKwkuY3RtX3NldCA9IG10a19jY29ycl9j dG1fc2V0LA0KPiAgfTsNCj4gIA0KPiAgc3RhdGljIGNvbnN0IHN0cnVjdCBtdGtfZGRwX2NvbXBf ZnVuY3MgZGRwX2RpdGhlciA9IHsNCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9tdGtfZHJtX2RkcF9jb21wLmggYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2Ry bV9kZHBfY29tcC5oDQo+IGluZGV4IDViMGEzZDQuLjRlM2U1YWEgMTAwNjQ0DQo+IC0tLSBhL2Ry aXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmgNCj4gKysrIGIvZHJpdmVy cy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2NvbXAuaA0KPiBAQCAtOTUsNiArOTUsOSBA QCBzdHJ1Y3QgbXRrX2RkcF9jb21wX2Z1bmNzIHsNCj4gIAkJCSAgc3RydWN0IGNtZHFfcGt0ICpj bWRxX3BrdCk7DQo+ICAJdm9pZCAoKmJnY2xyX2luX29uKShzdHJ1Y3QgbXRrX2RkcF9jb21wICpj b21wKTsNCj4gIAl2b2lkICgqYmdjbHJfaW5fb2ZmKShzdHJ1Y3QgbXRrX2RkcF9jb21wICpjb21w KTsNCj4gKwl2b2lkICgqY3RtX3NldCkoc3RydWN0IG10a19kZHBfY29tcCAqY29tcCwNCj4gKwkJ CXN0cnVjdCBkcm1fY3J0Y19zdGF0ZSAqc3RhdGUNCj4gKwkJCXN0cnVjdCBjbWRxX3BrdCAqY21k cV9wa3QpOw0KPiAgfTsNCj4gIA0KPiAgc3RydWN0IG10a19kZHBfY29tcCB7DQo+IEBAIC0yMTMs NiArMjE2LDE0IEBAIHN0YXRpYyBpbmxpbmUgdm9pZCBtdGtfZGRwX2NvbXBfYmdjbHJfaW5fb2Zm KHN0cnVjdCBtdGtfZGRwX2NvbXAgKmNvbXApDQo+ICAJCWNvbXAtPmZ1bmNzLT5iZ2Nscl9pbl9v ZmYoY29tcCk7DQo+ICB9DQo+ICANCj4gK3N0YXRpYyBpbmxpbmUgdm9pZCBtdGtfZGRwX2N0bV9z ZXQoc3RydWN0IG10a19kZHBfY29tcCAqY29tcCwNCj4gKwkJCQkgICBzdHJ1Y3QgZHJtX2NydGNf c3RhdGUgKnN0YXRlDQo+ICsJCQkJICAgc3RydWN0IGNtZHFfcGt0ICpjbWRxX3BrdCkNCj4gK3sN Cj4gKwlpZiAoY29tcC0+ZnVuY3MgJiYgY29tcC0+ZnVuY3MtPmN0bV9zZXQpDQo+ICsJCWNvbXAt PmZ1bmNzLT5jdG1fc2V0KGNvbXAsIHN0YXRlKTsNCj4gK30NCj4gKw0KPiAgaW50IG10a19kZHBf Y29tcF9nZXRfaWQoc3RydWN0IGRldmljZV9ub2RlICpub2RlLA0KPiAgCQkJZW51bSBtdGtfZGRw X2NvbXBfdHlwZSBjb21wX3R5cGUpOw0KPiAgaW50IG10a19kZHBfY29tcF9pbml0KHN0cnVjdCBk ZXZpY2UgKmRldiwgc3RydWN0IGRldmljZV9ub2RlICpjb21wX25vZGUsDQoNCl9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxp c3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNr dG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbA==