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+0800 Message-ID: <1575600902.6328.11.camel@mtksdaap41> Subject: Re: [PATCH v4 7/7] drm/mediatek: apply CMDQ control flow From: CK Hu To: Bibby Hsieh Date: Fri, 6 Dec 2019 10:55:02 +0800 In-Reply-To: <20191205092749.4021-8-bibby.hsieh@mediatek.com> References: <20191205092749.4021-1-bibby.hsieh@mediatek.com> <20191205092749.4021-8-bibby.hsieh@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191205_185514_000334_F7C2A760 X-CRM114-Status: GOOD ( 16.58 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drinkcat@chromium.org, Yongqiang Niu , srv_heupstream@mediatek.com, David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, tfiga@chromium.org, Thierry Reding , linux-mediatek@lists.infradead.org, Philipp Zabel , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, Bibby: On Thu, 2019-12-05 at 17:27 +0800, Bibby Hsieh wrote: > Unlike other SoCs, MT8183 does not have "shadow" > registers for performaing an atomic video mode > set or page flip at vblank/vsync. > > The CMDQ (Commend Queue) in MT8183 is used to help > update all relevant display controller registers > with critical time limation. Reviewed-by: CK Hu > > Signed-off-by: YT Shen > Signed-off-by: CK Hu > Signed-off-by: Philipp Zabel > Signed-off-by: Bibby Hsieh > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 56 +++++++++++++++++++++---- > 1 file changed, 49 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index 8c6231ed6f55..496dffe962af 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -12,6 +12,8 @@ > #include > #include > #include > +#include > +#include > > #include "mtk_drm_drv.h" > #include "mtk_drm_crtc.h" > @@ -43,6 +45,9 @@ struct mtk_drm_crtc { > bool pending_planes; > bool pending_async_planes; > > + struct cmdq_client *cmdq_client; > + u32 cmdq_event; > + > void __iomem *config_regs; > const struct mtk_mmsys_reg_data *mmsys_reg_data; > struct mtk_disp_mutex *mutex; > @@ -234,6 +239,13 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, > return NULL; > } > > +#ifdef CONFIG_MTK_CMDQ > +static void ddp_cmdq_cb(struct cmdq_cb_data data) > +{ > + cmdq_pkt_destroy(data.data); > +} > +#endif > + > static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) > { > struct drm_crtc *crtc = &mtk_crtc->base; > @@ -378,7 +390,8 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) > } > } > > -static void mtk_crtc_ddp_config(struct drm_crtc *crtc) > +static void mtk_crtc_ddp_config(struct drm_crtc *crtc, > + struct cmdq_pkt *cmdq_handle) > { > struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); > struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); > @@ -394,7 +407,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) > if (state->pending_config) { > mtk_ddp_comp_config(comp, state->pending_width, > state->pending_height, > - state->pending_vrefresh, 0, NULL); > + state->pending_vrefresh, 0, > + cmdq_handle); > > state->pending_config = false; > } > @@ -414,7 +428,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) > > if (comp) > mtk_ddp_comp_layer_config(comp, local_layer, > - plane_state, NULL); > + plane_state, > + cmdq_handle); > plane_state->pending.config = false; > } > mtk_crtc->pending_planes = false; > @@ -435,7 +450,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) > > if (comp) > mtk_ddp_comp_layer_config(comp, local_layer, > - plane_state, NULL); > + plane_state, > + cmdq_handle); > plane_state->pending.async_config = false; > } > mtk_crtc->pending_async_planes = false; > @@ -444,6 +460,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) > > static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) > { > + struct cmdq_pkt *cmdq_handle; > struct drm_crtc *crtc = &mtk_crtc->base; > struct mtk_drm_private *priv = crtc->dev->dev_private; > unsigned int pending_planes = 0, pending_async_planes = 0; > @@ -472,9 +489,18 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) > > if (priv->data->shadow_register) { > mtk_disp_mutex_acquire(mtk_crtc->mutex); > - mtk_crtc_ddp_config(crtc); > + mtk_crtc_ddp_config(crtc, NULL); > mtk_disp_mutex_release(mtk_crtc->mutex); > } > +#ifdef CONFIG_MTK_CMDQ > + if (mtk_crtc->cmdq_client) { > + cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); > + cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); > + cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event); > + mtk_crtc_ddp_config(crtc, cmdq_handle); > + cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); > + } > +#endif > mutex_unlock(&mtk_crtc->hw_lock); > } > > @@ -643,8 +669,8 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) > struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); > struct mtk_drm_private *priv = crtc->dev->dev_private; > > - if (!priv->data->shadow_register) > - mtk_crtc_ddp_config(crtc); > + if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) > + mtk_crtc_ddp_config(crtc, NULL); > > mtk_drm_finish_page_flip(mtk_crtc); > } > @@ -787,5 +813,21 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > priv->num_pipes++; > mutex_init(&mtk_crtc->hw_lock); > > +#ifdef CONFIG_MTK_CMDQ > + mtk_crtc->cmdq_client = > + cmdq_mbox_create(dev, drm_crtc_index(&mtk_crtc->base), > + 2000); > + if (IS_ERR(mtk_crtc->cmdq_client)) { > + dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", > + drm_crtc_index(&mtk_crtc->base)); > + mtk_crtc->cmdq_client = NULL; > + } > + ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events", > + drm_crtc_index(&mtk_crtc->base), > + &mtk_crtc->cmdq_event); > + if (ret) > + dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", > + drm_crtc_index(&mtk_crtc->base)); > +#endif > return 0; > } _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D6D8C43603 for ; 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Fri, 06 Dec 2019 02:55:16 +0000 X-UUID: d625fe20304a4f3db0697edc4ccd42b2-20191205 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=+m0881iTlxWLsLEeydzi6ozs1V2dNGB1CpLzB3Z+JSE=; b=i0LWQ+BHy0VCdjk3SADTwVtO7KBv5aPsls+cJ0E6hRYE0C2bMcHEfiIGgeWUu0iVO9wO+FsOqqjdOzo+Usdl5ZnwUQ7IZuusNw18tHxOWHFb6qUZs00+DDpR9GLuovKIXT430VlONCpN9RGy1boHke0IrBhuZ6czMkd65R5BYvg=; X-UUID: d625fe20304a4f3db0697edc4ccd42b2-20191205 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 778458383; Thu, 05 Dec 2019 18:55:05 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 5 Dec 2019 18:55:52 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 6 Dec 2019 10:54:57 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 6 Dec 2019 10:54:27 +0800 Message-ID: <1575600902.6328.11.camel@mtksdaap41> Subject: Re: [PATCH v4 7/7] drm/mediatek: apply CMDQ control flow From: CK Hu To: Bibby Hsieh Date: Fri, 6 Dec 2019 10:55:02 +0800 In-Reply-To: <20191205092749.4021-8-bibby.hsieh@mediatek.com> References: <20191205092749.4021-1-bibby.hsieh@mediatek.com> <20191205092749.4021-8-bibby.hsieh@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191205_185514_000334_F7C2A760 X-CRM114-Status: GOOD ( 16.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drinkcat@chromium.org, Yongqiang Niu , srv_heupstream@mediatek.com, David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, tfiga@chromium.org, YT Shen , Thierry Reding , linux-mediatek@lists.infradead.org, Philipp Zabel , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Bibby: On Thu, 2019-12-05 at 17:27 +0800, Bibby Hsieh wrote: > Unlike other SoCs, MT8183 does not have "shadow" > registers for performaing an atomic video mode > set or page flip at vblank/vsync. > > The CMDQ (Commend Queue) in MT8183 is used to help > update all relevant display controller registers > with critical time limation. Reviewed-by: CK Hu > > Signed-off-by: YT Shen > Signed-off-by: CK Hu > Signed-off-by: Philipp Zabel > Signed-off-by: Bibby Hsieh > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 56 +++++++++++++++++++++---- > 1 file changed, 49 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index 8c6231ed6f55..496dffe962af 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -12,6 +12,8 @@ > #include > #include > #include > +#include > +#include > > #include "mtk_drm_drv.h" > #include "mtk_drm_crtc.h" > @@ -43,6 +45,9 @@ struct mtk_drm_crtc { > bool pending_planes; > bool pending_async_planes; > > + struct cmdq_client *cmdq_client; > + u32 cmdq_event; > + > void __iomem *config_regs; > const struct mtk_mmsys_reg_data *mmsys_reg_data; > struct mtk_disp_mutex *mutex; > @@ -234,6 +239,13 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, > return NULL; > } > > +#ifdef CONFIG_MTK_CMDQ > +static void ddp_cmdq_cb(struct cmdq_cb_data data) > +{ > + cmdq_pkt_destroy(data.data); > +} > +#endif > + > static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) > { > struct drm_crtc *crtc = &mtk_crtc->base; > @@ -378,7 +390,8 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) > } > } > > -static void mtk_crtc_ddp_config(struct drm_crtc *crtc) > +static void mtk_crtc_ddp_config(struct drm_crtc *crtc, > + struct cmdq_pkt *cmdq_handle) > { > struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); > struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); > @@ -394,7 +407,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) > if (state->pending_config) { > mtk_ddp_comp_config(comp, state->pending_width, > state->pending_height, > - state->pending_vrefresh, 0, NULL); > + state->pending_vrefresh, 0, > + cmdq_handle); > > state->pending_config = false; > } > @@ -414,7 +428,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) > > if (comp) > mtk_ddp_comp_layer_config(comp, local_layer, > - plane_state, NULL); > + plane_state, > + cmdq_handle); > plane_state->pending.config = false; > } > mtk_crtc->pending_planes = false; > @@ -435,7 +450,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) > > if (comp) > mtk_ddp_comp_layer_config(comp, local_layer, > - plane_state, NULL); > + plane_state, > + cmdq_handle); > plane_state->pending.async_config = false; > } > mtk_crtc->pending_async_planes = false; > @@ -444,6 +460,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) > > static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) > { > + struct cmdq_pkt *cmdq_handle; > struct drm_crtc *crtc = &mtk_crtc->base; > struct mtk_drm_private *priv = crtc->dev->dev_private; > unsigned int pending_planes = 0, pending_async_planes = 0; > @@ -472,9 +489,18 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) > > if (priv->data->shadow_register) { > mtk_disp_mutex_acquire(mtk_crtc->mutex); > - mtk_crtc_ddp_config(crtc); > + mtk_crtc_ddp_config(crtc, NULL); > mtk_disp_mutex_release(mtk_crtc->mutex); > } > +#ifdef CONFIG_MTK_CMDQ > + if (mtk_crtc->cmdq_client) { > + cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); > + cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); > + cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event); > + mtk_crtc_ddp_config(crtc, cmdq_handle); > + cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); > + } > +#endif > mutex_unlock(&mtk_crtc->hw_lock); > } > > @@ -643,8 +669,8 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) > struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); > struct mtk_drm_private *priv = crtc->dev->dev_private; > > - if (!priv->data->shadow_register) > - mtk_crtc_ddp_config(crtc); > + if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) > + mtk_crtc_ddp_config(crtc, NULL); > > mtk_drm_finish_page_flip(mtk_crtc); > } > @@ -787,5 +813,21 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > priv->num_pipes++; > mutex_init(&mtk_crtc->hw_lock); > > +#ifdef CONFIG_MTK_CMDQ > + mtk_crtc->cmdq_client = > + cmdq_mbox_create(dev, drm_crtc_index(&mtk_crtc->base), > + 2000); > + if (IS_ERR(mtk_crtc->cmdq_client)) { > + dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", > + drm_crtc_index(&mtk_crtc->base)); > + mtk_crtc->cmdq_client = NULL; > + } > + ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events", > + drm_crtc_index(&mtk_crtc->base), > + &mtk_crtc->cmdq_event); > + if (ret) > + dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", > + drm_crtc_index(&mtk_crtc->base)); > +#endif > return 0; > } _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 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with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 6 Dec 2019 10:54:27 +0800 Message-ID: <1575600902.6328.11.camel@mtksdaap41> Subject: Re: [PATCH v4 7/7] drm/mediatek: apply CMDQ control flow From: CK Hu To: Bibby Hsieh Date: Fri, 6 Dec 2019 10:55:02 +0800 In-Reply-To: <20191205092749.4021-8-bibby.hsieh@mediatek.com> References: <20191205092749.4021-1-bibby.hsieh@mediatek.com> <20191205092749.4021-8-bibby.hsieh@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=+m0881iTlxWLsLEeydzi6ozs1V2dNGB1CpLzB3Z+JSE=; b=i0LWQ+BHy0VCdjk3SADTwVtO7KBv5aPsls+cJ0E6hRYE0C2bMcHEfiIGgeWUu0iVO9wO+FsOqqjdOzo+Usdl5ZnwUQ7IZuusNw18tHxOWHFb6qUZs00+DDpR9GLuovKIXT430VlONCpN9RGy1boHke0IrBhuZ6czMkd65R5BYvg=; X-BeenThere: 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