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S1727466AbfLJGrd (ORCPT ); Tue, 10 Dec 2019 01:47:33 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:11717 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727384AbfLJGr2 (ORCPT ); Tue, 10 Dec 2019 01:47:28 -0500 X-UUID: 2c0e9786781242198bcd6035e6e66bc2-20191210 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=FaKWV2oOD4uC3oUi5ljCHfnnP7F/NQ0DyNTQFbDfhiY=; b=Xtmdoryf2OTN+TLCVutEnHNC9tH7xKldqSBEyCx4ji9spxt5pptpe1asEmMfCPpn+M03UL+ml4j+YnCeCfn4ZCtdNi6MoSsg1lgKwl5W1L95cMjddBs7A3gu7AJ0TtM6oVU7Lnx2vCCIIh6NnTJXPdQBvbi8StVKhxX8krbohzg=; X-UUID: 2c0e9786781242198bcd6035e6e66bc2-20191210 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 448214538; Tue, 10 Dec 2019 14:47:16 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 10 Dec 2019 14:46:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 10 Dec 2019 14:47:17 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Rob Herring CC: James Liao , Fan Chen , , , , , Weiyi Lu , Yong Wu Subject: [PATCH v9 7/9] soc: mediatek: Add MT8183 scpsys support Date: Tue, 10 Dec 2019 14:46:51 +0800 Message-ID: <1575960413-6900-8-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1575960413-6900-1-git-send-email-weiyi.lu@mediatek.com> References: <1575960413-6900-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 5A1BC3662496BAA5D91E60F4491DD3D7911F6C78A338634B3F73EB58CAEBCD512000:8 X-MTK: N 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(172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 10 Dec 2019 14:46:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 10 Dec 2019 14:47:17 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Rob Herring Subject: [PATCH v9 7/9] soc: mediatek: Add MT8183 scpsys support Date: Tue, 10 Dec 2019 14:46:51 +0800 Message-ID: <1575960413-6900-8-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1575960413-6900-1-git-send-email-weiyi.lu@mediatek.com> References: <1575960413-6900-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 5A1BC3662496BAA5D91E60F4491DD3D7911F6C78A338634B3F73EB58CAEBCD512000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191209_225414_514217_15EB3A55 X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Yong Wu , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add scpsys driver for MT8183 Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 226 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 226 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 0676b46..5a6bf13 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -20,6 +20,7 @@ #include #include #include +#include #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -1131,6 +1132,217 @@ static void mtk_register_power_domains(struct platform_device *pdev, {MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG}, }; +/* + * MT8183 power domain support + */ + +static const struct scp_domain_data scp_domain_data_mt8183[] = { + [MT8183_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = PWR_STATUS_AUDIO, + .ctl_offs = 0x0314, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .basic_clk_id = {"audio", "audio1", "audio2"}, + }, + [MT8183_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = 0x032c, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + BIT(13) | BIT(14), BIT(13) | BIT(14)), + }, + }, + [MT8183_POWER_DOMAIN_MFG_ASYNC] = { + .name = "mfg_async", + .sta_mask = PWR_STATUS_MFG_ASYNC, + .ctl_offs = 0x0334, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .basic_clk_id = {"mfg"}, + }, + [MT8183_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = 0x0338, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_CORE0] = { + .name = "mfg_core0", + .sta_mask = BIT(7), + .ctl_offs = 0x034c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_CORE1] = { + .name = "mfg_core1", + .sta_mask = BIT(20), + .ctl_offs = 0x0310, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_2D] = { + .name = "mfg_2d", + .sta_mask = PWR_STATUS_MFG_2D, + .ctl_offs = 0x0348, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258, + BIT(19) | BIT(20) | BIT(21), + BIT(19) | BIT(20) | BIT(21)), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + BIT(21) | BIT(22), BIT(21) | BIT(22)), + }, + }, + [MT8183_POWER_DOMAIN_DISP] = { + .name = "disp", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = 0x030c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_id = {"mm"}, + .subsys_clk_prefix = "mm", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258, + BIT(16) | BIT(17), BIT(16) | BIT(17)), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + BIT(10) | BIT(11), BIT(10) | BIT(11)), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + GENMASK(7, 0), GENMASK(7, 0)), + }, + }, + [MT8183_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x0344, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_id = {"cam"}, + .subsys_clk_prefix = "cam", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + BIT(4) | BIT(5) | BIT(9) | BIT(13), + BIT(4) | BIT(5) | BIT(9) | BIT(13)), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + BIT(28), BIT(28)), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + BIT(11), 0), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + BIT(3) | BIT(4), BIT(3) | BIT(4)), + }, + }, + [MT8183_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = 0x0308, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_id = {"isp"}, + .subsys_clk_prefix = "isp", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + BIT(3) | BIT(8), BIT(3) | BIT(8)), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + BIT(10), 0), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + BIT(2), BIT(2)), + }, + }, + [MT8183_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = BIT(31), + .ctl_offs = 0x0300, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_table = { + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + BIT(7), BIT(7)), + }, + }, + [MT8183_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = PWR_STATUS_VENC, + .ctl_offs = 0x0304, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bp_table = { + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + BIT(1), BIT(1)), + }, + }, + [MT8183_POWER_DOMAIN_VPU_TOP] = { + .name = "vpu_top", + .sta_mask = BIT(26), + .ctl_offs = 0x0324, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_id = {"vpu", "vpu1"}, + .subsys_clk_prefix = "vpu", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + GENMASK(9, 6) | BIT(12), + GENMASK(9, 6) | BIT(12)), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + BIT(27), BIT(27)), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + BIT(10) | BIT(11), BIT(10) | BIT(11)), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + BIT(5) | BIT(6), BIT(5) | BIT(6)), + }, + }, + [MT8183_POWER_DOMAIN_VPU_CORE0] = { + .name = "vpu_core0", + .sta_mask = BIT(27), + .ctl_offs = 0x33c, + .sram_iso_ctrl = true, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_id = {"vpu2"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + BIT(6), BIT(6)), + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + BIT(0) | BIT(2) | BIT(4), + BIT(0) | BIT(2) | BIT(4)), + }, + }, + [MT8183_POWER_DOMAIN_VPU_CORE1] = { + .name = "vpu_core1", + .sta_mask = BIT(28), + .ctl_offs = 0x0340, + .sram_iso_ctrl = true, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_id = {"vpu3"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + BIT(7), BIT(7)), + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + BIT(1) | BIT(3) | BIT(5), + BIT(1) | BIT(3) | BIT(5)), + }, + }, +}; + +static const struct scp_subdomain scp_subdomain_mt8183[] = { + {MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG}, + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D}, + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0}, + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_CAM}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_ISP}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VDEC}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VENC}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VPU_TOP}, + {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE0}, + {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE1}, +}; + static const struct scp_soc_data mt2701_data = { .domains = scp_domain_data_mt2701, .num_domains = ARRAY_SIZE(scp_domain_data_mt2701), @@ -1197,6 +1409,17 @@ static void mtk_register_power_domains(struct platform_device *pdev, .bus_prot_reg_update = true, }; +static const struct scp_soc_data mt8183_data = { + .domains = scp_domain_data_mt8183, + .num_domains = ARRAY_SIZE(scp_domain_data_mt8183), + .subdomains = scp_subdomain_mt8183, + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8183), + .regs = { + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184 + } +}; + /* * scpsys driver init */ @@ -1221,6 +1444,9 @@ static void mtk_register_power_domains(struct platform_device *pdev, .compatible = "mediatek,mt8173-scpsys", .data = &mt8173_data, }, { + .compatible = "mediatek,mt8183-scpsys", + .data = &mt8183_data, + }, { /* sentinel */ } }; -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90EC7C2D0C4 for ; Tue, 10 Dec 2019 06:56:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher 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(172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 10 Dec 2019 14:46:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 10 Dec 2019 14:47:17 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Rob Herring Subject: [PATCH v9 7/9] soc: mediatek: Add MT8183 scpsys support Date: Tue, 10 Dec 2019 14:46:51 +0800 Message-ID: <1575960413-6900-8-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1575960413-6900-1-git-send-email-weiyi.lu@mediatek.com> References: <1575960413-6900-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 5A1BC3662496BAA5D91E60F4491DD3D7911F6C78A338634B3F73EB58CAEBCD512000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191209_225414_514217_15EB3A55 X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Yong Wu , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add scpsys driver for MT8183 Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 226 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 226 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 0676b46..5a6bf13 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -20,6 +20,7 @@ #include #include #include +#include #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -1131,6 +1132,217 @@ static void mtk_register_power_domains(struct platform_device *pdev, {MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG}, }; +/* + * MT8183 power domain support + */ + +static const struct scp_domain_data scp_domain_data_mt8183[] = { + [MT8183_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = PWR_STATUS_AUDIO, + .ctl_offs = 0x0314, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .basic_clk_id = {"audio", "audio1", "audio2"}, + }, + [MT8183_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = 0x032c, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + BIT(13) | BIT(14), BIT(13) | BIT(14)), + }, + }, + [MT8183_POWER_DOMAIN_MFG_ASYNC] = { + .name = "mfg_async", + .sta_mask = PWR_STATUS_MFG_ASYNC, + .ctl_offs = 0x0334, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .basic_clk_id = {"mfg"}, + }, + [MT8183_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = 0x0338, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_CORE0] = { + .name = "mfg_core0", + .sta_mask = BIT(7), + .ctl_offs = 0x034c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_CORE1] = { + .name = "mfg_core1", + .sta_mask = BIT(20), + .ctl_offs = 0x0310, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_2D] = { + .name = "mfg_2d", + .sta_mask = PWR_STATUS_MFG_2D, + .ctl_offs = 0x0348, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258, + BIT(19) | BIT(20) | BIT(21), + BIT(19) | BIT(20) | BIT(21)), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + BIT(21) | BIT(22), BIT(21) | BIT(22)), + }, + }, + [MT8183_POWER_DOMAIN_DISP] = { + .name = "disp", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = 0x030c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_id = {"mm"}, + .subsys_clk_prefix = "mm", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258, + BIT(16) | BIT(17), BIT(16) | BIT(17)), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + BIT(10) | BIT(11), BIT(10) | BIT(11)), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + GENMASK(7, 0), GENMASK(7, 0)), + }, + }, + [MT8183_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x0344, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_id = {"cam"}, + .subsys_clk_prefix = "cam", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + BIT(4) | BIT(5) | BIT(9) | BIT(13), + BIT(4) | BIT(5) | BIT(9) | BIT(13)), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + BIT(28), BIT(28)), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + BIT(11), 0), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + BIT(3) | BIT(4), BIT(3) | BIT(4)), + }, + }, + [MT8183_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = 0x0308, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_id = {"isp"}, + .subsys_clk_prefix = "isp", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + BIT(3) | BIT(8), BIT(3) | BIT(8)), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + BIT(10), 0), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + BIT(2), BIT(2)), + }, + }, + [MT8183_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = BIT(31), + .ctl_offs = 0x0300, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_table = { + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + BIT(7), BIT(7)), + }, + }, + [MT8183_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = PWR_STATUS_VENC, + .ctl_offs = 0x0304, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bp_table = { + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + BIT(1), BIT(1)), + }, + }, + [MT8183_POWER_DOMAIN_VPU_TOP] = { + .name = "vpu_top", + .sta_mask = BIT(26), + .ctl_offs = 0x0324, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_id = {"vpu", "vpu1"}, + .subsys_clk_prefix = "vpu", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + GENMASK(9, 6) | BIT(12), + GENMASK(9, 6) | BIT(12)), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + BIT(27), BIT(27)), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + BIT(10) | BIT(11), BIT(10) | BIT(11)), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + BIT(5) | BIT(6), BIT(5) | BIT(6)), + }, + }, + [MT8183_POWER_DOMAIN_VPU_CORE0] = { + .name = "vpu_core0", + .sta_mask = BIT(27), + .ctl_offs = 0x33c, + .sram_iso_ctrl = true, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_id = {"vpu2"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + BIT(6), BIT(6)), + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + BIT(0) | BIT(2) | BIT(4), + BIT(0) | BIT(2) | BIT(4)), + }, + }, + [MT8183_POWER_DOMAIN_VPU_CORE1] = { + .name = "vpu_core1", + .sta_mask = BIT(28), + .ctl_offs = 0x0340, + .sram_iso_ctrl = true, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_id = {"vpu3"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + BIT(7), BIT(7)), + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + BIT(1) | BIT(3) | BIT(5), + BIT(1) | BIT(3) | BIT(5)), + }, + }, +}; + +static const struct scp_subdomain scp_subdomain_mt8183[] = { + {MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG}, + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D}, + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0}, + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_CAM}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_ISP}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VDEC}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VENC}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VPU_TOP}, + {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE0}, + {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE1}, +}; + static const struct scp_soc_data mt2701_data = { .domains = scp_domain_data_mt2701, .num_domains = ARRAY_SIZE(scp_domain_data_mt2701), @@ -1197,6 +1409,17 @@ static void mtk_register_power_domains(struct platform_device *pdev, .bus_prot_reg_update = true, }; +static const struct scp_soc_data mt8183_data = { + .domains = scp_domain_data_mt8183, + .num_domains = ARRAY_SIZE(scp_domain_data_mt8183), + .subdomains = scp_subdomain_mt8183, + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8183), + .regs = { + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184 + } +}; + /* * scpsys driver init */ @@ -1221,6 +1444,9 @@ static void mtk_register_power_domains(struct platform_device *pdev, .compatible = "mediatek,mt8173-scpsys", .data = &mt8173_data, }, { + .compatible = "mediatek,mt8183-scpsys", + .data = &mt8183_data, + }, { /* sentinel */ } }; -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel