From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <SRS0=jko7=2A=vger.kernel.org=linux-kernel-owner@kernel.org>
X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
	aws-us-west-2-korg-lkml-1.web.codeaurora.org
X-Spam-Level: 
X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID,
	DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,
	HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,
	SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no
	version=3.4.0
Received: from mail.kernel.org (mail.kernel.org [198.145.29.99])
	by smtp.lore.kernel.org (Postfix) with ESMTP id 6D4C3C2D0BF
	for <linux-kernel@archiver.kernel.org>; Tue, 10 Dec 2019 08:37:26 +0000 (UTC)
Received: from vger.kernel.org (vger.kernel.org [209.132.180.67])
	by mail.kernel.org (Postfix) with ESMTP id 14F64207FF
	for <linux-kernel@archiver.kernel.org>; Tue, 10 Dec 2019 08:37:26 +0000 (UTC)
Authentication-Results: mail.kernel.org;
	dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lI7EB+RN"
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1727291AbfLJIhY (ORCPT
        <rfc822;linux-kernel@archiver.kernel.org>);
        Tue, 10 Dec 2019 03:37:24 -0500
Received: from mail-pg1-f196.google.com ([209.85.215.196]:40236 "EHLO
        mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1726960AbfLJIhV (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Tue, 10 Dec 2019 03:37:21 -0500
Received: by mail-pg1-f196.google.com with SMTP id k25so8541641pgt.7
        for <linux-kernel@vger.kernel.org>; Tue, 10 Dec 2019 00:37:20 -0800 (PST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=gmail.com; s=20161025;
        h=from:to:cc:subject:date:message-id:in-reply-to:references
         :mime-version:content-transfer-encoding;
        bh=2YOvetV4MVRRWPou2An5hVJNwBVfKLVagoiSqtpV5io=;
        b=lI7EB+RNXO2IOAaBP8QoxppbUYFi64K6owYRv+tg2UUiwIHPW5/xeQov8v2Wgeyou1
         XOQmtySV1DmVOmya4O3i/VN0IbkVt1axGw02ocTBXjAbiiqo5UQ7e0o5tMfZ1UdS+f9W
         vtR3SlhJhAw8MeD9jA+zBDqia0JaeNILol5rjIruBWt1NL1BXHsDugi6AFCQflS5PLFy
         6wn5tXmPhmsMmQct9bPxJ9pQsXbxESplbAOoCSGY2Ac3RVpMnLJrrEcLAxCsghVdZkFC
         idkTcZj36eVEtZm57o57N0bQ4KOjbCSeynaZx8QDJmKUFYbsZPYfTt8kAGTQwXRMCnV0
         8vAg==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=1e100.net; s=20161025;
        h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
         :references:mime-version:content-transfer-encoding;
        bh=2YOvetV4MVRRWPou2An5hVJNwBVfKLVagoiSqtpV5io=;
        b=Ll6+a+RSykPAX63KqkFVBp3Wnrvj+/SJYR1l/onrmhjy6M78w/Q98JLjTYXlVVkpoC
         71wVxuMojXk8ueCYZD0vChgpc+Q4bjd9xwpjmWvcwpShuTRhE9CTJ/h10011OWInuQSM
         rIezc1jL59YVKOwvhbI9wN4h9HLGW2RItcs6pys/YnSdDZyT7kJyoTxbHNUdrs5wY7Mw
         FasmP410O8fhMkaYSd8l/eiJv+8b1YoFwdL5wn02sXAM/HuoSZIZKqG3TSe/99B8suVr
         0pJZcplPo1GtfUsQphSHlUGHSLtFe7t96tAH1VejruFDgbj9QFZdLWUMJPMXF38dcz4m
         a7rg==
X-Gm-Message-State: APjAAAXxph8m5G2uWFxAxmkewT0SQehutWPFVn1Djh0FfVUBD++zPKkT
        aw62jI8NKp698wCWxA97Kf8=
X-Google-Smtp-Source: APXvYqzW5DPlSfWwIpXSCL6evLBhPC6okvck3EI2x3qAk5xyMoX4lwHt8lzwnWi2YPzDWoEejOVA2g==
X-Received: by 2002:a63:1b54:: with SMTP id b20mr23239679pgm.312.1575967039849;
        Tue, 10 Dec 2019 00:37:19 -0800 (PST)
Received: from nj08008nbu.spreadtrum.com ([117.18.48.82])
        by smtp.gmail.com with ESMTPSA id y128sm2246632pfg.17.2019.12.10.00.37.15
        (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);
        Tue, 10 Dec 2019 00:37:19 -0800 (PST)
From:   Kevin Tang <kevin3.tang@gmail.com>
To:     airlied@linux.ie, daniel@ffwll.ch, kevin3.tang@gmail.com
Cc:     orsonzhai@gmail.com, baolin.wang@linaro.org, zhang.lyra@gmail.com,
        linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: [PATCH RFC 8/8] drm/sprd: add Unisoc's drm generic mipi panel driver
Date:   Tue, 10 Dec 2019 16:36:35 +0800
Message-Id: <1575966995-13757-9-git-send-email-kevin3.tang@gmail.com>
X-Mailer: git-send-email 2.7.4
In-Reply-To: <1575966995-13757-1-git-send-email-kevin3.tang@gmail.com>
References: <1575966995-13757-1-git-send-email-kevin3.tang@gmail.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

From: Kevin Tang <kevin.tang@unisoc.com>

This is a generic mipi dsi panel driver, All the parameters related
to lcd panel, we are placed in the DTS to configure,
for example，lcd display timing, dpi parameter and more.

Cc: Orson Zhai <orsonzhai@gmail.com>
Cc: Baolin Wang <baolin.wang@linaro.org>
Cc: Chunyan Zhang <zhang.lyra@gmail.com>
Signed-off-by: Kevin Tang <kevin.tang@unisoc.com>
---
 drivers/gpu/drm/sprd/Makefile     |   3 +-
 drivers/gpu/drm/sprd/sprd_panel.c | 778 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/sprd/sprd_panel.h | 114 ++++++
 3 files changed, 894 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/sprd/sprd_panel.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_panel.h

diff --git a/drivers/gpu/drm/sprd/Makefile b/drivers/gpu/drm/sprd/Makefile
index 78d3ddb..30a581c 100644
--- a/drivers/gpu/drm/sprd/Makefile
+++ b/drivers/gpu/drm/sprd/Makefile
@@ -8,7 +8,8 @@ obj-y := sprd_drm.o \
 	sprd_gem.o \
 	sprd_dpu.o \
 	sprd_dsi.o \
-	sprd_dphy.o
+	sprd_dphy.o \
+	sprd_panel.o
 
 obj-y += disp_lib.o
 obj-y += dpu/
diff --git a/drivers/gpu/drm/sprd/sprd_panel.c b/drivers/gpu/drm/sprd/sprd_panel.c
new file mode 100644
index 0000000..4a70a20
--- /dev/null
+++ b/drivers/gpu/drm/sprd/sprd_panel.c
@@ -0,0 +1,778 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Unisoc Inc.
+ */
+
+#include <drm/drm_atomic_helper.h>
+#include <linux/backlight.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/pm_runtime.h>
+#include <video/mipi_display.h>
+#include <video/of_display_timing.h>
+#include <video/videomode.h>
+
+#include "sprd_dpu.h"
+#include "sprd_panel.h"
+#include "dsi/sprd_dsi_api.h"
+
+#define SPRD_MIPI_DSI_FMT_DSC 0xff
+static DEFINE_MUTEX(panel_lock);
+
+static const char *lcd_name;
+
+static inline struct sprd_panel *to_sprd_panel(struct drm_panel *panel)
+{
+	return container_of(panel, struct sprd_panel, base);
+}
+
+static int sprd_panel_send_cmds(struct mipi_dsi_device *dsi,
+				const void *data, int size)
+{
+	struct sprd_panel *panel;
+	const struct dsi_cmd_desc *cmds = data;
+	u16 len;
+
+	if (cmds == NULL || dsi == NULL)
+		return -EINVAL;
+
+	panel = mipi_dsi_get_drvdata(dsi);
+
+	while (size > 0) {
+		len = (cmds->wc_h << 8) | cmds->wc_l;
+
+		if (panel->info.use_dcs)
+			mipi_dsi_dcs_write_buffer(dsi, cmds->payload, len);
+		else
+			mipi_dsi_generic_write(dsi, cmds->payload, len);
+
+		if (cmds->wait)
+			msleep(cmds->wait);
+		cmds = (const struct dsi_cmd_desc *)(cmds->payload + len);
+		size -= (len + 4);
+	}
+
+	return 0;
+}
+
+static int sprd_panel_unprepare(struct drm_panel *p)
+{
+	struct sprd_panel *panel = to_sprd_panel(p);
+	struct gpio_timing *timing;
+	int items, i;
+
+	DRM_INFO("%s()\n", __func__);
+
+	if (panel->info.avee_gpio) {
+		gpiod_direction_output(panel->info.avee_gpio, 0);
+		mdelay(5);
+	}
+
+	if (panel->info.avdd_gpio) {
+		gpiod_direction_output(panel->info.avdd_gpio, 0);
+		mdelay(5);
+	}
+
+	if (panel->info.reset_gpio) {
+		items = panel->info.rst_off_seq.items;
+		timing = panel->info.rst_off_seq.timing;
+		for (i = 0; i < items; i++) {
+			gpiod_direction_output(panel->info.reset_gpio,
+						timing[i].level);
+			mdelay(timing[i].delay);
+		}
+	}
+
+	regulator_disable(panel->supply);
+
+	return 0;
+}
+
+static int sprd_panel_prepare(struct drm_panel *p)
+{
+	struct sprd_panel *panel = to_sprd_panel(p);
+	struct gpio_timing *timing;
+	int items, i, ret;
+
+	DRM_INFO("%s()\n", __func__);
+
+	ret = regulator_enable(panel->supply);
+	if (ret < 0) {
+		DRM_ERROR("enable lcd regulator failed\n");
+		return ret;
+	}
+
+	if (panel->info.avdd_gpio) {
+		gpiod_direction_output(panel->info.avdd_gpio, 1);
+		mdelay(5);
+	}
+
+	if (panel->info.avee_gpio) {
+		gpiod_direction_output(panel->info.avee_gpio, 1);
+		mdelay(5);
+	}
+
+	if (panel->info.reset_gpio) {
+		items = panel->info.rst_on_seq.items;
+		timing = panel->info.rst_on_seq.timing;
+		for (i = 0; i < items; i++) {
+			gpiod_direction_output(panel->info.reset_gpio,
+						timing[i].level);
+			mdelay(timing[i].delay);
+		}
+	}
+
+	return 0;
+}
+
+static int sprd_panel_disable(struct drm_panel *p)
+{
+	struct sprd_panel *panel = to_sprd_panel(p);
+
+	DRM_INFO("%s()\n", __func__);
+
+	mutex_lock(&panel_lock);
+	/*
+	 * FIXME:
+	 * The cancel work should be executed before DPU stop,
+	 * otherwise the esd check will be failed if the DPU
+	 * stopped in video mode and the DSI has not change to
+	 * CMD mode yet. Since there is no VBLANK timing for
+	 * LP cmd transmission.
+	 */
+	if (panel->esd_work_pending) {
+		cancel_delayed_work_sync(&panel->esd_work);
+		panel->esd_work_pending = false;
+	}
+
+	if (panel->backlight) {
+		panel->backlight->props.power = FB_BLANK_POWERDOWN;
+		panel->backlight->props.state |= BL_CORE_FBBLANK;
+		backlight_update_status(panel->backlight);
+	}
+
+	sprd_panel_send_cmds(panel->slave,
+			     panel->info.cmds[CMD_CODE_SLEEP_IN],
+			     panel->info.cmds_len[CMD_CODE_SLEEP_IN]);
+
+	panel->is_enabled = false;
+	mutex_unlock(&panel_lock);
+
+	return 0;
+}
+
+static int sprd_panel_enable(struct drm_panel *p)
+{
+	struct sprd_panel *panel = to_sprd_panel(p);
+
+	DRM_INFO("%s()\n", __func__);
+
+	mutex_lock(&panel_lock);
+	sprd_panel_send_cmds(panel->slave,
+			     panel->info.cmds[CMD_CODE_INIT],
+			     panel->info.cmds_len[CMD_CODE_INIT]);
+
+	if (panel->backlight) {
+		panel->backlight->props.power = FB_BLANK_UNBLANK;
+		panel->backlight->props.state &= ~BL_CORE_FBBLANK;
+		backlight_update_status(panel->backlight);
+	}
+
+	if (panel->info.esd_check_en) {
+		schedule_delayed_work(&panel->esd_work,
+				      msecs_to_jiffies(1000));
+		panel->esd_work_pending = true;
+	}
+
+	panel->is_enabled = true;
+	mutex_unlock(&panel_lock);
+
+	return 0;
+}
+
+static int sprd_panel_get_modes(struct drm_panel *p)
+{
+	struct drm_display_mode *mode;
+	struct sprd_panel *panel = to_sprd_panel(p);
+	struct device_node *np = panel->slave->dev.of_node;
+	u32 surface_width = 0, surface_height = 0;
+	int i, mode_count = 0;
+
+	DRM_INFO("%s()\n", __func__);
+	mode = drm_mode_duplicate(p->drm, &panel->info.mode);
+	if (!mode) {
+		DRM_ERROR("failed to alloc mode %s\n", panel->info.mode.name);
+		return 0;
+	}
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_probed_add(p->connector, mode);
+	mode_count++;
+
+	for (i = 1; i < panel->info.num_buildin_modes; i++)	{
+		mode = drm_mode_duplicate(p->drm,
+			&(panel->info.buildin_modes[i]));
+		if (!mode) {
+			DRM_ERROR("failed to alloc mode %s\n",
+				panel->info.buildin_modes[i].name);
+			return 0;
+		}
+		mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_DEFAULT;
+		drm_mode_probed_add(p->connector, mode);
+		mode_count++;
+	}
+
+	of_property_read_u32(np, "sprd,surface-width", &surface_width);
+	of_property_read_u32(np, "sprd,surface-height", &surface_height);
+	if (surface_width && surface_height) {
+		struct videomode vm = {};
+
+		vm.hactive = surface_width;
+		vm.vactive = surface_height;
+		vm.pixelclock = surface_width * surface_height * 60;
+
+		mode = drm_mode_create(p->drm);
+
+		mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_BUILTIN |
+			DRM_MODE_TYPE_CRTC_C;
+		mode->vrefresh = 60;
+		drm_display_mode_from_videomode(&vm, mode);
+		drm_mode_probed_add(p->connector, mode);
+		mode_count++;
+	}
+
+	p->connector->display_info.width_mm = panel->info.mode.width_mm;
+	p->connector->display_info.height_mm = panel->info.mode.height_mm;
+
+	return mode_count;
+}
+
+static const struct drm_panel_funcs sprd_panel_funcs = {
+	.get_modes = sprd_panel_get_modes,
+	.enable = sprd_panel_enable,
+	.disable = sprd_panel_disable,
+	.prepare = sprd_panel_prepare,
+	.unprepare = sprd_panel_unprepare,
+};
+
+static int sprd_panel_esd_check(struct sprd_panel *panel)
+{
+	struct panel_info *info = &panel->info;
+	u8 read_val = 0;
+
+	/* FIXME: we should enable HS cmd tx here */
+	mipi_dsi_set_maximum_return_packet_size(panel->slave, 1);
+	mipi_dsi_dcs_read(panel->slave, info->esd_check_reg,
+			  &read_val, 1);
+
+	/*
+	 * TODO:
+	 * Should we support multi-registers check in the future?
+	 */
+	if (read_val != info->esd_check_val) {
+		DRM_ERROR("esd check failed, read value = 0x%02x\n",
+			  read_val);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sprd_panel_te_check(struct sprd_panel *panel)
+{
+	static int te_wq_inited;
+	struct sprd_dpu *dpu;
+	int ret;
+	bool irq_occur;
+
+	if (!panel->base.connector ||
+	    !panel->base.connector->encoder ||
+	    !panel->base.connector->encoder->crtc) {
+		return 0;
+	}
+
+	dpu = container_of(panel->base.connector->encoder->crtc,
+		struct sprd_dpu, crtc);
+
+	if (!te_wq_inited) {
+		init_waitqueue_head(&dpu->ctx.te_wq);
+		te_wq_inited = 1;
+		dpu->ctx.evt_te = false;
+		DRM_INFO("%s init te waitqueue\n", __func__);
+	}
+
+	/* DPU TE irq maybe enabled in kernel */
+	if (!dpu->ctx.is_inited)
+		return 0;
+
+	dpu->ctx.te_check_en = true;
+
+	/* wait for TE interrupt */
+	ret = wait_event_interruptible_timeout(dpu->ctx.te_wq,
+		dpu->ctx.evt_te, msecs_to_jiffies(500));
+	if (!ret) {
+		/* double check TE interrupt through dpu_int_raw register */
+		if (dpu->core && dpu->core->check_raw_int) {
+			irq_occur = dpu->core->check_raw_int(&dpu->ctx,
+				DISPC_INT_TE_MASK);
+			if (!irq_occur) {
+				DRM_ERROR("TE esd timeout.\n");
+				ret = -ETIMEDOUT;
+			} else
+				DRM_WARN("TE occur, but isr schedule delay\n");
+		} else {
+			DRM_ERROR("TE esd timeout.\n");
+			ret = -ETIMEDOUT;
+		}
+	}
+
+	dpu->ctx.te_check_en = false;
+	dpu->ctx.evt_te = false;
+
+	return ret < 0 ? ret : 0;
+}
+
+static void sprd_panel_esd_work_func(struct work_struct *work)
+{
+	struct sprd_panel *panel = container_of(work, struct sprd_panel,
+						esd_work.work);
+	struct panel_info *info = &panel->info;
+	int ret;
+
+	if (info->esd_check_mode == ESD_MODE_REG_CHECK)
+		ret = sprd_panel_esd_check(panel);
+	else if (info->esd_check_mode == ESD_MODE_TE_CHECK)
+		ret = sprd_panel_te_check(panel);
+	else {
+		DRM_ERROR("unknown esd check mode:%d\n", info->esd_check_mode);
+		return;
+	}
+
+	if (ret && panel->base.connector && panel->base.connector->encoder) {
+		const struct drm_encoder_helper_funcs *funcs;
+		struct drm_encoder *encoder;
+
+		encoder = panel->base.connector->encoder;
+		funcs = encoder->helper_private;
+		panel->esd_work_pending = false;
+
+		if (encoder->crtc && encoder->crtc->state &&
+		    !encoder->crtc->state->active) {
+			DRM_INFO("skip esd recovery during panel suspend\n");
+			return;
+		}
+
+		DRM_INFO("====== esd recovery start ========\n");
+		funcs->disable(encoder);
+
+		if (!encoder->crtc->state->active) {
+			DRM_INFO("skip esd recovery if panel suspend\n");
+			return;
+		}
+		funcs->enable(encoder);
+		DRM_INFO("======= esd recovery end =========\n");
+	} else
+		schedule_delayed_work(&panel->esd_work,
+			msecs_to_jiffies(info->esd_check_period));
+}
+
+static int sprd_panel_gpio_request(struct device *dev,
+			struct sprd_panel *panel)
+{
+	panel->info.avdd_gpio = devm_gpiod_get_optional(dev,
+					"avdd", GPIOD_ASIS);
+	if (IS_ERR_OR_NULL(panel->info.avdd_gpio))
+		DRM_WARN("can't get panel avdd gpio: %ld\n",
+				 PTR_ERR(panel->info.avdd_gpio));
+
+	panel->info.avee_gpio = devm_gpiod_get_optional(dev,
+					"avee", GPIOD_ASIS);
+	if (IS_ERR_OR_NULL(panel->info.avee_gpio))
+		DRM_WARN("can't get panel avee gpio: %ld\n",
+				 PTR_ERR(panel->info.avee_gpio));
+
+	panel->info.reset_gpio = devm_gpiod_get_optional(dev,
+					"reset", GPIOD_ASIS);
+	if (IS_ERR_OR_NULL(panel->info.reset_gpio))
+		DRM_WARN("can't get panel reset gpio: %ld\n",
+				 PTR_ERR(panel->info.reset_gpio));
+
+	return 0;
+}
+
+static int of_parse_reset_seq(struct device_node *np,
+				struct panel_info *info)
+{
+	struct property *prop;
+	int bytes, rc;
+	u32 *p;
+
+	prop = of_find_property(np, "sprd,reset-on-sequence", &bytes);
+	if (!prop) {
+		DRM_ERROR("sprd,reset-on-sequence property not found\n");
+		return -EINVAL;
+	}
+
+	p = kzalloc(bytes, GFP_KERNEL);
+	if (!p)
+		return -ENOMEM;
+	rc = of_property_read_u32_array(np, "sprd,reset-on-sequence",
+					p, bytes / 4);
+	if (rc) {
+		DRM_ERROR("parse sprd,reset-on-sequence failed\n");
+		kfree(p);
+		return rc;
+	}
+
+	info->rst_on_seq.items = bytes / 8;
+	info->rst_on_seq.timing = (struct gpio_timing *)p;
+
+	prop = of_find_property(np, "sprd,reset-off-sequence", &bytes);
+	if (!prop) {
+		DRM_ERROR("sprd,reset-off-sequence property not found\n");
+		return -EINVAL;
+	}
+
+	p = kzalloc(bytes, GFP_KERNEL);
+	if (!p)
+		return -ENOMEM;
+	rc = of_property_read_u32_array(np, "sprd,reset-off-sequence",
+					p, bytes / 4);
+	if (rc) {
+		DRM_ERROR("parse sprd,reset-off-sequence failed\n");
+		kfree(p);
+		return rc;
+	}
+
+	info->rst_off_seq.items = bytes / 8;
+	info->rst_off_seq.timing = (struct gpio_timing *)p;
+
+	return 0;
+}
+
+static int of_parse_buildin_modes(struct panel_info *info,
+	struct device_node *lcd_node)
+{
+	int i, rc, num_timings;
+	struct device_node *timings_np;
+
+
+	timings_np = of_get_child_by_name(lcd_node, "display-timings");
+	if (!timings_np) {
+		DRM_ERROR("%s: can not find display-timings node\n",
+			lcd_node->name);
+		return -ENODEV;
+	}
+
+	num_timings = of_get_child_count(timings_np);
+	if (num_timings == 0) {
+		/* should never happen, as entry was already found above */
+		DRM_ERROR("%s: no timings specified\n", lcd_node->name);
+		goto done;
+	}
+
+	info->buildin_modes = kzalloc(sizeof(struct drm_display_mode) *
+				num_timings, GFP_KERNEL);
+
+	for (i = 0; i < num_timings; i++) {
+		rc = of_get_drm_display_mode(lcd_node,
+			&info->buildin_modes[i], NULL, i);
+		if (rc) {
+			DRM_ERROR("get display timing failed\n");
+			goto entryfail;
+		}
+
+		info->buildin_modes[i].width_mm = info->mode.width_mm;
+		info->buildin_modes[i].height_mm = info->mode.height_mm;
+		info->buildin_modes[i].vrefresh = info->mode.vrefresh;
+	}
+	info->num_buildin_modes = num_timings;
+	DRM_INFO("info->num_buildin_modes = %d\n", num_timings);
+	goto done;
+
+entryfail:
+	kfree(info->buildin_modes);
+done:
+	of_node_put(timings_np);
+
+	return 0;
+}
+
+static int sprd_panel_parse_dt(struct device_node *np, struct sprd_panel *panel)
+{
+	u32 val;
+	struct device_node *lcd_node;
+	struct panel_info *info = &panel->info;
+	int bytes, rc;
+	const void *p;
+	const char *str;
+	char lcd_path[60];
+
+	sprintf(lcd_path, "/lcds/%s", lcd_name);
+	lcd_node = of_find_node_by_path(lcd_path);
+	if (!lcd_node) {
+		DRM_ERROR("%pOF: could not find %s node\n", np, lcd_name);
+		return -ENODEV;
+	}
+	info->of_node = lcd_node;
+
+	rc = of_property_read_u32(lcd_node, "sprd,dsi-work-mode", &val);
+	if (!rc) {
+		if (val == SPRD_DSI_MODE_CMD)
+			info->mode_flags = 0;
+		else if (val == SPRD_DSI_MODE_VIDEO_BURST)
+			info->mode_flags = MIPI_DSI_MODE_VIDEO |
+					   MIPI_DSI_MODE_VIDEO_BURST;
+		else if (val == SPRD_DSI_MODE_VIDEO_SYNC_PULSE)
+			info->mode_flags = MIPI_DSI_MODE_VIDEO |
+					   MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+		else if (val == SPRD_DSI_MODE_VIDEO_SYNC_EVENT)
+			info->mode_flags = MIPI_DSI_MODE_VIDEO;
+	} else {
+		DRM_ERROR("dsi work mode is not found! use video mode\n");
+		info->mode_flags = MIPI_DSI_MODE_VIDEO |
+				   MIPI_DSI_MODE_VIDEO_BURST;
+	}
+
+	if (of_property_read_bool(lcd_node, "sprd,dsi-non-continuous-clock"))
+		info->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
+
+	rc = of_property_read_u32(lcd_node, "sprd,dsi-lane-number", &val);
+	if (!rc)
+		info->lanes = val;
+	else
+		info->lanes = 4;
+
+	rc = of_property_read_string(lcd_node, "sprd,dsi-color-format", &str);
+	if (rc)
+		info->format = MIPI_DSI_FMT_RGB888;
+	else if (!strcmp(str, "rgb888"))
+		info->format = MIPI_DSI_FMT_RGB888;
+	else if (!strcmp(str, "rgb666"))
+		info->format = MIPI_DSI_FMT_RGB666;
+	else if (!strcmp(str, "rgb666_packed"))
+		info->format = MIPI_DSI_FMT_RGB666_PACKED;
+	else if (!strcmp(str, "rgb565"))
+		info->format = MIPI_DSI_FMT_RGB565;
+	else if (!strcmp(str, "dsc"))
+		info->format = SPRD_MIPI_DSI_FMT_DSC;
+	else
+		DRM_ERROR("dsi-color-format (%s) is not supported\n", str);
+
+	rc = of_property_read_u32(lcd_node, "width-mm", &val);
+	if (!rc)
+		info->mode.width_mm = val;
+	else
+		info->mode.width_mm = 68;
+
+	rc = of_property_read_u32(lcd_node, "height-mm", &val);
+	if (!rc)
+		info->mode.height_mm = val;
+	else
+		info->mode.height_mm = 121;
+
+	rc = of_property_read_u32(lcd_node, "sprd,esd-check-enable", &val);
+	if (!rc)
+		info->esd_check_en = val;
+
+	rc = of_property_read_u32(lcd_node, "sprd,esd-check-mode", &val);
+	if (!rc)
+		info->esd_check_mode = val;
+	else
+		info->esd_check_mode = 1;
+
+	rc = of_property_read_u32(lcd_node, "sprd,esd-check-period", &val);
+	if (!rc)
+		info->esd_check_period = val;
+	else
+		info->esd_check_period = 1000;
+
+	rc = of_property_read_u32(lcd_node, "sprd,esd-check-register", &val);
+	if (!rc)
+		info->esd_check_reg = val;
+	else
+		info->esd_check_reg = 0x0A;
+
+	rc = of_property_read_u32(lcd_node, "sprd,esd-check-value", &val);
+	if (!rc)
+		info->esd_check_val = val;
+	else
+		info->esd_check_val = 0x9C;
+
+	if (of_property_read_bool(lcd_node, "sprd,use-dcs-write"))
+		info->use_dcs = true;
+	else
+		info->use_dcs = false;
+
+	rc = of_parse_reset_seq(lcd_node, info);
+	if (rc)
+		DRM_ERROR("parse lcd reset sequence failed\n");
+
+	p = of_get_property(lcd_node, "sprd,initial-command", &bytes);
+	if (p) {
+		info->cmds[CMD_CODE_INIT] = p;
+		info->cmds_len[CMD_CODE_INIT] = bytes;
+	} else
+		DRM_ERROR("can't find sprd,initial-command property\n");
+
+	p = of_get_property(lcd_node, "sprd,sleep-in-command", &bytes);
+	if (p) {
+		info->cmds[CMD_CODE_SLEEP_IN] = p;
+		info->cmds_len[CMD_CODE_SLEEP_IN] = bytes;
+	} else
+		DRM_ERROR("can't find sprd,sleep-in-command property\n");
+
+	p = of_get_property(lcd_node, "sprd,sleep-out-command", &bytes);
+	if (p) {
+		info->cmds[CMD_CODE_SLEEP_OUT] = p;
+		info->cmds_len[CMD_CODE_SLEEP_OUT] = bytes;
+	} else
+		DRM_ERROR("can't find sprd,sleep-out-command property\n");
+
+	rc = of_get_drm_display_mode(lcd_node, &info->mode, 0,
+				     OF_USE_NATIVE_MODE);
+	if (rc) {
+		DRM_ERROR("get display timing failed\n");
+		return rc;
+	}
+
+	info->mode.vrefresh = drm_mode_vrefresh(&info->mode);
+	of_parse_buildin_modes(info, lcd_node);
+
+	return 0;
+}
+
+static int sprd_panel_probe(struct mipi_dsi_device *slave)
+{
+	int ret;
+	struct sprd_panel *panel;
+	struct device_node *bl_node;
+
+	panel = devm_kzalloc(&slave->dev, sizeof(*panel), GFP_KERNEL);
+	if (!panel)
+		return -ENOMEM;
+
+	bl_node = of_parse_phandle(slave->dev.of_node,
+					"sprd,backlight", 0);
+	if (bl_node) {
+		panel->backlight = of_find_backlight_by_node(bl_node);
+		of_node_put(bl_node);
+
+		if (panel->backlight) {
+			panel->backlight->props.state &= ~BL_CORE_FBBLANK;
+			panel->backlight->props.power = FB_BLANK_UNBLANK;
+			backlight_update_status(panel->backlight);
+		} else {
+			DRM_WARN("backlight is not ready, panel probe deferred\n");
+			return -EPROBE_DEFER;
+		}
+	} else
+		DRM_WARN("backlight node not found\n");
+
+	panel->supply = devm_regulator_get(&slave->dev, "power");
+	if (IS_ERR(panel->supply)) {
+		if (PTR_ERR(panel->supply) == -EPROBE_DEFER)
+			DRM_ERROR("regulator driver not initialized, probe deffer\n");
+		else
+			DRM_ERROR("can't get regulator: %ld\n", PTR_ERR(panel->supply));
+
+		return PTR_ERR(panel->supply);
+	}
+
+	INIT_DELAYED_WORK(&panel->esd_work, sprd_panel_esd_work_func);
+
+	ret = sprd_panel_parse_dt(slave->dev.of_node, panel);
+	if (ret) {
+		DRM_ERROR("parse panel info failed\n");
+		return ret;
+	}
+
+	ret = sprd_panel_gpio_request(&slave->dev, panel);
+	if (ret) {
+		DRM_WARN("gpio is not ready, panel probe deferred\n");
+		return -EPROBE_DEFER;
+	}
+
+	drm_panel_init(&panel->base, &panel->dev,
+		&sprd_panel_funcs, DRM_MODE_CONNECTOR_DSI);
+
+	ret = drm_panel_add(&panel->base);
+	if (ret) {
+		DRM_ERROR("drm_panel_add() failed\n");
+		return ret;
+	}
+
+	slave->lanes = panel->info.lanes;
+	slave->format = panel->info.format;
+	slave->mode_flags = panel->info.mode_flags;
+
+	ret = mipi_dsi_attach(slave);
+	if (ret) {
+		DRM_ERROR("failed to attach dsi panel to host\n");
+		drm_panel_remove(&panel->base);
+		return ret;
+	}
+	panel->slave = slave;
+
+	mipi_dsi_set_drvdata(slave, panel);
+
+	/*
+	 * FIXME:
+	 * The esd check work should not be scheduled in probe
+	 * function. It should be scheduled in the enable()
+	 * callback function. But the dsi encoder will not call
+	 * drm_panel_enable() the first time in encoder_enable().
+	 */
+	if (panel->info.esd_check_en) {
+		schedule_delayed_work(&panel->esd_work,
+				      msecs_to_jiffies(2000));
+		panel->esd_work_pending = true;
+	}
+
+	panel->is_enabled = true;
+
+	DRM_INFO("panel driver probe success\n");
+
+	return 0;
+}
+
+static int sprd_panel_remove(struct mipi_dsi_device *slave)
+{
+	struct sprd_panel *panel = mipi_dsi_get_drvdata(slave);
+	int ret;
+
+	DRM_INFO("%s()\n", __func__);
+
+	sprd_panel_disable(&panel->base);
+	sprd_panel_unprepare(&panel->base);
+
+	ret = mipi_dsi_detach(slave);
+	if (ret < 0)
+		DRM_ERROR("failed to detach from DSI host: %d\n", ret);
+
+	drm_panel_detach(&panel->base);
+	drm_panel_remove(&panel->base);
+
+	return 0;
+}
+
+static const struct of_device_id panel_of_match[] = {
+	{ .compatible = "sprd,generic-mipi-panel", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, panel_of_match);
+
+static struct mipi_dsi_driver sprd_panel_driver = {
+	.driver = {
+		.name = "sprd-mipi-panel-drv",
+		.of_match_table = panel_of_match,
+	},
+	.probe = sprd_panel_probe,
+	.remove = sprd_panel_remove,
+};
+module_mipi_dsi_driver(sprd_panel_driver);
+
+MODULE_AUTHOR("Leon He <leon.he@unisoc.com>");
+MODULE_AUTHOR("Kevin Tang <kevin.tang@unisoc.com>");
+MODULE_DESCRIPTION("Unisoc MIPI DSI Panel Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/sprd/sprd_panel.h b/drivers/gpu/drm/sprd/sprd_panel.h
new file mode 100644
index 0000000..216cd4b
--- /dev/null
+++ b/drivers/gpu/drm/sprd/sprd_panel.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Unisoc Inc.
+ */
+
+#ifndef _SPRD_PANEL_H_
+#define _SPRD_PANEL_H_
+
+#include <linux/backlight.h>
+#include <linux/of.h>
+#include <linux/regulator/consumer.h>
+#include <linux/workqueue.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_print.h>
+
+enum {
+	CMD_CODE_INIT = 0,
+	CMD_CODE_SLEEP_IN,
+	CMD_CODE_SLEEP_OUT,
+	CMD_OLED_BRIGHTNESS,
+	CMD_OLED_REG_LOCK,
+	CMD_OLED_REG_UNLOCK,
+	CMD_CODE_RESERVED0,
+	CMD_CODE_RESERVED1,
+	CMD_CODE_RESERVED2,
+	CMD_CODE_RESERVED3,
+	CMD_CODE_RESERVED4,
+	CMD_CODE_RESERVED5,
+	CMD_CODE_MAX,
+};
+
+enum {
+	SPRD_DSI_MODE_CMD = 0,
+	SPRD_DSI_MODE_VIDEO_BURST,
+	SPRD_DSI_MODE_VIDEO_SYNC_PULSE,
+	SPRD_DSI_MODE_VIDEO_SYNC_EVENT,
+};
+
+enum {
+	ESD_MODE_REG_CHECK,
+	ESD_MODE_TE_CHECK,
+};
+
+struct dsi_cmd_desc {
+	u8 data_type;
+	u8 wait;
+	u8 wc_h;
+	u8 wc_l;
+	u8 payload[];
+};
+
+struct gpio_timing {
+	u32 level;
+	u32 delay;
+};
+
+struct reset_sequence {
+	u32 items;
+	struct gpio_timing *timing;
+};
+
+struct panel_info {
+	/* common parameters */
+	struct device_node *of_node;
+	struct drm_display_mode mode;
+	struct drm_display_mode *buildin_modes;
+	int num_buildin_modes;
+	struct gpio_desc *avdd_gpio;
+	struct gpio_desc *avee_gpio;
+	struct gpio_desc *reset_gpio;
+	struct reset_sequence rst_on_seq;
+	struct reset_sequence rst_off_seq;
+	const void *cmds[CMD_CODE_MAX];
+	int cmds_len[CMD_CODE_MAX];
+
+	/* esd check parameters*/
+	bool esd_check_en;
+	u8 esd_check_mode;
+	u16 esd_check_period;
+	u32 esd_check_reg;
+	u32 esd_check_val;
+
+	/* MIPI DSI specific parameters */
+	u32 format;
+	u32 lanes;
+	u32 mode_flags;
+	bool use_dcs;
+};
+
+struct sprd_panel {
+	struct device dev;
+	struct drm_panel base;
+	struct mipi_dsi_device *slave;
+	struct panel_info info;
+	struct backlight_device *backlight;
+	struct regulator *supply;
+	struct delayed_work esd_work;
+	bool esd_work_pending;
+	bool is_enabled;
+};
+
+struct sprd_oled {
+	struct backlight_device *bdev;
+	struct sprd_panel *panel;
+	struct dsi_cmd_desc *cmds[255];
+	int cmd_len;
+	int cmds_total;
+	int max_level;
+};
+
+#endif
-- 
2.7.4


From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <SRS0=Fh9a=2A=lists.freedesktop.org=dri-devel-bounces@kernel.org>
X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
	aws-us-west-2-korg-lkml-1.web.codeaurora.org
X-Spam-Level: 
X-Spam-Status: No, score=-9.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED,
	DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,
	HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,
	SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no
	version=3.4.0
Received: from mail.kernel.org (mail.kernel.org [198.145.29.99])
	by smtp.lore.kernel.org (Postfix) with ESMTP id A507BC43603
	for <dri-devel@archiver.kernel.org>; Tue, 10 Dec 2019 08:41:20 +0000 (UTC)
Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177])
	(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
	(No client certificate requested)
	by mail.kernel.org (Postfix) with ESMTPS id 7C282206D5
	for <dri-devel@archiver.kernel.org>; Tue, 10 Dec 2019 08:41:20 +0000 (UTC)
Authentication-Results: mail.kernel.org;
	dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lI7EB+RN"
DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7C282206D5
Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com
Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org
Received: from gabe.freedesktop.org (localhost [127.0.0.1])
	by gabe.freedesktop.org (Postfix) with ESMTP id 27C0A6E852;
	Tue, 10 Dec 2019 08:40:46 +0000 (UTC)
Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com
 [IPv6:2607:f8b0:4864:20::544])
 by gabe.freedesktop.org (Postfix) with ESMTPS id 59B9F6E82F
 for <dri-devel@lists.freedesktop.org>; Tue, 10 Dec 2019 08:37:20 +0000 (UTC)
Received: by mail-pg1-x544.google.com with SMTP id b1so8532378pgq.10
 for <dri-devel@lists.freedesktop.org>; Tue, 10 Dec 2019 00:37:20 -0800 (PST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;
 h=from:to:cc:subject:date:message-id:in-reply-to:references
 :mime-version:content-transfer-encoding;
 bh=2YOvetV4MVRRWPou2An5hVJNwBVfKLVagoiSqtpV5io=;
 b=lI7EB+RNXO2IOAaBP8QoxppbUYFi64K6owYRv+tg2UUiwIHPW5/xeQov8v2Wgeyou1
 XOQmtySV1DmVOmya4O3i/VN0IbkVt1axGw02ocTBXjAbiiqo5UQ7e0o5tMfZ1UdS+f9W
 vtR3SlhJhAw8MeD9jA+zBDqia0JaeNILol5rjIruBWt1NL1BXHsDugi6AFCQflS5PLFy
 6wn5tXmPhmsMmQct9bPxJ9pQsXbxESplbAOoCSGY2Ac3RVpMnLJrrEcLAxCsghVdZkFC
 idkTcZj36eVEtZm57o57N0bQ4KOjbCSeynaZx8QDJmKUFYbsZPYfTt8kAGTQwXRMCnV0
 8vAg==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
 d=1e100.net; s=20161025;
 h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
 :references:mime-version:content-transfer-encoding;
 bh=2YOvetV4MVRRWPou2An5hVJNwBVfKLVagoiSqtpV5io=;
 b=sYNKty5FASM3kaLX7DhmiNyPjO0Oh0czCXkTVMYgmH2rfZ1zXdEnx/ccEjn8Bzgz95
 hVoXIx2xIxrwsv9aYE+GpIHFywP1TvXAAyFosTgpYuKDcBHEfGZwBabCOXZjMoTJ2Ac/
 YmEbKY9Lsou6k4VIdJn9trleRQDVm/azc0iZLQ3MoqAxlzHteP9vYp5Y4h3sPcA5rPDW
 lMmfMc80mMCjeAk8Qlm3lP/DcCJUUz97nXnfQDHL0qPYyuq09XpGounYLNYhXyztWEJ0
 nxxu0LZFwApB8ZI4H6dnWEBZkda+QBOQY2L1jWsYhZNKWLGZx9FFjRYk79G965zPrOi4
 uy6Q==
X-Gm-Message-State: APjAAAUWjiFl16jNXLNUkZz3SytNnB/L0I+8UK0w5IUeufPrXR9E7HMw
 wyDc3YzOjy6VLWrF0X8+SMIsD6vy
X-Google-Smtp-Source: APXvYqzW5DPlSfWwIpXSCL6evLBhPC6okvck3EI2x3qAk5xyMoX4lwHt8lzwnWi2YPzDWoEejOVA2g==
X-Received: by 2002:a63:1b54:: with SMTP id b20mr23239679pgm.312.1575967039849; 
 Tue, 10 Dec 2019 00:37:19 -0800 (PST)
Received: from nj08008nbu.spreadtrum.com ([117.18.48.82])
 by smtp.gmail.com with ESMTPSA id y128sm2246632pfg.17.2019.12.10.00.37.15
 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);
 Tue, 10 Dec 2019 00:37:19 -0800 (PST)
From: Kevin Tang <kevin3.tang@gmail.com>
To: airlied@linux.ie,
	daniel@ffwll.ch,
	kevin3.tang@gmail.com
Subject: [PATCH RFC 8/8] drm/sprd: add Unisoc's drm generic mipi panel driver
Date: Tue, 10 Dec 2019 16:36:35 +0800
Message-Id: <1575966995-13757-9-git-send-email-kevin3.tang@gmail.com>
X-Mailer: git-send-email 2.7.4
In-Reply-To: <1575966995-13757-1-git-send-email-kevin3.tang@gmail.com>
References: <1575966995-13757-1-git-send-email-kevin3.tang@gmail.com>
MIME-Version: 1.0
X-Mailman-Approved-At: Tue, 10 Dec 2019 08:40:04 +0000
X-BeenThere: dri-devel@lists.freedesktop.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: Direct Rendering Infrastructure - Development
 <dri-devel.lists.freedesktop.org>
List-Unsubscribe: <https://lists.freedesktop.org/mailman/options/dri-devel>,
 <mailto:dri-devel-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <https://lists.freedesktop.org/archives/dri-devel>
List-Post: <mailto:dri-devel@lists.freedesktop.org>
List-Help: <mailto:dri-devel-request@lists.freedesktop.org?subject=help>
List-Subscribe: <https://lists.freedesktop.org/mailman/listinfo/dri-devel>,
 <mailto:dri-devel-request@lists.freedesktop.org?subject=subscribe>
Cc: orsonzhai@gmail.com, dri-devel@lists.freedesktop.org,
 linux-kernel@vger.kernel.org, zhang.lyra@gmail.com, baolin.wang@linaro.org
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
Errors-To: dri-devel-bounces@lists.freedesktop.org
Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org>

RnJvbTogS2V2aW4gVGFuZyA8a2V2aW4udGFuZ0B1bmlzb2MuY29tPgoKVGhpcyBpcyBhIGdlbmVy
aWMgbWlwaSBkc2kgcGFuZWwgZHJpdmVyLCBBbGwgdGhlIHBhcmFtZXRlcnMgcmVsYXRlZAp0byBs
Y2QgcGFuZWwsIHdlIGFyZSBwbGFjZWQgaW4gdGhlIERUUyB0byBjb25maWd1cmUsCmZvciBleGFt
cGxl77yMbGNkIGRpc3BsYXkgdGltaW5nLCBkcGkgcGFyYW1ldGVyIGFuZCBtb3JlLgoKQ2M6IE9y
c29uIFpoYWkgPG9yc29uemhhaUBnbWFpbC5jb20+CkNjOiBCYW9saW4gV2FuZyA8YmFvbGluLndh
bmdAbGluYXJvLm9yZz4KQ2M6IENodW55YW4gWmhhbmcgPHpoYW5nLmx5cmFAZ21haWwuY29tPgpT
aWduZWQtb2ZmLWJ5OiBLZXZpbiBUYW5nIDxrZXZpbi50YW5nQHVuaXNvYy5jb20+Ci0tLQogZHJp
dmVycy9ncHUvZHJtL3NwcmQvTWFrZWZpbGUgICAgIHwgICAzICstCiBkcml2ZXJzL2dwdS9kcm0v
c3ByZC9zcHJkX3BhbmVsLmMgfCA3NzggKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysr
KysrKysKIGRyaXZlcnMvZ3B1L2RybS9zcHJkL3NwcmRfcGFuZWwuaCB8IDExNCArKysrKysKIDMg
ZmlsZXMgY2hhbmdlZCwgODk0IGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkKIGNyZWF0ZSBt
b2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0vc3ByZC9zcHJkX3BhbmVsLmMKIGNyZWF0ZSBtb2Rl
IDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0vc3ByZC9zcHJkX3BhbmVsLmgKCmRpZmYgLS1naXQgYS9k
cml2ZXJzL2dwdS9kcm0vc3ByZC9NYWtlZmlsZSBiL2RyaXZlcnMvZ3B1L2RybS9zcHJkL01ha2Vm
aWxlCmluZGV4IDc4ZDNkZGIuLjMwYTU4MWMgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9z
cHJkL01ha2VmaWxlCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9zcHJkL01ha2VmaWxlCkBAIC04LDcg
KzgsOCBAQCBvYmoteSA6PSBzcHJkX2RybS5vIFwKIAlzcHJkX2dlbS5vIFwKIAlzcHJkX2RwdS5v
IFwKIAlzcHJkX2RzaS5vIFwKLQlzcHJkX2RwaHkubworCXNwcmRfZHBoeS5vIFwKKwlzcHJkX3Bh
bmVsLm8KIAogb2JqLXkgKz0gZGlzcF9saWIubwogb2JqLXkgKz0gZHB1LwpkaWZmIC0tZ2l0IGEv
ZHJpdmVycy9ncHUvZHJtL3NwcmQvc3ByZF9wYW5lbC5jIGIvZHJpdmVycy9ncHUvZHJtL3NwcmQv
c3ByZF9wYW5lbC5jCm5ldyBmaWxlIG1vZGUgMTAwNjQ0CmluZGV4IDAwMDAwMDAuLjRhNzBhMjAK
LS0tIC9kZXYvbnVsbAorKysgYi9kcml2ZXJzL2dwdS9kcm0vc3ByZC9zcHJkX3BhbmVsLmMKQEAg
LTAsMCArMSw3NzggQEAKKy8vIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBHUEwtMi4wCisvKgor
ICogQ29weXJpZ2h0IChDKSAyMDE5IFVuaXNvYyBJbmMuCisgKi8KKworI2luY2x1ZGUgPGRybS9k
cm1fYXRvbWljX2hlbHBlci5oPgorI2luY2x1ZGUgPGxpbnV4L2JhY2tsaWdodC5oPgorI2luY2x1
ZGUgPGxpbnV4L21vZHVsZS5oPgorI2luY2x1ZGUgPGxpbnV4L29mLmg+CisjaW5jbHVkZSA8bGlu
dXgvb2ZfZ3Bpby5oPgorI2luY2x1ZGUgPGxpbnV4L3BtX3J1bnRpbWUuaD4KKyNpbmNsdWRlIDx2
aWRlby9taXBpX2Rpc3BsYXkuaD4KKyNpbmNsdWRlIDx2aWRlby9vZl9kaXNwbGF5X3RpbWluZy5o
PgorI2luY2x1ZGUgPHZpZGVvL3ZpZGVvbW9kZS5oPgorCisjaW5jbHVkZSAic3ByZF9kcHUuaCIK
KyNpbmNsdWRlICJzcHJkX3BhbmVsLmgiCisjaW5jbHVkZSAiZHNpL3NwcmRfZHNpX2FwaS5oIgor
CisjZGVmaW5lIFNQUkRfTUlQSV9EU0lfRk1UX0RTQyAweGZmCitzdGF0aWMgREVGSU5FX01VVEVY
KHBhbmVsX2xvY2spOworCitzdGF0aWMgY29uc3QgY2hhciAqbGNkX25hbWU7CisKK3N0YXRpYyBp
bmxpbmUgc3RydWN0IHNwcmRfcGFuZWwgKnRvX3NwcmRfcGFuZWwoc3RydWN0IGRybV9wYW5lbCAq
cGFuZWwpCit7CisJcmV0dXJuIGNvbnRhaW5lcl9vZihwYW5lbCwgc3RydWN0IHNwcmRfcGFuZWws
IGJhc2UpOworfQorCitzdGF0aWMgaW50IHNwcmRfcGFuZWxfc2VuZF9jbWRzKHN0cnVjdCBtaXBp
X2RzaV9kZXZpY2UgKmRzaSwKKwkJCQljb25zdCB2b2lkICpkYXRhLCBpbnQgc2l6ZSkKK3sKKwlz
dHJ1Y3Qgc3ByZF9wYW5lbCAqcGFuZWw7CisJY29uc3Qgc3RydWN0IGRzaV9jbWRfZGVzYyAqY21k
cyA9IGRhdGE7CisJdTE2IGxlbjsKKworCWlmIChjbWRzID09IE5VTEwgfHwgZHNpID09IE5VTEwp
CisJCXJldHVybiAtRUlOVkFMOworCisJcGFuZWwgPSBtaXBpX2RzaV9nZXRfZHJ2ZGF0YShkc2kp
OworCisJd2hpbGUgKHNpemUgPiAwKSB7CisJCWxlbiA9IChjbWRzLT53Y19oIDw8IDgpIHwgY21k
cy0+d2NfbDsKKworCQlpZiAocGFuZWwtPmluZm8udXNlX2RjcykKKwkJCW1pcGlfZHNpX2Rjc193
cml0ZV9idWZmZXIoZHNpLCBjbWRzLT5wYXlsb2FkLCBsZW4pOworCQllbHNlCisJCQltaXBpX2Rz
aV9nZW5lcmljX3dyaXRlKGRzaSwgY21kcy0+cGF5bG9hZCwgbGVuKTsKKworCQlpZiAoY21kcy0+
d2FpdCkKKwkJCW1zbGVlcChjbWRzLT53YWl0KTsKKwkJY21kcyA9IChjb25zdCBzdHJ1Y3QgZHNp
X2NtZF9kZXNjICopKGNtZHMtPnBheWxvYWQgKyBsZW4pOworCQlzaXplIC09IChsZW4gKyA0KTsK
Kwl9CisKKwlyZXR1cm4gMDsKK30KKworc3RhdGljIGludCBzcHJkX3BhbmVsX3VucHJlcGFyZShz
dHJ1Y3QgZHJtX3BhbmVsICpwKQoreworCXN0cnVjdCBzcHJkX3BhbmVsICpwYW5lbCA9IHRvX3Nw
cmRfcGFuZWwocCk7CisJc3RydWN0IGdwaW9fdGltaW5nICp0aW1pbmc7CisJaW50IGl0ZW1zLCBp
OworCisJRFJNX0lORk8oIiVzKClcbiIsIF9fZnVuY19fKTsKKworCWlmIChwYW5lbC0+aW5mby5h
dmVlX2dwaW8pIHsKKwkJZ3Bpb2RfZGlyZWN0aW9uX291dHB1dChwYW5lbC0+aW5mby5hdmVlX2dw
aW8sIDApOworCQltZGVsYXkoNSk7CisJfQorCisJaWYgKHBhbmVsLT5pbmZvLmF2ZGRfZ3Bpbykg
eworCQlncGlvZF9kaXJlY3Rpb25fb3V0cHV0KHBhbmVsLT5pbmZvLmF2ZGRfZ3BpbywgMCk7CisJ
CW1kZWxheSg1KTsKKwl9CisKKwlpZiAocGFuZWwtPmluZm8ucmVzZXRfZ3BpbykgeworCQlpdGVt
cyA9IHBhbmVsLT5pbmZvLnJzdF9vZmZfc2VxLml0ZW1zOworCQl0aW1pbmcgPSBwYW5lbC0+aW5m
by5yc3Rfb2ZmX3NlcS50aW1pbmc7CisJCWZvciAoaSA9IDA7IGkgPCBpdGVtczsgaSsrKSB7CisJ
CQlncGlvZF9kaXJlY3Rpb25fb3V0cHV0KHBhbmVsLT5pbmZvLnJlc2V0X2dwaW8sCisJCQkJCQl0
aW1pbmdbaV0ubGV2ZWwpOworCQkJbWRlbGF5KHRpbWluZ1tpXS5kZWxheSk7CisJCX0KKwl9CisK
KwlyZWd1bGF0b3JfZGlzYWJsZShwYW5lbC0+c3VwcGx5KTsKKworCXJldHVybiAwOworfQorCitz
dGF0aWMgaW50IHNwcmRfcGFuZWxfcHJlcGFyZShzdHJ1Y3QgZHJtX3BhbmVsICpwKQoreworCXN0
cnVjdCBzcHJkX3BhbmVsICpwYW5lbCA9IHRvX3NwcmRfcGFuZWwocCk7CisJc3RydWN0IGdwaW9f
dGltaW5nICp0aW1pbmc7CisJaW50IGl0ZW1zLCBpLCByZXQ7CisKKwlEUk1fSU5GTygiJXMoKVxu
IiwgX19mdW5jX18pOworCisJcmV0ID0gcmVndWxhdG9yX2VuYWJsZShwYW5lbC0+c3VwcGx5KTsK
KwlpZiAocmV0IDwgMCkgeworCQlEUk1fRVJST1IoImVuYWJsZSBsY2QgcmVndWxhdG9yIGZhaWxl
ZFxuIik7CisJCXJldHVybiByZXQ7CisJfQorCisJaWYgKHBhbmVsLT5pbmZvLmF2ZGRfZ3Bpbykg
eworCQlncGlvZF9kaXJlY3Rpb25fb3V0cHV0KHBhbmVsLT5pbmZvLmF2ZGRfZ3BpbywgMSk7CisJ
CW1kZWxheSg1KTsKKwl9CisKKwlpZiAocGFuZWwtPmluZm8uYXZlZV9ncGlvKSB7CisJCWdwaW9k
X2RpcmVjdGlvbl9vdXRwdXQocGFuZWwtPmluZm8uYXZlZV9ncGlvLCAxKTsKKwkJbWRlbGF5KDUp
OworCX0KKworCWlmIChwYW5lbC0+aW5mby5yZXNldF9ncGlvKSB7CisJCWl0ZW1zID0gcGFuZWwt
PmluZm8ucnN0X29uX3NlcS5pdGVtczsKKwkJdGltaW5nID0gcGFuZWwtPmluZm8ucnN0X29uX3Nl
cS50aW1pbmc7CisJCWZvciAoaSA9IDA7IGkgPCBpdGVtczsgaSsrKSB7CisJCQlncGlvZF9kaXJl
Y3Rpb25fb3V0cHV0KHBhbmVsLT5pbmZvLnJlc2V0X2dwaW8sCisJCQkJCQl0aW1pbmdbaV0ubGV2
ZWwpOworCQkJbWRlbGF5KHRpbWluZ1tpXS5kZWxheSk7CisJCX0KKwl9CisKKwlyZXR1cm4gMDsK
K30KKworc3RhdGljIGludCBzcHJkX3BhbmVsX2Rpc2FibGUoc3RydWN0IGRybV9wYW5lbCAqcCkK
K3sKKwlzdHJ1Y3Qgc3ByZF9wYW5lbCAqcGFuZWwgPSB0b19zcHJkX3BhbmVsKHApOworCisJRFJN
X0lORk8oIiVzKClcbiIsIF9fZnVuY19fKTsKKworCW11dGV4X2xvY2soJnBhbmVsX2xvY2spOwor
CS8qCisJICogRklYTUU6CisJICogVGhlIGNhbmNlbCB3b3JrIHNob3VsZCBiZSBleGVjdXRlZCBi
ZWZvcmUgRFBVIHN0b3AsCisJICogb3RoZXJ3aXNlIHRoZSBlc2QgY2hlY2sgd2lsbCBiZSBmYWls
ZWQgaWYgdGhlIERQVQorCSAqIHN0b3BwZWQgaW4gdmlkZW8gbW9kZSBhbmQgdGhlIERTSSBoYXMg
bm90IGNoYW5nZSB0bworCSAqIENNRCBtb2RlIHlldC4gU2luY2UgdGhlcmUgaXMgbm8gVkJMQU5L
IHRpbWluZyBmb3IKKwkgKiBMUCBjbWQgdHJhbnNtaXNzaW9uLgorCSAqLworCWlmIChwYW5lbC0+
ZXNkX3dvcmtfcGVuZGluZykgeworCQljYW5jZWxfZGVsYXllZF93b3JrX3N5bmMoJnBhbmVsLT5l
c2Rfd29yayk7CisJCXBhbmVsLT5lc2Rfd29ya19wZW5kaW5nID0gZmFsc2U7CisJfQorCisJaWYg
KHBhbmVsLT5iYWNrbGlnaHQpIHsKKwkJcGFuZWwtPmJhY2tsaWdodC0+cHJvcHMucG93ZXIgPSBG
Ql9CTEFOS19QT1dFUkRPV047CisJCXBhbmVsLT5iYWNrbGlnaHQtPnByb3BzLnN0YXRlIHw9IEJM
X0NPUkVfRkJCTEFOSzsKKwkJYmFja2xpZ2h0X3VwZGF0ZV9zdGF0dXMocGFuZWwtPmJhY2tsaWdo
dCk7CisJfQorCisJc3ByZF9wYW5lbF9zZW5kX2NtZHMocGFuZWwtPnNsYXZlLAorCQkJICAgICBw
YW5lbC0+aW5mby5jbWRzW0NNRF9DT0RFX1NMRUVQX0lOXSwKKwkJCSAgICAgcGFuZWwtPmluZm8u
Y21kc19sZW5bQ01EX0NPREVfU0xFRVBfSU5dKTsKKworCXBhbmVsLT5pc19lbmFibGVkID0gZmFs
c2U7CisJbXV0ZXhfdW5sb2NrKCZwYW5lbF9sb2NrKTsKKworCXJldHVybiAwOworfQorCitzdGF0
aWMgaW50IHNwcmRfcGFuZWxfZW5hYmxlKHN0cnVjdCBkcm1fcGFuZWwgKnApCit7CisJc3RydWN0
IHNwcmRfcGFuZWwgKnBhbmVsID0gdG9fc3ByZF9wYW5lbChwKTsKKworCURSTV9JTkZPKCIlcygp
XG4iLCBfX2Z1bmNfXyk7CisKKwltdXRleF9sb2NrKCZwYW5lbF9sb2NrKTsKKwlzcHJkX3BhbmVs
X3NlbmRfY21kcyhwYW5lbC0+c2xhdmUsCisJCQkgICAgIHBhbmVsLT5pbmZvLmNtZHNbQ01EX0NP
REVfSU5JVF0sCisJCQkgICAgIHBhbmVsLT5pbmZvLmNtZHNfbGVuW0NNRF9DT0RFX0lOSVRdKTsK
KworCWlmIChwYW5lbC0+YmFja2xpZ2h0KSB7CisJCXBhbmVsLT5iYWNrbGlnaHQtPnByb3BzLnBv
d2VyID0gRkJfQkxBTktfVU5CTEFOSzsKKwkJcGFuZWwtPmJhY2tsaWdodC0+cHJvcHMuc3RhdGUg
Jj0gfkJMX0NPUkVfRkJCTEFOSzsKKwkJYmFja2xpZ2h0X3VwZGF0ZV9zdGF0dXMocGFuZWwtPmJh
Y2tsaWdodCk7CisJfQorCisJaWYgKHBhbmVsLT5pbmZvLmVzZF9jaGVja19lbikgeworCQlzY2hl
ZHVsZV9kZWxheWVkX3dvcmsoJnBhbmVsLT5lc2Rfd29yaywKKwkJCQkgICAgICBtc2Vjc190b19q
aWZmaWVzKDEwMDApKTsKKwkJcGFuZWwtPmVzZF93b3JrX3BlbmRpbmcgPSB0cnVlOworCX0KKwor
CXBhbmVsLT5pc19lbmFibGVkID0gdHJ1ZTsKKwltdXRleF91bmxvY2soJnBhbmVsX2xvY2spOwor
CisJcmV0dXJuIDA7Cit9CisKK3N0YXRpYyBpbnQgc3ByZF9wYW5lbF9nZXRfbW9kZXMoc3RydWN0
IGRybV9wYW5lbCAqcCkKK3sKKwlzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAqbW9kZTsKKwlzdHJ1
Y3Qgc3ByZF9wYW5lbCAqcGFuZWwgPSB0b19zcHJkX3BhbmVsKHApOworCXN0cnVjdCBkZXZpY2Vf
bm9kZSAqbnAgPSBwYW5lbC0+c2xhdmUtPmRldi5vZl9ub2RlOworCXUzMiBzdXJmYWNlX3dpZHRo
ID0gMCwgc3VyZmFjZV9oZWlnaHQgPSAwOworCWludCBpLCBtb2RlX2NvdW50ID0gMDsKKworCURS
TV9JTkZPKCIlcygpXG4iLCBfX2Z1bmNfXyk7CisJbW9kZSA9IGRybV9tb2RlX2R1cGxpY2F0ZShw
LT5kcm0sICZwYW5lbC0+aW5mby5tb2RlKTsKKwlpZiAoIW1vZGUpIHsKKwkJRFJNX0VSUk9SKCJm
YWlsZWQgdG8gYWxsb2MgbW9kZSAlc1xuIiwgcGFuZWwtPmluZm8ubW9kZS5uYW1lKTsKKwkJcmV0
dXJuIDA7CisJfQorCW1vZGUtPnR5cGUgPSBEUk1fTU9ERV9UWVBFX0RSSVZFUiB8IERSTV9NT0RF
X1RZUEVfUFJFRkVSUkVEOworCWRybV9tb2RlX3Byb2JlZF9hZGQocC0+Y29ubmVjdG9yLCBtb2Rl
KTsKKwltb2RlX2NvdW50Kys7CisKKwlmb3IgKGkgPSAxOyBpIDwgcGFuZWwtPmluZm8ubnVtX2J1
aWxkaW5fbW9kZXM7IGkrKykJeworCQltb2RlID0gZHJtX21vZGVfZHVwbGljYXRlKHAtPmRybSwK
KwkJCSYocGFuZWwtPmluZm8uYnVpbGRpbl9tb2Rlc1tpXSkpOworCQlpZiAoIW1vZGUpIHsKKwkJ
CURSTV9FUlJPUigiZmFpbGVkIHRvIGFsbG9jIG1vZGUgJXNcbiIsCisJCQkJcGFuZWwtPmluZm8u
YnVpbGRpbl9tb2Rlc1tpXS5uYW1lKTsKKwkJCXJldHVybiAwOworCQl9CisJCW1vZGUtPnR5cGUg
PSBEUk1fTU9ERV9UWVBFX0RSSVZFUiB8IERSTV9NT0RFX1RZUEVfREVGQVVMVDsKKwkJZHJtX21v
ZGVfcHJvYmVkX2FkZChwLT5jb25uZWN0b3IsIG1vZGUpOworCQltb2RlX2NvdW50Kys7CisJfQor
CisJb2ZfcHJvcGVydHlfcmVhZF91MzIobnAsICJzcHJkLHN1cmZhY2Utd2lkdGgiLCAmc3VyZmFj
ZV93aWR0aCk7CisJb2ZfcHJvcGVydHlfcmVhZF91MzIobnAsICJzcHJkLHN1cmZhY2UtaGVpZ2h0
IiwgJnN1cmZhY2VfaGVpZ2h0KTsKKwlpZiAoc3VyZmFjZV93aWR0aCAmJiBzdXJmYWNlX2hlaWdo
dCkgeworCQlzdHJ1Y3QgdmlkZW9tb2RlIHZtID0ge307CisKKwkJdm0uaGFjdGl2ZSA9IHN1cmZh
Y2Vfd2lkdGg7CisJCXZtLnZhY3RpdmUgPSBzdXJmYWNlX2hlaWdodDsKKwkJdm0ucGl4ZWxjbG9j
ayA9IHN1cmZhY2Vfd2lkdGggKiBzdXJmYWNlX2hlaWdodCAqIDYwOworCisJCW1vZGUgPSBkcm1f
bW9kZV9jcmVhdGUocC0+ZHJtKTsKKworCQltb2RlLT50eXBlID0gRFJNX01PREVfVFlQRV9EUklW
RVIgfCBEUk1fTU9ERV9UWVBFX0JVSUxUSU4gfAorCQkJRFJNX01PREVfVFlQRV9DUlRDX0M7CisJ
CW1vZGUtPnZyZWZyZXNoID0gNjA7CisJCWRybV9kaXNwbGF5X21vZGVfZnJvbV92aWRlb21vZGUo
JnZtLCBtb2RlKTsKKwkJZHJtX21vZGVfcHJvYmVkX2FkZChwLT5jb25uZWN0b3IsIG1vZGUpOwor
CQltb2RlX2NvdW50Kys7CisJfQorCisJcC0+Y29ubmVjdG9yLT5kaXNwbGF5X2luZm8ud2lkdGhf
bW0gPSBwYW5lbC0+aW5mby5tb2RlLndpZHRoX21tOworCXAtPmNvbm5lY3Rvci0+ZGlzcGxheV9p
bmZvLmhlaWdodF9tbSA9IHBhbmVsLT5pbmZvLm1vZGUuaGVpZ2h0X21tOworCisJcmV0dXJuIG1v
ZGVfY291bnQ7Cit9CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3QgZHJtX3BhbmVsX2Z1bmNzIHNwcmRf
cGFuZWxfZnVuY3MgPSB7CisJLmdldF9tb2RlcyA9IHNwcmRfcGFuZWxfZ2V0X21vZGVzLAorCS5l
bmFibGUgPSBzcHJkX3BhbmVsX2VuYWJsZSwKKwkuZGlzYWJsZSA9IHNwcmRfcGFuZWxfZGlzYWJs
ZSwKKwkucHJlcGFyZSA9IHNwcmRfcGFuZWxfcHJlcGFyZSwKKwkudW5wcmVwYXJlID0gc3ByZF9w
YW5lbF91bnByZXBhcmUsCit9OworCitzdGF0aWMgaW50IHNwcmRfcGFuZWxfZXNkX2NoZWNrKHN0
cnVjdCBzcHJkX3BhbmVsICpwYW5lbCkKK3sKKwlzdHJ1Y3QgcGFuZWxfaW5mbyAqaW5mbyA9ICZw
YW5lbC0+aW5mbzsKKwl1OCByZWFkX3ZhbCA9IDA7CisKKwkvKiBGSVhNRTogd2Ugc2hvdWxkIGVu
YWJsZSBIUyBjbWQgdHggaGVyZSAqLworCW1pcGlfZHNpX3NldF9tYXhpbXVtX3JldHVybl9wYWNr
ZXRfc2l6ZShwYW5lbC0+c2xhdmUsIDEpOworCW1pcGlfZHNpX2Rjc19yZWFkKHBhbmVsLT5zbGF2
ZSwgaW5mby0+ZXNkX2NoZWNrX3JlZywKKwkJCSAgJnJlYWRfdmFsLCAxKTsKKworCS8qCisJICog
VE9ETzoKKwkgKiBTaG91bGQgd2Ugc3VwcG9ydCBtdWx0aS1yZWdpc3RlcnMgY2hlY2sgaW4gdGhl
IGZ1dHVyZT8KKwkgKi8KKwlpZiAocmVhZF92YWwgIT0gaW5mby0+ZXNkX2NoZWNrX3ZhbCkgewor
CQlEUk1fRVJST1IoImVzZCBjaGVjayBmYWlsZWQsIHJlYWQgdmFsdWUgPSAweCUwMnhcbiIsCisJ
CQkgIHJlYWRfdmFsKTsKKwkJcmV0dXJuIC1FSU5WQUw7CisJfQorCisJcmV0dXJuIDA7Cit9CisK
K3N0YXRpYyBpbnQgc3ByZF9wYW5lbF90ZV9jaGVjayhzdHJ1Y3Qgc3ByZF9wYW5lbCAqcGFuZWwp
Cit7CisJc3RhdGljIGludCB0ZV93cV9pbml0ZWQ7CisJc3RydWN0IHNwcmRfZHB1ICpkcHU7CisJ
aW50IHJldDsKKwlib29sIGlycV9vY2N1cjsKKworCWlmICghcGFuZWwtPmJhc2UuY29ubmVjdG9y
IHx8CisJICAgICFwYW5lbC0+YmFzZS5jb25uZWN0b3ItPmVuY29kZXIgfHwKKwkgICAgIXBhbmVs
LT5iYXNlLmNvbm5lY3Rvci0+ZW5jb2Rlci0+Y3J0YykgeworCQlyZXR1cm4gMDsKKwl9CisKKwlk
cHUgPSBjb250YWluZXJfb2YocGFuZWwtPmJhc2UuY29ubmVjdG9yLT5lbmNvZGVyLT5jcnRjLAor
CQlzdHJ1Y3Qgc3ByZF9kcHUsIGNydGMpOworCisJaWYgKCF0ZV93cV9pbml0ZWQpIHsKKwkJaW5p
dF93YWl0cXVldWVfaGVhZCgmZHB1LT5jdHgudGVfd3EpOworCQl0ZV93cV9pbml0ZWQgPSAxOwor
CQlkcHUtPmN0eC5ldnRfdGUgPSBmYWxzZTsKKwkJRFJNX0lORk8oIiVzIGluaXQgdGUgd2FpdHF1
ZXVlXG4iLCBfX2Z1bmNfXyk7CisJfQorCisJLyogRFBVIFRFIGlycSBtYXliZSBlbmFibGVkIGlu
IGtlcm5lbCAqLworCWlmICghZHB1LT5jdHguaXNfaW5pdGVkKQorCQlyZXR1cm4gMDsKKworCWRw
dS0+Y3R4LnRlX2NoZWNrX2VuID0gdHJ1ZTsKKworCS8qIHdhaXQgZm9yIFRFIGludGVycnVwdCAq
LworCXJldCA9IHdhaXRfZXZlbnRfaW50ZXJydXB0aWJsZV90aW1lb3V0KGRwdS0+Y3R4LnRlX3dx
LAorCQlkcHUtPmN0eC5ldnRfdGUsIG1zZWNzX3RvX2ppZmZpZXMoNTAwKSk7CisJaWYgKCFyZXQp
IHsKKwkJLyogZG91YmxlIGNoZWNrIFRFIGludGVycnVwdCB0aHJvdWdoIGRwdV9pbnRfcmF3IHJl
Z2lzdGVyICovCisJCWlmIChkcHUtPmNvcmUgJiYgZHB1LT5jb3JlLT5jaGVja19yYXdfaW50KSB7
CisJCQlpcnFfb2NjdXIgPSBkcHUtPmNvcmUtPmNoZWNrX3Jhd19pbnQoJmRwdS0+Y3R4LAorCQkJ
CURJU1BDX0lOVF9URV9NQVNLKTsKKwkJCWlmICghaXJxX29jY3VyKSB7CisJCQkJRFJNX0VSUk9S
KCJURSBlc2QgdGltZW91dC5cbiIpOworCQkJCXJldCA9IC1FVElNRURPVVQ7CisJCQl9IGVsc2UK
KwkJCQlEUk1fV0FSTigiVEUgb2NjdXIsIGJ1dCBpc3Igc2NoZWR1bGUgZGVsYXlcbiIpOworCQl9
IGVsc2UgeworCQkJRFJNX0VSUk9SKCJURSBlc2QgdGltZW91dC5cbiIpOworCQkJcmV0ID0gLUVU
SU1FRE9VVDsKKwkJfQorCX0KKworCWRwdS0+Y3R4LnRlX2NoZWNrX2VuID0gZmFsc2U7CisJZHB1
LT5jdHguZXZ0X3RlID0gZmFsc2U7CisKKwlyZXR1cm4gcmV0IDwgMCA/IHJldCA6IDA7Cit9CisK
K3N0YXRpYyB2b2lkIHNwcmRfcGFuZWxfZXNkX3dvcmtfZnVuYyhzdHJ1Y3Qgd29ya19zdHJ1Y3Qg
KndvcmspCit7CisJc3RydWN0IHNwcmRfcGFuZWwgKnBhbmVsID0gY29udGFpbmVyX29mKHdvcmss
IHN0cnVjdCBzcHJkX3BhbmVsLAorCQkJCQkJZXNkX3dvcmsud29yayk7CisJc3RydWN0IHBhbmVs
X2luZm8gKmluZm8gPSAmcGFuZWwtPmluZm87CisJaW50IHJldDsKKworCWlmIChpbmZvLT5lc2Rf
Y2hlY2tfbW9kZSA9PSBFU0RfTU9ERV9SRUdfQ0hFQ0spCisJCXJldCA9IHNwcmRfcGFuZWxfZXNk
X2NoZWNrKHBhbmVsKTsKKwllbHNlIGlmIChpbmZvLT5lc2RfY2hlY2tfbW9kZSA9PSBFU0RfTU9E
RV9URV9DSEVDSykKKwkJcmV0ID0gc3ByZF9wYW5lbF90ZV9jaGVjayhwYW5lbCk7CisJZWxzZSB7
CisJCURSTV9FUlJPUigidW5rbm93biBlc2QgY2hlY2sgbW9kZTolZFxuIiwgaW5mby0+ZXNkX2No
ZWNrX21vZGUpOworCQlyZXR1cm47CisJfQorCisJaWYgKHJldCAmJiBwYW5lbC0+YmFzZS5jb25u
ZWN0b3IgJiYgcGFuZWwtPmJhc2UuY29ubmVjdG9yLT5lbmNvZGVyKSB7CisJCWNvbnN0IHN0cnVj
dCBkcm1fZW5jb2Rlcl9oZWxwZXJfZnVuY3MgKmZ1bmNzOworCQlzdHJ1Y3QgZHJtX2VuY29kZXIg
KmVuY29kZXI7CisKKwkJZW5jb2RlciA9IHBhbmVsLT5iYXNlLmNvbm5lY3Rvci0+ZW5jb2RlcjsK
KwkJZnVuY3MgPSBlbmNvZGVyLT5oZWxwZXJfcHJpdmF0ZTsKKwkJcGFuZWwtPmVzZF93b3JrX3Bl
bmRpbmcgPSBmYWxzZTsKKworCQlpZiAoZW5jb2Rlci0+Y3J0YyAmJiBlbmNvZGVyLT5jcnRjLT5z
dGF0ZSAmJgorCQkgICAgIWVuY29kZXItPmNydGMtPnN0YXRlLT5hY3RpdmUpIHsKKwkJCURSTV9J
TkZPKCJza2lwIGVzZCByZWNvdmVyeSBkdXJpbmcgcGFuZWwgc3VzcGVuZFxuIik7CisJCQlyZXR1
cm47CisJCX0KKworCQlEUk1fSU5GTygiPT09PT09IGVzZCByZWNvdmVyeSBzdGFydCA9PT09PT09
PVxuIik7CisJCWZ1bmNzLT5kaXNhYmxlKGVuY29kZXIpOworCisJCWlmICghZW5jb2Rlci0+Y3J0
Yy0+c3RhdGUtPmFjdGl2ZSkgeworCQkJRFJNX0lORk8oInNraXAgZXNkIHJlY292ZXJ5IGlmIHBh
bmVsIHN1c3BlbmRcbiIpOworCQkJcmV0dXJuOworCQl9CisJCWZ1bmNzLT5lbmFibGUoZW5jb2Rl
cik7CisJCURSTV9JTkZPKCI9PT09PT09IGVzZCByZWNvdmVyeSBlbmQgPT09PT09PT09XG4iKTsK
Kwl9IGVsc2UKKwkJc2NoZWR1bGVfZGVsYXllZF93b3JrKCZwYW5lbC0+ZXNkX3dvcmssCisJCQlt
c2Vjc190b19qaWZmaWVzKGluZm8tPmVzZF9jaGVja19wZXJpb2QpKTsKK30KKworc3RhdGljIGlu
dCBzcHJkX3BhbmVsX2dwaW9fcmVxdWVzdChzdHJ1Y3QgZGV2aWNlICpkZXYsCisJCQlzdHJ1Y3Qg
c3ByZF9wYW5lbCAqcGFuZWwpCit7CisJcGFuZWwtPmluZm8uYXZkZF9ncGlvID0gZGV2bV9ncGlv
ZF9nZXRfb3B0aW9uYWwoZGV2LAorCQkJCQkiYXZkZCIsIEdQSU9EX0FTSVMpOworCWlmIChJU19F
UlJfT1JfTlVMTChwYW5lbC0+aW5mby5hdmRkX2dwaW8pKQorCQlEUk1fV0FSTigiY2FuJ3QgZ2V0
IHBhbmVsIGF2ZGQgZ3BpbzogJWxkXG4iLAorCQkJCSBQVFJfRVJSKHBhbmVsLT5pbmZvLmF2ZGRf
Z3BpbykpOworCisJcGFuZWwtPmluZm8uYXZlZV9ncGlvID0gZGV2bV9ncGlvZF9nZXRfb3B0aW9u
YWwoZGV2LAorCQkJCQkiYXZlZSIsIEdQSU9EX0FTSVMpOworCWlmIChJU19FUlJfT1JfTlVMTChw
YW5lbC0+aW5mby5hdmVlX2dwaW8pKQorCQlEUk1fV0FSTigiY2FuJ3QgZ2V0IHBhbmVsIGF2ZWUg
Z3BpbzogJWxkXG4iLAorCQkJCSBQVFJfRVJSKHBhbmVsLT5pbmZvLmF2ZWVfZ3BpbykpOworCisJ
cGFuZWwtPmluZm8ucmVzZXRfZ3BpbyA9IGRldm1fZ3Bpb2RfZ2V0X29wdGlvbmFsKGRldiwKKwkJ
CQkJInJlc2V0IiwgR1BJT0RfQVNJUyk7CisJaWYgKElTX0VSUl9PUl9OVUxMKHBhbmVsLT5pbmZv
LnJlc2V0X2dwaW8pKQorCQlEUk1fV0FSTigiY2FuJ3QgZ2V0IHBhbmVsIHJlc2V0IGdwaW86ICVs
ZFxuIiwKKwkJCQkgUFRSX0VSUihwYW5lbC0+aW5mby5yZXNldF9ncGlvKSk7CisKKwlyZXR1cm4g
MDsKK30KKworc3RhdGljIGludCBvZl9wYXJzZV9yZXNldF9zZXEoc3RydWN0IGRldmljZV9ub2Rl
ICpucCwKKwkJCQlzdHJ1Y3QgcGFuZWxfaW5mbyAqaW5mbykKK3sKKwlzdHJ1Y3QgcHJvcGVydHkg
KnByb3A7CisJaW50IGJ5dGVzLCByYzsKKwl1MzIgKnA7CisKKwlwcm9wID0gb2ZfZmluZF9wcm9w
ZXJ0eShucCwgInNwcmQscmVzZXQtb24tc2VxdWVuY2UiLCAmYnl0ZXMpOworCWlmICghcHJvcCkg
eworCQlEUk1fRVJST1IoInNwcmQscmVzZXQtb24tc2VxdWVuY2UgcHJvcGVydHkgbm90IGZvdW5k
XG4iKTsKKwkJcmV0dXJuIC1FSU5WQUw7CisJfQorCisJcCA9IGt6YWxsb2MoYnl0ZXMsIEdGUF9L
RVJORUwpOworCWlmICghcCkKKwkJcmV0dXJuIC1FTk9NRU07CisJcmMgPSBvZl9wcm9wZXJ0eV9y
ZWFkX3UzMl9hcnJheShucCwgInNwcmQscmVzZXQtb24tc2VxdWVuY2UiLAorCQkJCQlwLCBieXRl
cyAvIDQpOworCWlmIChyYykgeworCQlEUk1fRVJST1IoInBhcnNlIHNwcmQscmVzZXQtb24tc2Vx
dWVuY2UgZmFpbGVkXG4iKTsKKwkJa2ZyZWUocCk7CisJCXJldHVybiByYzsKKwl9CisKKwlpbmZv
LT5yc3Rfb25fc2VxLml0ZW1zID0gYnl0ZXMgLyA4OworCWluZm8tPnJzdF9vbl9zZXEudGltaW5n
ID0gKHN0cnVjdCBncGlvX3RpbWluZyAqKXA7CisKKwlwcm9wID0gb2ZfZmluZF9wcm9wZXJ0eShu
cCwgInNwcmQscmVzZXQtb2ZmLXNlcXVlbmNlIiwgJmJ5dGVzKTsKKwlpZiAoIXByb3ApIHsKKwkJ
RFJNX0VSUk9SKCJzcHJkLHJlc2V0LW9mZi1zZXF1ZW5jZSBwcm9wZXJ0eSBub3QgZm91bmRcbiIp
OworCQlyZXR1cm4gLUVJTlZBTDsKKwl9CisKKwlwID0ga3phbGxvYyhieXRlcywgR0ZQX0tFUk5F
TCk7CisJaWYgKCFwKQorCQlyZXR1cm4gLUVOT01FTTsKKwlyYyA9IG9mX3Byb3BlcnR5X3JlYWRf
dTMyX2FycmF5KG5wLCAic3ByZCxyZXNldC1vZmYtc2VxdWVuY2UiLAorCQkJCQlwLCBieXRlcyAv
IDQpOworCWlmIChyYykgeworCQlEUk1fRVJST1IoInBhcnNlIHNwcmQscmVzZXQtb2ZmLXNlcXVl
bmNlIGZhaWxlZFxuIik7CisJCWtmcmVlKHApOworCQlyZXR1cm4gcmM7CisJfQorCisJaW5mby0+
cnN0X29mZl9zZXEuaXRlbXMgPSBieXRlcyAvIDg7CisJaW5mby0+cnN0X29mZl9zZXEudGltaW5n
ID0gKHN0cnVjdCBncGlvX3RpbWluZyAqKXA7CisKKwlyZXR1cm4gMDsKK30KKworc3RhdGljIGlu
dCBvZl9wYXJzZV9idWlsZGluX21vZGVzKHN0cnVjdCBwYW5lbF9pbmZvICppbmZvLAorCXN0cnVj
dCBkZXZpY2Vfbm9kZSAqbGNkX25vZGUpCit7CisJaW50IGksIHJjLCBudW1fdGltaW5nczsKKwlz
dHJ1Y3QgZGV2aWNlX25vZGUgKnRpbWluZ3NfbnA7CisKKworCXRpbWluZ3NfbnAgPSBvZl9nZXRf
Y2hpbGRfYnlfbmFtZShsY2Rfbm9kZSwgImRpc3BsYXktdGltaW5ncyIpOworCWlmICghdGltaW5n
c19ucCkgeworCQlEUk1fRVJST1IoIiVzOiBjYW4gbm90IGZpbmQgZGlzcGxheS10aW1pbmdzIG5v
ZGVcbiIsCisJCQlsY2Rfbm9kZS0+bmFtZSk7CisJCXJldHVybiAtRU5PREVWOworCX0KKworCW51
bV90aW1pbmdzID0gb2ZfZ2V0X2NoaWxkX2NvdW50KHRpbWluZ3NfbnApOworCWlmIChudW1fdGlt
aW5ncyA9PSAwKSB7CisJCS8qIHNob3VsZCBuZXZlciBoYXBwZW4sIGFzIGVudHJ5IHdhcyBhbHJl
YWR5IGZvdW5kIGFib3ZlICovCisJCURSTV9FUlJPUigiJXM6IG5vIHRpbWluZ3Mgc3BlY2lmaWVk
XG4iLCBsY2Rfbm9kZS0+bmFtZSk7CisJCWdvdG8gZG9uZTsKKwl9CisKKwlpbmZvLT5idWlsZGlu
X21vZGVzID0ga3phbGxvYyhzaXplb2Yoc3RydWN0IGRybV9kaXNwbGF5X21vZGUpICoKKwkJCQlu
dW1fdGltaW5ncywgR0ZQX0tFUk5FTCk7CisKKwlmb3IgKGkgPSAwOyBpIDwgbnVtX3RpbWluZ3M7
IGkrKykgeworCQlyYyA9IG9mX2dldF9kcm1fZGlzcGxheV9tb2RlKGxjZF9ub2RlLAorCQkJJmlu
Zm8tPmJ1aWxkaW5fbW9kZXNbaV0sIE5VTEwsIGkpOworCQlpZiAocmMpIHsKKwkJCURSTV9FUlJP
UigiZ2V0IGRpc3BsYXkgdGltaW5nIGZhaWxlZFxuIik7CisJCQlnb3RvIGVudHJ5ZmFpbDsKKwkJ
fQorCisJCWluZm8tPmJ1aWxkaW5fbW9kZXNbaV0ud2lkdGhfbW0gPSBpbmZvLT5tb2RlLndpZHRo
X21tOworCQlpbmZvLT5idWlsZGluX21vZGVzW2ldLmhlaWdodF9tbSA9IGluZm8tPm1vZGUuaGVp
Z2h0X21tOworCQlpbmZvLT5idWlsZGluX21vZGVzW2ldLnZyZWZyZXNoID0gaW5mby0+bW9kZS52
cmVmcmVzaDsKKwl9CisJaW5mby0+bnVtX2J1aWxkaW5fbW9kZXMgPSBudW1fdGltaW5nczsKKwlE
Uk1fSU5GTygiaW5mby0+bnVtX2J1aWxkaW5fbW9kZXMgPSAlZFxuIiwgbnVtX3RpbWluZ3MpOwor
CWdvdG8gZG9uZTsKKworZW50cnlmYWlsOgorCWtmcmVlKGluZm8tPmJ1aWxkaW5fbW9kZXMpOwor
ZG9uZToKKwlvZl9ub2RlX3B1dCh0aW1pbmdzX25wKTsKKworCXJldHVybiAwOworfQorCitzdGF0
aWMgaW50IHNwcmRfcGFuZWxfcGFyc2VfZHQoc3RydWN0IGRldmljZV9ub2RlICpucCwgc3RydWN0
IHNwcmRfcGFuZWwgKnBhbmVsKQoreworCXUzMiB2YWw7CisJc3RydWN0IGRldmljZV9ub2RlICps
Y2Rfbm9kZTsKKwlzdHJ1Y3QgcGFuZWxfaW5mbyAqaW5mbyA9ICZwYW5lbC0+aW5mbzsKKwlpbnQg
Ynl0ZXMsIHJjOworCWNvbnN0IHZvaWQgKnA7CisJY29uc3QgY2hhciAqc3RyOworCWNoYXIgbGNk
X3BhdGhbNjBdOworCisJc3ByaW50ZihsY2RfcGF0aCwgIi9sY2RzLyVzIiwgbGNkX25hbWUpOwor
CWxjZF9ub2RlID0gb2ZfZmluZF9ub2RlX2J5X3BhdGgobGNkX3BhdGgpOworCWlmICghbGNkX25v
ZGUpIHsKKwkJRFJNX0VSUk9SKCIlcE9GOiBjb3VsZCBub3QgZmluZCAlcyBub2RlXG4iLCBucCwg
bGNkX25hbWUpOworCQlyZXR1cm4gLUVOT0RFVjsKKwl9CisJaW5mby0+b2Zfbm9kZSA9IGxjZF9u
b2RlOworCisJcmMgPSBvZl9wcm9wZXJ0eV9yZWFkX3UzMihsY2Rfbm9kZSwgInNwcmQsZHNpLXdv
cmstbW9kZSIsICZ2YWwpOworCWlmICghcmMpIHsKKwkJaWYgKHZhbCA9PSBTUFJEX0RTSV9NT0RF
X0NNRCkKKwkJCWluZm8tPm1vZGVfZmxhZ3MgPSAwOworCQllbHNlIGlmICh2YWwgPT0gU1BSRF9E
U0lfTU9ERV9WSURFT19CVVJTVCkKKwkJCWluZm8tPm1vZGVfZmxhZ3MgPSBNSVBJX0RTSV9NT0RF
X1ZJREVPIHwKKwkJCQkJICAgTUlQSV9EU0lfTU9ERV9WSURFT19CVVJTVDsKKwkJZWxzZSBpZiAo
dmFsID09IFNQUkRfRFNJX01PREVfVklERU9fU1lOQ19QVUxTRSkKKwkJCWluZm8tPm1vZGVfZmxh
Z3MgPSBNSVBJX0RTSV9NT0RFX1ZJREVPIHwKKwkJCQkJICAgTUlQSV9EU0lfTU9ERV9WSURFT19T
WU5DX1BVTFNFOworCQllbHNlIGlmICh2YWwgPT0gU1BSRF9EU0lfTU9ERV9WSURFT19TWU5DX0VW
RU5UKQorCQkJaW5mby0+bW9kZV9mbGFncyA9IE1JUElfRFNJX01PREVfVklERU87CisJfSBlbHNl
IHsKKwkJRFJNX0VSUk9SKCJkc2kgd29yayBtb2RlIGlzIG5vdCBmb3VuZCEgdXNlIHZpZGVvIG1v
ZGVcbiIpOworCQlpbmZvLT5tb2RlX2ZsYWdzID0gTUlQSV9EU0lfTU9ERV9WSURFTyB8CisJCQkJ
ICAgTUlQSV9EU0lfTU9ERV9WSURFT19CVVJTVDsKKwl9CisKKwlpZiAob2ZfcHJvcGVydHlfcmVh
ZF9ib29sKGxjZF9ub2RlLCAic3ByZCxkc2ktbm9uLWNvbnRpbnVvdXMtY2xvY2siKSkKKwkJaW5m
by0+bW9kZV9mbGFncyB8PSBNSVBJX0RTSV9DTE9DS19OT05fQ09OVElOVU9VUzsKKworCXJjID0g
b2ZfcHJvcGVydHlfcmVhZF91MzIobGNkX25vZGUsICJzcHJkLGRzaS1sYW5lLW51bWJlciIsICZ2
YWwpOworCWlmICghcmMpCisJCWluZm8tPmxhbmVzID0gdmFsOworCWVsc2UKKwkJaW5mby0+bGFu
ZXMgPSA0OworCisJcmMgPSBvZl9wcm9wZXJ0eV9yZWFkX3N0cmluZyhsY2Rfbm9kZSwgInNwcmQs
ZHNpLWNvbG9yLWZvcm1hdCIsICZzdHIpOworCWlmIChyYykKKwkJaW5mby0+Zm9ybWF0ID0gTUlQ
SV9EU0lfRk1UX1JHQjg4ODsKKwllbHNlIGlmICghc3RyY21wKHN0ciwgInJnYjg4OCIpKQorCQlp
bmZvLT5mb3JtYXQgPSBNSVBJX0RTSV9GTVRfUkdCODg4OworCWVsc2UgaWYgKCFzdHJjbXAoc3Ry
LCAicmdiNjY2IikpCisJCWluZm8tPmZvcm1hdCA9IE1JUElfRFNJX0ZNVF9SR0I2NjY7CisJZWxz
ZSBpZiAoIXN0cmNtcChzdHIsICJyZ2I2NjZfcGFja2VkIikpCisJCWluZm8tPmZvcm1hdCA9IE1J
UElfRFNJX0ZNVF9SR0I2NjZfUEFDS0VEOworCWVsc2UgaWYgKCFzdHJjbXAoc3RyLCAicmdiNTY1
IikpCisJCWluZm8tPmZvcm1hdCA9IE1JUElfRFNJX0ZNVF9SR0I1NjU7CisJZWxzZSBpZiAoIXN0
cmNtcChzdHIsICJkc2MiKSkKKwkJaW5mby0+Zm9ybWF0ID0gU1BSRF9NSVBJX0RTSV9GTVRfRFND
OworCWVsc2UKKwkJRFJNX0VSUk9SKCJkc2ktY29sb3ItZm9ybWF0ICglcykgaXMgbm90IHN1cHBv
cnRlZFxuIiwgc3RyKTsKKworCXJjID0gb2ZfcHJvcGVydHlfcmVhZF91MzIobGNkX25vZGUsICJ3
aWR0aC1tbSIsICZ2YWwpOworCWlmICghcmMpCisJCWluZm8tPm1vZGUud2lkdGhfbW0gPSB2YWw7
CisJZWxzZQorCQlpbmZvLT5tb2RlLndpZHRoX21tID0gNjg7CisKKwlyYyA9IG9mX3Byb3BlcnR5
X3JlYWRfdTMyKGxjZF9ub2RlLCAiaGVpZ2h0LW1tIiwgJnZhbCk7CisJaWYgKCFyYykKKwkJaW5m
by0+bW9kZS5oZWlnaHRfbW0gPSB2YWw7CisJZWxzZQorCQlpbmZvLT5tb2RlLmhlaWdodF9tbSA9
IDEyMTsKKworCXJjID0gb2ZfcHJvcGVydHlfcmVhZF91MzIobGNkX25vZGUsICJzcHJkLGVzZC1j
aGVjay1lbmFibGUiLCAmdmFsKTsKKwlpZiAoIXJjKQorCQlpbmZvLT5lc2RfY2hlY2tfZW4gPSB2
YWw7CisKKwlyYyA9IG9mX3Byb3BlcnR5X3JlYWRfdTMyKGxjZF9ub2RlLCAic3ByZCxlc2QtY2hl
Y2stbW9kZSIsICZ2YWwpOworCWlmICghcmMpCisJCWluZm8tPmVzZF9jaGVja19tb2RlID0gdmFs
OworCWVsc2UKKwkJaW5mby0+ZXNkX2NoZWNrX21vZGUgPSAxOworCisJcmMgPSBvZl9wcm9wZXJ0
eV9yZWFkX3UzMihsY2Rfbm9kZSwgInNwcmQsZXNkLWNoZWNrLXBlcmlvZCIsICZ2YWwpOworCWlm
ICghcmMpCisJCWluZm8tPmVzZF9jaGVja19wZXJpb2QgPSB2YWw7CisJZWxzZQorCQlpbmZvLT5l
c2RfY2hlY2tfcGVyaW9kID0gMTAwMDsKKworCXJjID0gb2ZfcHJvcGVydHlfcmVhZF91MzIobGNk
X25vZGUsICJzcHJkLGVzZC1jaGVjay1yZWdpc3RlciIsICZ2YWwpOworCWlmICghcmMpCisJCWlu
Zm8tPmVzZF9jaGVja19yZWcgPSB2YWw7CisJZWxzZQorCQlpbmZvLT5lc2RfY2hlY2tfcmVnID0g
MHgwQTsKKworCXJjID0gb2ZfcHJvcGVydHlfcmVhZF91MzIobGNkX25vZGUsICJzcHJkLGVzZC1j
aGVjay12YWx1ZSIsICZ2YWwpOworCWlmICghcmMpCisJCWluZm8tPmVzZF9jaGVja192YWwgPSB2
YWw7CisJZWxzZQorCQlpbmZvLT5lc2RfY2hlY2tfdmFsID0gMHg5QzsKKworCWlmIChvZl9wcm9w
ZXJ0eV9yZWFkX2Jvb2wobGNkX25vZGUsICJzcHJkLHVzZS1kY3Mtd3JpdGUiKSkKKwkJaW5mby0+
dXNlX2RjcyA9IHRydWU7CisJZWxzZQorCQlpbmZvLT51c2VfZGNzID0gZmFsc2U7CisKKwlyYyA9
IG9mX3BhcnNlX3Jlc2V0X3NlcShsY2Rfbm9kZSwgaW5mbyk7CisJaWYgKHJjKQorCQlEUk1fRVJS
T1IoInBhcnNlIGxjZCByZXNldCBzZXF1ZW5jZSBmYWlsZWRcbiIpOworCisJcCA9IG9mX2dldF9w
cm9wZXJ0eShsY2Rfbm9kZSwgInNwcmQsaW5pdGlhbC1jb21tYW5kIiwgJmJ5dGVzKTsKKwlpZiAo
cCkgeworCQlpbmZvLT5jbWRzW0NNRF9DT0RFX0lOSVRdID0gcDsKKwkJaW5mby0+Y21kc19sZW5b
Q01EX0NPREVfSU5JVF0gPSBieXRlczsKKwl9IGVsc2UKKwkJRFJNX0VSUk9SKCJjYW4ndCBmaW5k
IHNwcmQsaW5pdGlhbC1jb21tYW5kIHByb3BlcnR5XG4iKTsKKworCXAgPSBvZl9nZXRfcHJvcGVy
dHkobGNkX25vZGUsICJzcHJkLHNsZWVwLWluLWNvbW1hbmQiLCAmYnl0ZXMpOworCWlmIChwKSB7
CisJCWluZm8tPmNtZHNbQ01EX0NPREVfU0xFRVBfSU5dID0gcDsKKwkJaW5mby0+Y21kc19sZW5b
Q01EX0NPREVfU0xFRVBfSU5dID0gYnl0ZXM7CisJfSBlbHNlCisJCURSTV9FUlJPUigiY2FuJ3Qg
ZmluZCBzcHJkLHNsZWVwLWluLWNvbW1hbmQgcHJvcGVydHlcbiIpOworCisJcCA9IG9mX2dldF9w
cm9wZXJ0eShsY2Rfbm9kZSwgInNwcmQsc2xlZXAtb3V0LWNvbW1hbmQiLCAmYnl0ZXMpOworCWlm
IChwKSB7CisJCWluZm8tPmNtZHNbQ01EX0NPREVfU0xFRVBfT1VUXSA9IHA7CisJCWluZm8tPmNt
ZHNfbGVuW0NNRF9DT0RFX1NMRUVQX09VVF0gPSBieXRlczsKKwl9IGVsc2UKKwkJRFJNX0VSUk9S
KCJjYW4ndCBmaW5kIHNwcmQsc2xlZXAtb3V0LWNvbW1hbmQgcHJvcGVydHlcbiIpOworCisJcmMg
PSBvZl9nZXRfZHJtX2Rpc3BsYXlfbW9kZShsY2Rfbm9kZSwgJmluZm8tPm1vZGUsIDAsCisJCQkJ
ICAgICBPRl9VU0VfTkFUSVZFX01PREUpOworCWlmIChyYykgeworCQlEUk1fRVJST1IoImdldCBk
aXNwbGF5IHRpbWluZyBmYWlsZWRcbiIpOworCQlyZXR1cm4gcmM7CisJfQorCisJaW5mby0+bW9k
ZS52cmVmcmVzaCA9IGRybV9tb2RlX3ZyZWZyZXNoKCZpbmZvLT5tb2RlKTsKKwlvZl9wYXJzZV9i
dWlsZGluX21vZGVzKGluZm8sIGxjZF9ub2RlKTsKKworCXJldHVybiAwOworfQorCitzdGF0aWMg
aW50IHNwcmRfcGFuZWxfcHJvYmUoc3RydWN0IG1pcGlfZHNpX2RldmljZSAqc2xhdmUpCit7CisJ
aW50IHJldDsKKwlzdHJ1Y3Qgc3ByZF9wYW5lbCAqcGFuZWw7CisJc3RydWN0IGRldmljZV9ub2Rl
ICpibF9ub2RlOworCisJcGFuZWwgPSBkZXZtX2t6YWxsb2MoJnNsYXZlLT5kZXYsIHNpemVvZigq
cGFuZWwpLCBHRlBfS0VSTkVMKTsKKwlpZiAoIXBhbmVsKQorCQlyZXR1cm4gLUVOT01FTTsKKwor
CWJsX25vZGUgPSBvZl9wYXJzZV9waGFuZGxlKHNsYXZlLT5kZXYub2Zfbm9kZSwKKwkJCQkJInNw
cmQsYmFja2xpZ2h0IiwgMCk7CisJaWYgKGJsX25vZGUpIHsKKwkJcGFuZWwtPmJhY2tsaWdodCA9
IG9mX2ZpbmRfYmFja2xpZ2h0X2J5X25vZGUoYmxfbm9kZSk7CisJCW9mX25vZGVfcHV0KGJsX25v
ZGUpOworCisJCWlmIChwYW5lbC0+YmFja2xpZ2h0KSB7CisJCQlwYW5lbC0+YmFja2xpZ2h0LT5w
cm9wcy5zdGF0ZSAmPSB+QkxfQ09SRV9GQkJMQU5LOworCQkJcGFuZWwtPmJhY2tsaWdodC0+cHJv
cHMucG93ZXIgPSBGQl9CTEFOS19VTkJMQU5LOworCQkJYmFja2xpZ2h0X3VwZGF0ZV9zdGF0dXMo
cGFuZWwtPmJhY2tsaWdodCk7CisJCX0gZWxzZSB7CisJCQlEUk1fV0FSTigiYmFja2xpZ2h0IGlz
IG5vdCByZWFkeSwgcGFuZWwgcHJvYmUgZGVmZXJyZWRcbiIpOworCQkJcmV0dXJuIC1FUFJPQkVf
REVGRVI7CisJCX0KKwl9IGVsc2UKKwkJRFJNX1dBUk4oImJhY2tsaWdodCBub2RlIG5vdCBmb3Vu
ZFxuIik7CisKKwlwYW5lbC0+c3VwcGx5ID0gZGV2bV9yZWd1bGF0b3JfZ2V0KCZzbGF2ZS0+ZGV2
LCAicG93ZXIiKTsKKwlpZiAoSVNfRVJSKHBhbmVsLT5zdXBwbHkpKSB7CisJCWlmIChQVFJfRVJS
KHBhbmVsLT5zdXBwbHkpID09IC1FUFJPQkVfREVGRVIpCisJCQlEUk1fRVJST1IoInJlZ3VsYXRv
ciBkcml2ZXIgbm90IGluaXRpYWxpemVkLCBwcm9iZSBkZWZmZXJcbiIpOworCQllbHNlCisJCQlE
Uk1fRVJST1IoImNhbid0IGdldCByZWd1bGF0b3I6ICVsZFxuIiwgUFRSX0VSUihwYW5lbC0+c3Vw
cGx5KSk7CisKKwkJcmV0dXJuIFBUUl9FUlIocGFuZWwtPnN1cHBseSk7CisJfQorCisJSU5JVF9E
RUxBWUVEX1dPUksoJnBhbmVsLT5lc2Rfd29yaywgc3ByZF9wYW5lbF9lc2Rfd29ya19mdW5jKTsK
KworCXJldCA9IHNwcmRfcGFuZWxfcGFyc2VfZHQoc2xhdmUtPmRldi5vZl9ub2RlLCBwYW5lbCk7
CisJaWYgKHJldCkgeworCQlEUk1fRVJST1IoInBhcnNlIHBhbmVsIGluZm8gZmFpbGVkXG4iKTsK
KwkJcmV0dXJuIHJldDsKKwl9CisKKwlyZXQgPSBzcHJkX3BhbmVsX2dwaW9fcmVxdWVzdCgmc2xh
dmUtPmRldiwgcGFuZWwpOworCWlmIChyZXQpIHsKKwkJRFJNX1dBUk4oImdwaW8gaXMgbm90IHJl
YWR5LCBwYW5lbCBwcm9iZSBkZWZlcnJlZFxuIik7CisJCXJldHVybiAtRVBST0JFX0RFRkVSOwor
CX0KKworCWRybV9wYW5lbF9pbml0KCZwYW5lbC0+YmFzZSwgJnBhbmVsLT5kZXYsCisJCSZzcHJk
X3BhbmVsX2Z1bmNzLCBEUk1fTU9ERV9DT05ORUNUT1JfRFNJKTsKKworCXJldCA9IGRybV9wYW5l
bF9hZGQoJnBhbmVsLT5iYXNlKTsKKwlpZiAocmV0KSB7CisJCURSTV9FUlJPUigiZHJtX3BhbmVs
X2FkZCgpIGZhaWxlZFxuIik7CisJCXJldHVybiByZXQ7CisJfQorCisJc2xhdmUtPmxhbmVzID0g
cGFuZWwtPmluZm8ubGFuZXM7CisJc2xhdmUtPmZvcm1hdCA9IHBhbmVsLT5pbmZvLmZvcm1hdDsK
KwlzbGF2ZS0+bW9kZV9mbGFncyA9IHBhbmVsLT5pbmZvLm1vZGVfZmxhZ3M7CisKKwlyZXQgPSBt
aXBpX2RzaV9hdHRhY2goc2xhdmUpOworCWlmIChyZXQpIHsKKwkJRFJNX0VSUk9SKCJmYWlsZWQg
dG8gYXR0YWNoIGRzaSBwYW5lbCB0byBob3N0XG4iKTsKKwkJZHJtX3BhbmVsX3JlbW92ZSgmcGFu
ZWwtPmJhc2UpOworCQlyZXR1cm4gcmV0OworCX0KKwlwYW5lbC0+c2xhdmUgPSBzbGF2ZTsKKwor
CW1pcGlfZHNpX3NldF9kcnZkYXRhKHNsYXZlLCBwYW5lbCk7CisKKwkvKgorCSAqIEZJWE1FOgor
CSAqIFRoZSBlc2QgY2hlY2sgd29yayBzaG91bGQgbm90IGJlIHNjaGVkdWxlZCBpbiBwcm9iZQor
CSAqIGZ1bmN0aW9uLiBJdCBzaG91bGQgYmUgc2NoZWR1bGVkIGluIHRoZSBlbmFibGUoKQorCSAq
IGNhbGxiYWNrIGZ1bmN0aW9uLiBCdXQgdGhlIGRzaSBlbmNvZGVyIHdpbGwgbm90IGNhbGwKKwkg
KiBkcm1fcGFuZWxfZW5hYmxlKCkgdGhlIGZpcnN0IHRpbWUgaW4gZW5jb2Rlcl9lbmFibGUoKS4K
KwkgKi8KKwlpZiAocGFuZWwtPmluZm8uZXNkX2NoZWNrX2VuKSB7CisJCXNjaGVkdWxlX2RlbGF5
ZWRfd29yaygmcGFuZWwtPmVzZF93b3JrLAorCQkJCSAgICAgIG1zZWNzX3RvX2ppZmZpZXMoMjAw
MCkpOworCQlwYW5lbC0+ZXNkX3dvcmtfcGVuZGluZyA9IHRydWU7CisJfQorCisJcGFuZWwtPmlz
X2VuYWJsZWQgPSB0cnVlOworCisJRFJNX0lORk8oInBhbmVsIGRyaXZlciBwcm9iZSBzdWNjZXNz
XG4iKTsKKworCXJldHVybiAwOworfQorCitzdGF0aWMgaW50IHNwcmRfcGFuZWxfcmVtb3ZlKHN0
cnVjdCBtaXBpX2RzaV9kZXZpY2UgKnNsYXZlKQoreworCXN0cnVjdCBzcHJkX3BhbmVsICpwYW5l
bCA9IG1pcGlfZHNpX2dldF9kcnZkYXRhKHNsYXZlKTsKKwlpbnQgcmV0OworCisJRFJNX0lORk8o
IiVzKClcbiIsIF9fZnVuY19fKTsKKworCXNwcmRfcGFuZWxfZGlzYWJsZSgmcGFuZWwtPmJhc2Up
OworCXNwcmRfcGFuZWxfdW5wcmVwYXJlKCZwYW5lbC0+YmFzZSk7CisKKwlyZXQgPSBtaXBpX2Rz
aV9kZXRhY2goc2xhdmUpOworCWlmIChyZXQgPCAwKQorCQlEUk1fRVJST1IoImZhaWxlZCB0byBk
ZXRhY2ggZnJvbSBEU0kgaG9zdDogJWRcbiIsIHJldCk7CisKKwlkcm1fcGFuZWxfZGV0YWNoKCZw
YW5lbC0+YmFzZSk7CisJZHJtX3BhbmVsX3JlbW92ZSgmcGFuZWwtPmJhc2UpOworCisJcmV0dXJu
IDA7Cit9CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIHBhbmVsX29mX21hdGNo
W10gPSB7CisJeyAuY29tcGF0aWJsZSA9ICJzcHJkLGdlbmVyaWMtbWlwaS1wYW5lbCIsIH0sCisJ
eyB9Cit9OworTU9EVUxFX0RFVklDRV9UQUJMRShvZiwgcGFuZWxfb2ZfbWF0Y2gpOworCitzdGF0
aWMgc3RydWN0IG1pcGlfZHNpX2RyaXZlciBzcHJkX3BhbmVsX2RyaXZlciA9IHsKKwkuZHJpdmVy
ID0geworCQkubmFtZSA9ICJzcHJkLW1pcGktcGFuZWwtZHJ2IiwKKwkJLm9mX21hdGNoX3RhYmxl
ID0gcGFuZWxfb2ZfbWF0Y2gsCisJfSwKKwkucHJvYmUgPSBzcHJkX3BhbmVsX3Byb2JlLAorCS5y
ZW1vdmUgPSBzcHJkX3BhbmVsX3JlbW92ZSwKK307Cittb2R1bGVfbWlwaV9kc2lfZHJpdmVyKHNw
cmRfcGFuZWxfZHJpdmVyKTsKKworTU9EVUxFX0FVVEhPUigiTGVvbiBIZSA8bGVvbi5oZUB1bmlz
b2MuY29tPiIpOworTU9EVUxFX0FVVEhPUigiS2V2aW4gVGFuZyA8a2V2aW4udGFuZ0B1bmlzb2Mu
Y29tPiIpOworTU9EVUxFX0RFU0NSSVBUSU9OKCJVbmlzb2MgTUlQSSBEU0kgUGFuZWwgRHJpdmVy
Iik7CitNT0RVTEVfTElDRU5TRSgiR1BMIHYyIik7CmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9k
cm0vc3ByZC9zcHJkX3BhbmVsLmggYi9kcml2ZXJzL2dwdS9kcm0vc3ByZC9zcHJkX3BhbmVsLmgK
bmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMC4uMjE2Y2Q0YgotLS0gL2Rldi9udWxs
CisrKyBiL2RyaXZlcnMvZ3B1L2RybS9zcHJkL3NwcmRfcGFuZWwuaApAQCAtMCwwICsxLDExNCBA
QAorLyogU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAgKi8KKy8qCisgKiBDb3B5cmln
aHQgKEMpIDIwMTkgVW5pc29jIEluYy4KKyAqLworCisjaWZuZGVmIF9TUFJEX1BBTkVMX0hfCisj
ZGVmaW5lIF9TUFJEX1BBTkVMX0hfCisKKyNpbmNsdWRlIDxsaW51eC9iYWNrbGlnaHQuaD4KKyNp
bmNsdWRlIDxsaW51eC9vZi5oPgorI2luY2x1ZGUgPGxpbnV4L3JlZ3VsYXRvci9jb25zdW1lci5o
PgorI2luY2x1ZGUgPGxpbnV4L3dvcmtxdWV1ZS5oPgorCisjaW5jbHVkZSA8ZHJtL2RybV9taXBp
X2RzaS5oPgorI2luY2x1ZGUgPGRybS9kcm1fbW9kZXMuaD4KKyNpbmNsdWRlIDxkcm0vZHJtX3Bh
bmVsLmg+CisjaW5jbHVkZSA8ZHJtL2RybV9wcmludC5oPgorCitlbnVtIHsKKwlDTURfQ09ERV9J
TklUID0gMCwKKwlDTURfQ09ERV9TTEVFUF9JTiwKKwlDTURfQ09ERV9TTEVFUF9PVVQsCisJQ01E
X09MRURfQlJJR0hUTkVTUywKKwlDTURfT0xFRF9SRUdfTE9DSywKKwlDTURfT0xFRF9SRUdfVU5M
T0NLLAorCUNNRF9DT0RFX1JFU0VSVkVEMCwKKwlDTURfQ09ERV9SRVNFUlZFRDEsCisJQ01EX0NP
REVfUkVTRVJWRUQyLAorCUNNRF9DT0RFX1JFU0VSVkVEMywKKwlDTURfQ09ERV9SRVNFUlZFRDQs
CisJQ01EX0NPREVfUkVTRVJWRUQ1LAorCUNNRF9DT0RFX01BWCwKK307CisKK2VudW0geworCVNQ
UkRfRFNJX01PREVfQ01EID0gMCwKKwlTUFJEX0RTSV9NT0RFX1ZJREVPX0JVUlNULAorCVNQUkRf
RFNJX01PREVfVklERU9fU1lOQ19QVUxTRSwKKwlTUFJEX0RTSV9NT0RFX1ZJREVPX1NZTkNfRVZF
TlQsCit9OworCitlbnVtIHsKKwlFU0RfTU9ERV9SRUdfQ0hFQ0ssCisJRVNEX01PREVfVEVfQ0hF
Q0ssCit9OworCitzdHJ1Y3QgZHNpX2NtZF9kZXNjIHsKKwl1OCBkYXRhX3R5cGU7CisJdTggd2Fp
dDsKKwl1OCB3Y19oOworCXU4IHdjX2w7CisJdTggcGF5bG9hZFtdOworfTsKKworc3RydWN0IGdw
aW9fdGltaW5nIHsKKwl1MzIgbGV2ZWw7CisJdTMyIGRlbGF5OworfTsKKworc3RydWN0IHJlc2V0
X3NlcXVlbmNlIHsKKwl1MzIgaXRlbXM7CisJc3RydWN0IGdwaW9fdGltaW5nICp0aW1pbmc7Cit9
OworCitzdHJ1Y3QgcGFuZWxfaW5mbyB7CisJLyogY29tbW9uIHBhcmFtZXRlcnMgKi8KKwlzdHJ1
Y3QgZGV2aWNlX25vZGUgKm9mX25vZGU7CisJc3RydWN0IGRybV9kaXNwbGF5X21vZGUgbW9kZTsK
KwlzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAqYnVpbGRpbl9tb2RlczsKKwlpbnQgbnVtX2J1aWxk
aW5fbW9kZXM7CisJc3RydWN0IGdwaW9fZGVzYyAqYXZkZF9ncGlvOworCXN0cnVjdCBncGlvX2Rl
c2MgKmF2ZWVfZ3BpbzsKKwlzdHJ1Y3QgZ3Bpb19kZXNjICpyZXNldF9ncGlvOworCXN0cnVjdCBy
ZXNldF9zZXF1ZW5jZSByc3Rfb25fc2VxOworCXN0cnVjdCByZXNldF9zZXF1ZW5jZSByc3Rfb2Zm
X3NlcTsKKwljb25zdCB2b2lkICpjbWRzW0NNRF9DT0RFX01BWF07CisJaW50IGNtZHNfbGVuW0NN
RF9DT0RFX01BWF07CisKKwkvKiBlc2QgY2hlY2sgcGFyYW1ldGVycyovCisJYm9vbCBlc2RfY2hl
Y2tfZW47CisJdTggZXNkX2NoZWNrX21vZGU7CisJdTE2IGVzZF9jaGVja19wZXJpb2Q7CisJdTMy
IGVzZF9jaGVja19yZWc7CisJdTMyIGVzZF9jaGVja192YWw7CisKKwkvKiBNSVBJIERTSSBzcGVj
aWZpYyBwYXJhbWV0ZXJzICovCisJdTMyIGZvcm1hdDsKKwl1MzIgbGFuZXM7CisJdTMyIG1vZGVf
ZmxhZ3M7CisJYm9vbCB1c2VfZGNzOworfTsKKworc3RydWN0IHNwcmRfcGFuZWwgeworCXN0cnVj
dCBkZXZpY2UgZGV2OworCXN0cnVjdCBkcm1fcGFuZWwgYmFzZTsKKwlzdHJ1Y3QgbWlwaV9kc2lf
ZGV2aWNlICpzbGF2ZTsKKwlzdHJ1Y3QgcGFuZWxfaW5mbyBpbmZvOworCXN0cnVjdCBiYWNrbGln
aHRfZGV2aWNlICpiYWNrbGlnaHQ7CisJc3RydWN0IHJlZ3VsYXRvciAqc3VwcGx5OworCXN0cnVj
dCBkZWxheWVkX3dvcmsgZXNkX3dvcms7CisJYm9vbCBlc2Rfd29ya19wZW5kaW5nOworCWJvb2wg
aXNfZW5hYmxlZDsKK307CisKK3N0cnVjdCBzcHJkX29sZWQgeworCXN0cnVjdCBiYWNrbGlnaHRf
ZGV2aWNlICpiZGV2OworCXN0cnVjdCBzcHJkX3BhbmVsICpwYW5lbDsKKwlzdHJ1Y3QgZHNpX2Nt
ZF9kZXNjICpjbWRzWzI1NV07CisJaW50IGNtZF9sZW47CisJaW50IGNtZHNfdG90YWw7CisJaW50
IG1heF9sZXZlbDsKK307CisKKyNlbmRpZgotLSAKMi43LjQKCl9fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRl
dmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9t
YWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo=