From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MIME_BASE64_TEXT,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19287C43603 for ; Wed, 18 Dec 2019 08:31:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C9F7224672 for ; Wed, 18 Dec 2019 08:31:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="lq6UXcM3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726921AbfLRIbW (ORCPT ); Wed, 18 Dec 2019 03:31:22 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:13541 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726787AbfLRIbN (ORCPT ); Wed, 18 Dec 2019 03:31:13 -0500 X-UUID: 9e571695cb72479985a6fa7fe4e77aa1-20191218 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=a5FCEy2BZm61QcAEPy9+kPZfwRGbVTTgU0WkpB3/H0E=; b=lq6UXcM3E29Sj4VNDoaapn85HP2B5047kCPd/KQGUErgb87X7kvomIQHEfwUwTI4rDHHyV9LLjs4X5YH3EygTXCZCum3kblqcPwz+ZhcgAEcE94SrwPbU/ECWqsDTic1FmINNQvYVsiLsqRFPuKiUNQYTMrmPWZg+r/61wJ3h/Q=; X-UUID: 9e571695cb72479985a6fa7fe4e77aa1-20191218 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1305820243; Wed, 18 Dec 2019 16:30:59 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 18 Dec 2019 16:30:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 18 Dec 2019 16:30:30 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Rob Herring , Sascha Hauer CC: James Liao , Fan Chen , , , , , Weiyi Lu Subject: [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support Date: Wed, 18 Dec 2019 16:30:43 +0800 Message-ID: <1576657848-14711-8-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1576657848-14711-1-git-send-email-weiyi.lu@mediatek.com> References: <1576657848-14711-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SW4gcHJldmlvdXMgcGF0Y2hlcywgd2UgaW50cm9kdWNlIHNjcHN5cy1leHQgZHJpdmVyIHRoYXQg Y292ZXJzDQp0aGUgZnVuY3Rpb25zIHdoaWNoIGluZnJhY2ZnIG1pc2MgZHJpdmVyIHByb3ZpZGVk Lg0KQW5kIHRoZW4gcmVwbGFjZSBidXNfcHJvdF9tYXNrIHdpdGggYnBfdGFibGUgb2YgYWxsIGNv bXBhdGlibGVzLg0KTm93LCB3ZSdyZSBnb2luZyB0byByZW1vdmUgaW5mcmFjZmcgbWlzYyBkcnZp ZXIgd2hpY2ggaXMgbm8gbG9uZ2VyDQpiZWluZyB1c2VkLg0KDQpTaWduZWQtb2ZmLWJ5OiBXZWl5 aSBMdSA8d2VpeWkubHVAbWVkaWF0ZWsuY29tPg0KLS0tDQogZHJpdmVycy9zb2MvbWVkaWF0ZWsv S2NvbmZpZyAgICAgICAgICB8IDEwIC0tLS0tDQogZHJpdmVycy9zb2MvbWVkaWF0ZWsvTWFrZWZp bGUgICAgICAgICB8ICAzICstDQogZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXRrLWluZnJhY2ZnLmMg ICB8IDc5IC0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tDQogaW5jbHVkZS9saW51 eC9zb2MvbWVkaWF0ZWsvaW5mcmFjZmcuaCB8IDM5IC0tLS0tLS0tLS0tLS0tLS0tDQogNCBmaWxl cyBjaGFuZ2VkLCAxIGluc2VydGlvbigrKSwgMTMwIGRlbGV0aW9ucygtKQ0KIGRlbGV0ZSBtb2Rl IDEwMDY0NCBkcml2ZXJzL3NvYy9tZWRpYXRlay9tdGstaW5mcmFjZmcuYw0KIGRlbGV0ZSBtb2Rl IDEwMDY0NCBpbmNsdWRlL2xpbnV4L3NvYy9tZWRpYXRlay9pbmZyYWNmZy5oDQoNCmRpZmYgLS1n aXQgYS9kcml2ZXJzL3NvYy9tZWRpYXRlay9LY29uZmlnIGIvZHJpdmVycy9zb2MvbWVkaWF0ZWsv S2NvbmZpZw0KaW5kZXggMjExNGI1Ni4uZjgzN2IzYyAxMDA2NDQNCi0tLSBhL2RyaXZlcnMvc29j L21lZGlhdGVrL0tjb25maWcNCisrKyBiL2RyaXZlcnMvc29jL21lZGlhdGVrL0tjb25maWcNCkBA IC0xMCwyMSArMTAsMTIgQEAgY29uZmlnIE1US19DTURRDQogCWRlcGVuZHMgb24gQVJDSF9NRURJ QVRFSyB8fCBDT01QSUxFX1RFU1QNCiAJc2VsZWN0IE1BSUxCT1gNCiAJc2VsZWN0IE1US19DTURR X01CT1gNCi0Jc2VsZWN0IE1US19JTkZSQUNGRw0KIAloZWxwDQogCSAgU2F5IHllcyBoZXJlIHRv IGFkZCBzdXBwb3J0IGZvciB0aGUgTWVkaWFUZWsgQ29tbWFuZCBRdWV1ZSAoQ01EUSkNCiAJICBk cml2ZXIuIFRoZSBDTURRIGlzIHVzZWQgdG8gaGVscCByZWFkL3dyaXRlIHJlZ2lzdGVycyB3aXRo IGNyaXRpY2FsDQogCSAgdGltZSBsaW1pdGF0aW9uLCBzdWNoIGFzIHVwZGF0aW5nIGRpc3BsYXkg Y29uZmlndXJhdGlvbiBkdXJpbmcgdGhlDQogCSAgdmJsYW5rLg0KIA0KLWNvbmZpZyBNVEtfSU5G UkFDRkcNCi0JYm9vbCAiTWVkaWFUZWsgSU5GUkFDRkcgU3VwcG9ydCINCi0Jc2VsZWN0IFJFR01B UA0KLQloZWxwDQotCSAgU2F5IHllcyBoZXJlIHRvIGFkZCBzdXBwb3J0IGZvciB0aGUgTWVkaWFU ZWsgSU5GUkFDRkcgY29udHJvbGxlci4gVGhlDQotCSAgSU5GUkFDRkcgY29udHJvbGxlciBjb250 YWlucyB2YXJpb3VzIGluZnJhc3RydWN0dXJlIHJlZ2lzdGVycyBub3QNCi0JICBkaXJlY3RseSBh c3NvY2lhdGVkIHRvIGFueSBkZXZpY2UuDQotDQogY29uZmlnIE1US19QTUlDX1dSQVANCiAJdHJp c3RhdGUgIk1lZGlhVGVrIFBNSUMgV3JhcHBlciBTdXBwb3J0Ig0KIAlkZXBlbmRzIG9uIFJFU0VU X0NPTlRST0xMRVINCkBAIC0zOCw3ICsyOSw2IEBAIGNvbmZpZyBNVEtfU0NQU1lTDQogCWJvb2wg Ik1lZGlhVGVrIFNDUFNZUyBTdXBwb3J0Ig0KIAlkZWZhdWx0IEFSQ0hfTUVESUFURUsNCiAJc2Vs ZWN0IFJFR01BUA0KLQlzZWxlY3QgTVRLX0lORlJBQ0ZHDQogCXNlbGVjdCBQTV9HRU5FUklDX0RP TUFJTlMgaWYgUE0NCiAJaGVscA0KIAkgIFNheSB5ZXMgaGVyZSB0byBhZGQgc3VwcG9ydCBmb3Ig dGhlIE1lZGlhVGVrIFNDUFNZUyBwb3dlciBkb21haW4NCmRpZmYgLS1naXQgYS9kcml2ZXJzL3Nv Yy9tZWRpYXRlay9NYWtlZmlsZSBiL2RyaXZlcnMvc29jL21lZGlhdGVrL01ha2VmaWxlDQppbmRl eCBiNDQyYmU5Li43YmY3ZTg4IDEwMDY0NA0KLS0tIGEvZHJpdmVycy9zb2MvbWVkaWF0ZWsvTWFr ZWZpbGUNCisrKyBiL2RyaXZlcnMvc29jL21lZGlhdGVrL01ha2VmaWxlDQpAQCAtMSw1ICsxLDQg QEANCiAjIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBHUEwtMi4wLW9ubHkNCiBvYmotJChDT05G SUdfTVRLX0NNRFEpICs9IG10ay1jbWRxLWhlbHBlci5vDQotb2JqLSQoQ09ORklHX01US19JTkZS QUNGRykgKz0gbXRrLWluZnJhY2ZnLm8gbXRrLXNjcHN5cy1leHQubw0KIG9iai0kKENPTkZJR19N VEtfUE1JQ19XUkFQKSArPSBtdGstcG1pYy13cmFwLm8NCi1vYmotJChDT05GSUdfTVRLX1NDUFNZ UykgKz0gbXRrLXNjcHN5cy5vDQorb2JqLSQoQ09ORklHX01US19TQ1BTWVMpICs9IG10ay1zY3Bz eXMubyBtdGstc2Nwc3lzLWV4dC5vDQpkaWZmIC0tZ2l0IGEvZHJpdmVycy9zb2MvbWVkaWF0ZWsv bXRrLWluZnJhY2ZnLmMgYi9kcml2ZXJzL3NvYy9tZWRpYXRlay9tdGstaW5mcmFjZmcuYw0KZGVs ZXRlZCBmaWxlIG1vZGUgMTAwNjQ0DQppbmRleCAzNDFjN2FjLi4wMDAwMDAwDQotLS0gYS9kcml2 ZXJzL3NvYy9tZWRpYXRlay9tdGstaW5mcmFjZmcuYw0KKysrIC9kZXYvbnVsbA0KQEAgLTEsNzkg KzAsMCBAQA0KLS8vIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBHUEwtMi4wLW9ubHkNCi0vKg0K LSAqIENvcHlyaWdodCAoYykgMjAxNSBQZW5ndXRyb25peCwgU2FzY2hhIEhhdWVyIDxrZXJuZWxA cGVuZ3V0cm9uaXguZGU+DQotICovDQotDQotI2luY2x1ZGUgPGxpbnV4L2V4cG9ydC5oPg0KLSNp bmNsdWRlIDxsaW51eC9qaWZmaWVzLmg+DQotI2luY2x1ZGUgPGxpbnV4L3JlZ21hcC5oPg0KLSNp bmNsdWRlIDxsaW51eC9zb2MvbWVkaWF0ZWsvaW5mcmFjZmcuaD4NCi0jaW5jbHVkZSA8YXNtL3By b2Nlc3Nvci5oPg0KLQ0KLSNkZWZpbmUgTVRLX1BPTExfREVMQVlfVVMgICAxMA0KLSNkZWZpbmUg TVRLX1BPTExfVElNRU9VVCAgICAoamlmZmllc190b191c2VjcyhIWikpDQotDQotI2RlZmluZSBJ TkZSQV9UT1BBWElfUFJPVEVDVEVOCQkweDAyMjANCi0jZGVmaW5lIElORlJBX1RPUEFYSV9QUk9U RUNUU1RBMQkweDAyMjgNCi0jZGVmaW5lIElORlJBX1RPUEFYSV9QUk9URUNURU5fU0VUCTB4MDI2 MA0KLSNkZWZpbmUgSU5GUkFfVE9QQVhJX1BST1RFQ1RFTl9DTFIJMHgwMjY0DQotDQotLyoqDQot ICogbXRrX2luZnJhY2ZnX3NldF9idXNfcHJvdGVjdGlvbiAtIGVuYWJsZSBidXMgcHJvdGVjdGlv bg0KLSAqIEByZWdtYXA6IFRoZSBpbmZyYWNmZyByZWdtYXANCi0gKiBAbWFzazogVGhlIG1hc2sg Y29udGFpbmluZyB0aGUgcHJvdGVjdGlvbiBiaXRzIHRvIGJlIGVuYWJsZWQuDQotICogQHJlZ191 cGRhdGU6IFRoZSBib29sZWFuIGZsYWcgZGV0ZXJtaW5lcyB0byBzZXQgdGhlIHByb3RlY3Rpb24g Yml0cw0KLSAqICAgICAgICAgICAgICBieSByZWdtYXBfdXBkYXRlX2JpdHMgd2l0aCBlbmFibGUg cmVnaXN0ZXIoUFJPVEVDVEVOKSBvcg0KLSAqICAgICAgICAgICAgICBieSByZWdtYXBfd3JpdGUg d2l0aCBzZXQgcmVnaXN0ZXIoUFJPVEVDVEVOX1NFVCkuDQotICoNCi0gKiBUaGlzIGZ1bmN0aW9u IGVuYWJsZXMgdGhlIGJ1cyBwcm90ZWN0aW9uIGJpdHMgZm9yIGRpc2FibGVkIHBvd2VyDQotICog ZG9tYWlucyBzbyB0aGF0IHRoZSBzeXN0ZW0gZG9lcyBub3QgaGFuZyB3aGVuIHNvbWUgdW5pdCBh Y2Nlc3NlcyB0aGUNCi0gKiBidXMgd2hpbGUgaW4gcG93ZXIgZG93bi4NCi0gKi8NCi1pbnQgbXRr X2luZnJhY2ZnX3NldF9idXNfcHJvdGVjdGlvbihzdHJ1Y3QgcmVnbWFwICppbmZyYWNmZywgdTMy IG1hc2ssDQotCQlib29sIHJlZ191cGRhdGUpDQotew0KLQl1MzIgdmFsOw0KLQlpbnQgcmV0Ow0K LQ0KLQlpZiAocmVnX3VwZGF0ZSkNCi0JCXJlZ21hcF91cGRhdGVfYml0cyhpbmZyYWNmZywgSU5G UkFfVE9QQVhJX1BST1RFQ1RFTiwgbWFzaywNCi0JCQkJbWFzayk7DQotCWVsc2UNCi0JCXJlZ21h cF93cml0ZShpbmZyYWNmZywgSU5GUkFfVE9QQVhJX1BST1RFQ1RFTl9TRVQsIG1hc2spOw0KLQ0K LQlyZXQgPSByZWdtYXBfcmVhZF9wb2xsX3RpbWVvdXQoaW5mcmFjZmcsIElORlJBX1RPUEFYSV9Q Uk9URUNUU1RBMSwNCi0JCQkJICAgICAgIHZhbCwgKHZhbCAmIG1hc2spID09IG1hc2ssDQotCQkJ CSAgICAgICBNVEtfUE9MTF9ERUxBWV9VUywgTVRLX1BPTExfVElNRU9VVCk7DQotDQotCXJldHVy biByZXQ7DQotfQ0KLQ0KLS8qKg0KLSAqIG10a19pbmZyYWNmZ19jbGVhcl9idXNfcHJvdGVjdGlv biAtIGRpc2FibGUgYnVzIHByb3RlY3Rpb24NCi0gKiBAcmVnbWFwOiBUaGUgaW5mcmFjZmcgcmVn bWFwDQotICogQG1hc2s6IFRoZSBtYXNrIGNvbnRhaW5pbmcgdGhlIHByb3RlY3Rpb24gYml0cyB0 byBiZSBkaXNhYmxlZC4NCi0gKiBAcmVnX3VwZGF0ZTogVGhlIGJvb2xlYW4gZmxhZyBkZXRlcm1p bmVzIHRvIGNsZWFyIHRoZSBwcm90ZWN0aW9uIGJpdHMNCi0gKiAgICAgICAgICAgICAgYnkgcmVn bWFwX3VwZGF0ZV9iaXRzIHdpdGggZW5hYmxlIHJlZ2lzdGVyKFBST1RFQ1RFTikgb3INCi0gKiAg ICAgICAgICAgICAgYnkgcmVnbWFwX3dyaXRlIHdpdGggY2xlYXIgcmVnaXN0ZXIoUFJPVEVDVEVO X0NMUikuDQotICoNCi0gKiBUaGlzIGZ1bmN0aW9uIGRpc2FibGVzIHRoZSBidXMgcHJvdGVjdGlv biBiaXRzIHByZXZpb3VzbHkgZW5hYmxlZCB3aXRoDQotICogbXRrX2luZnJhY2ZnX3NldF9idXNf cHJvdGVjdGlvbi4NCi0gKi8NCi0NCi1pbnQgbXRrX2luZnJhY2ZnX2NsZWFyX2J1c19wcm90ZWN0 aW9uKHN0cnVjdCByZWdtYXAgKmluZnJhY2ZnLCB1MzIgbWFzaywNCi0JCWJvb2wgcmVnX3VwZGF0 ZSkNCi17DQotCWludCByZXQ7DQotCXUzMiB2YWw7DQotDQotCWlmIChyZWdfdXBkYXRlKQ0KLQkJ cmVnbWFwX3VwZGF0ZV9iaXRzKGluZnJhY2ZnLCBJTkZSQV9UT1BBWElfUFJPVEVDVEVOLCBtYXNr LCAwKTsNCi0JZWxzZQ0KLQkJcmVnbWFwX3dyaXRlKGluZnJhY2ZnLCBJTkZSQV9UT1BBWElfUFJP VEVDVEVOX0NMUiwgbWFzayk7DQotDQotCXJldCA9IHJlZ21hcF9yZWFkX3BvbGxfdGltZW91dChp bmZyYWNmZywgSU5GUkFfVE9QQVhJX1BST1RFQ1RTVEExLA0KLQkJCQkgICAgICAgdmFsLCAhKHZh bCAmIG1hc2spLA0KLQkJCQkgICAgICAgTVRLX1BPTExfREVMQVlfVVMsIE1US19QT0xMX1RJTUVP VVQpOw0KLQ0KLQlyZXR1cm4gcmV0Ow0KLX0NCmRpZmYgLS1naXQgYS9pbmNsdWRlL2xpbnV4L3Nv Yy9tZWRpYXRlay9pbmZyYWNmZy5oIGIvaW5jbHVkZS9saW51eC9zb2MvbWVkaWF0ZWsvaW5mcmFj ZmcuaA0KZGVsZXRlZCBmaWxlIG1vZGUgMTAwNjQ0DQppbmRleCBmZDI1ZjAxLi4wMDAwMDAwDQot LS0gYS9pbmNsdWRlL2xpbnV4L3NvYy9tZWRpYXRlay9pbmZyYWNmZy5oDQorKysgL2Rldi9udWxs DQpAQCAtMSwzOSArMCwwIEBADQotLyogU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAg Ki8NCi0jaWZuZGVmIF9fU09DX01FRElBVEVLX0lORlJBQ0ZHX0gNCi0jZGVmaW5lIF9fU09DX01F RElBVEVLX0lORlJBQ0ZHX0gNCi0NCi0jZGVmaW5lIE1UODE3M19UT1BfQVhJX1BST1RfRU5fTUNJ X00yCQlCSVQoMCkNCi0jZGVmaW5lIE1UODE3M19UT1BfQVhJX1BST1RfRU5fTU1fTTAJCUJJVCgx KQ0KLSNkZWZpbmUgTVQ4MTczX1RPUF9BWElfUFJPVF9FTl9NTV9NMQkJQklUKDIpDQotI2RlZmlu ZSBNVDgxNzNfVE9QX0FYSV9QUk9UX0VOX01NQVBCX1MJCUJJVCg2KQ0KLSNkZWZpbmUgTVQ4MTcz X1RPUF9BWElfUFJPVF9FTl9MMkNfTTIJCUJJVCg5KQ0KLSNkZWZpbmUgTVQ4MTczX1RPUF9BWElf UFJPVF9FTl9MMlNTX1NNSQkJQklUKDExKQ0KLSNkZWZpbmUgTVQ4MTczX1RPUF9BWElfUFJPVF9F Tl9MMlNTX0FERAkJQklUKDEyKQ0KLSNkZWZpbmUgTVQ4MTczX1RPUF9BWElfUFJPVF9FTl9DQ0lf TTIJCUJJVCgxMykNCi0jZGVmaW5lIE1UODE3M19UT1BfQVhJX1BST1RfRU5fTUZHX1MJCUJJVCgx NCkNCi0jZGVmaW5lIE1UODE3M19UT1BfQVhJX1BST1RfRU5fUEVSSV9NMAkJQklUKDE1KQ0KLSNk ZWZpbmUgTVQ4MTczX1RPUF9BWElfUFJPVF9FTl9QRVJJX00xCQlCSVQoMTYpDQotI2RlZmluZSBN VDgxNzNfVE9QX0FYSV9QUk9UX0VOX0RFQlVHU1lTCQlCSVQoMTcpDQotI2RlZmluZSBNVDgxNzNf VE9QX0FYSV9QUk9UX0VOX0NRX0RNQQkJQklUKDE4KQ0KLSNkZWZpbmUgTVQ4MTczX1RPUF9BWElf UFJPVF9FTl9HQ1BVCQlCSVQoMTkpDQotI2RlZmluZSBNVDgxNzNfVE9QX0FYSV9QUk9UX0VOX0lP TU1VCQlCSVQoMjApDQotI2RlZmluZSBNVDgxNzNfVE9QX0FYSV9QUk9UX0VOX01GR19NMAkJQklU KDIxKQ0KLSNkZWZpbmUgTVQ4MTczX1RPUF9BWElfUFJPVF9FTl9NRkdfTTEJCUJJVCgyMikNCi0j ZGVmaW5lIE1UODE3M19UT1BfQVhJX1BST1RfRU5fTUZHX1NOT09QX09VVAlCSVQoMjMpDQotDQot I2RlZmluZSBNVDI3MDFfVE9QX0FYSV9QUk9UX0VOX01NX00wCQlCSVQoMSkNCi0jZGVmaW5lIE1U MjcwMV9UT1BfQVhJX1BST1RfRU5fQ09OTl9NCQlCSVQoMikNCi0jZGVmaW5lIE1UMjcwMV9UT1Bf QVhJX1BST1RfRU5fQ09OTl9TCQlCSVQoOCkNCi0NCi0jZGVmaW5lIE1UNzYyMl9UT1BfQVhJX1BS T1RfRU5fRVRIU1lTCQkoQklUKDMpIHwgQklUKDE3KSkNCi0jZGVmaW5lIE1UNzYyMl9UT1BfQVhJ X1BST1RfRU5fSElGMAkJKEJJVCgyNCkgfCBCSVQoMjUpKQ0KLSNkZWZpbmUgTVQ3NjIyX1RPUF9B WElfUFJPVF9FTl9ISUYxCQkoQklUKDI2KSB8IEJJVCgyNykgfCBcDQotCQkJCQkJIEJJVCgyOCkp DQotI2RlZmluZSBNVDc2MjJfVE9QX0FYSV9QUk9UX0VOX1dCCQkoQklUKDIpIHwgQklUKDYpIHwg XA0KLQkJCQkJCSBCSVQoNykgfCBCSVQoOCkpDQotDQotaW50IG10a19pbmZyYWNmZ19zZXRfYnVz X3Byb3RlY3Rpb24oc3RydWN0IHJlZ21hcCAqaW5mcmFjZmcsIHUzMiBtYXNrLA0KLQkJYm9vbCBy ZWdfdXBkYXRlKTsNCi1pbnQgbXRrX2luZnJhY2ZnX2NsZWFyX2J1c19wcm90ZWN0aW9uKHN0cnVj dCByZWdtYXAgKmluZnJhY2ZnLCB1MzIgbWFzaywNCi0JCWJvb2wgcmVnX3VwZGF0ZSk7DQotI2Vu ZGlmIC8qIF9fU09DX01FRElBVEVLX0lORlJBQ0ZHX0ggKi8NCi0tIA0KMS44LjEuMS5kaXJ0eQ0K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F191C43603 for ; Wed, 18 Dec 2019 08:41:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 05A9721D7D for ; Wed, 18 Dec 2019 08:41:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="H9+BOkfd"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="lq6UXcM3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 05A9721D7D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=QBKdsb61uIiQkCrQEyUvpQWR03EbH+F2Pfy2aD8SfjA=; b=H9+BOkfdVIo6ZH 9FMfMUZjVtJWswSpNcM/Q9TKy+DNy84DgXUc12vRKGX6rnzptr2mAjhbJ9Ig3JRabPBREuRa8DdmA MnBDi/Mt9f0w/rN5q/x/N9XpMJ8CVTXt8G7oNeK2U3R1D53oqllGaPJxFFG5cahDRy6H2WmGNS2xX Dv+Z+oZmltTy5Na/Kdjjuk+1DBHsD7zFEXhViMGqULKspFHwdIlQ3jAdcF4FNQ0GdvDmnF3URgH5y 3Q4wSuqBG8D9yizXFlytY/Jfa172TF0adiOkljoBAhCeR2iCbSJEEPyYgMsmk+S0yRBjUwtd2ytD0 RdH7esS9X4U6ecwsnnOw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1ihUu0-0004rJ-Th; Wed, 18 Dec 2019 08:41:52 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1ihUtF-0004DR-6L; Wed, 18 Dec 2019 08:41:06 +0000 X-UUID: 107b70b56a5841ffab198ae4e6dc767b-20191218 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=a5FCEy2BZm61QcAEPy9+kPZfwRGbVTTgU0WkpB3/H0E=; b=lq6UXcM3E29Sj4VNDoaapn85HP2B5047kCPd/KQGUErgb87X7kvomIQHEfwUwTI4rDHHyV9LLjs4X5YH3EygTXCZCum3kblqcPwz+ZhcgAEcE94SrwPbU/ECWqsDTic1FmINNQvYVsiLsqRFPuKiUNQYTMrmPWZg+r/61wJ3h/Q=; X-UUID: 107b70b56a5841ffab198ae4e6dc767b-20191218 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 106811220; Wed, 18 Dec 2019 00:41:00 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 18 Dec 2019 00:31:20 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 18 Dec 2019 16:30:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 18 Dec 2019 16:30:30 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Rob Herring , Sascha Hauer Subject: [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support Date: Wed, 18 Dec 2019 16:30:43 +0800 Message-ID: <1576657848-14711-8-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1576657848-14711-1-git-send-email-weiyi.lu@mediatek.com> References: <1576657848-14711-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191218_004105_235411_DF26B296 X-CRM114-Status: GOOD ( 13.66 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org In previous patches, we introduce scpsys-ext driver that covers the functions which infracfg misc driver provided. And then replace bus_prot_mask with bp_table of all compatibles. Now, we're going to remove infracfg misc drvier which is no longer being used. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/Kconfig | 10 ----- drivers/soc/mediatek/Makefile | 3 +- drivers/soc/mediatek/mtk-infracfg.c | 79 ----------------------------------- include/linux/soc/mediatek/infracfg.h | 39 ----------------- 4 files changed, 1 insertion(+), 130 deletions(-) delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c delete mode 100644 include/linux/soc/mediatek/infracfg.h diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 2114b56..f837b3c 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -10,21 +10,12 @@ config MTK_CMDQ depends on ARCH_MEDIATEK || COMPILE_TEST select MAILBOX select MTK_CMDQ_MBOX - select MTK_INFRACFG help Say yes here to add support for the MediaTek Command Queue (CMDQ) driver. The CMDQ is used to help read/write registers with critical time limitation, such as updating display configuration during the vblank. -config MTK_INFRACFG - bool "MediaTek INFRACFG Support" - select REGMAP - help - Say yes here to add support for the MediaTek INFRACFG controller. The - INFRACFG controller contains various infrastructure registers not - directly associated to any device. - config MTK_PMIC_WRAP tristate "MediaTek PMIC Wrapper Support" depends on RESET_CONTROLLER @@ -38,7 +29,6 @@ config MTK_SCPSYS bool "MediaTek SCPSYS Support" default ARCH_MEDIATEK select REGMAP - select MTK_INFRACFG select PM_GENERIC_DOMAINS if PM help Say yes here to add support for the MediaTek SCPSYS power domain diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index b442be9..7bf7e88 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o -obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o +obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o mtk-scpsys-ext.o diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c deleted file mode 100644 index 341c7ac..0000000 --- a/drivers/soc/mediatek/mtk-infracfg.c +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015 Pengutronix, Sascha Hauer - */ - -#include -#include -#include -#include -#include - -#define MTK_POLL_DELAY_US 10 -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ)) - -#define INFRA_TOPAXI_PROTECTEN 0x0220 -#define INFRA_TOPAXI_PROTECTSTA1 0x0228 -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 - -/** - * mtk_infracfg_set_bus_protection - enable bus protection - * @regmap: The infracfg regmap - * @mask: The mask containing the protection bits to be enabled. - * @reg_update: The boolean flag determines to set the protection bits - * by regmap_update_bits with enable register(PROTECTEN) or - * by regmap_write with set register(PROTECTEN_SET). - * - * This function enables the bus protection bits for disabled power - * domains so that the system does not hang when some unit accesses the - * bus while in power down. - */ -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update) -{ - u32 val; - int ret; - - if (reg_update) - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, - mask); - else - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); - - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, - val, (val & mask) == mask, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); - - return ret; -} - -/** - * mtk_infracfg_clear_bus_protection - disable bus protection - * @regmap: The infracfg regmap - * @mask: The mask containing the protection bits to be disabled. - * @reg_update: The boolean flag determines to clear the protection bits - * by regmap_update_bits with enable register(PROTECTEN) or - * by regmap_write with clear register(PROTECTEN_CLR). - * - * This function disables the bus protection bits previously enabled with - * mtk_infracfg_set_bus_protection. - */ - -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update) -{ - int ret; - u32 val; - - if (reg_update) - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); - else - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); - - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, - val, !(val & mask), - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); - - return ret; -} diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h deleted file mode 100644 index fd25f01..0000000 --- a/include/linux/soc/mediatek/infracfg.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __SOC_MEDIATEK_INFRACFG_H -#define __SOC_MEDIATEK_INFRACFG_H - -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6) -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9) -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11) -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12) -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13) -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15) -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16) -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17) -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18) -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19) -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20) -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) - -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) - -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ - BIT(28)) -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ - BIT(7) | BIT(8)) - -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update); -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update); -#endif /* __SOC_MEDIATEK_INFRACFG_H */ -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90C86C43603 for ; Wed, 18 Dec 2019 08:42:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 38D0321D7D for ; Wed, 18 Dec 2019 08:42:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="AoxkQ/7a"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="lq6UXcM3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 38D0321D7D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+KlIXhpcMpfQnY1zFkRMkTbzOLaxd37q0wsYKCAdzhc=; b=AoxkQ/7aJeMUvK q0hMj84kPgJv6A+a7kcUiVOg70h9WqqZaZvgUhyITSQARd0lrn+HB6jE3E/X/ma8SZpZhhjI8b8v9 H0pHPfcBbeVhYqME2yagkPkrRBHt9M8Bb+ts9BFb7oYRH58oSPe/YKvhb2nkJI1tf61SDKhwmVbuU KkK0qmRTQTDnOnTt5dyKJvn/Qs2wR9ZfFsUturqESK1ibvbYvCB++cAAajqG1LJNgDxjdxiWYlifH PNCPNisWgsTUURW1e7aQjdEaiaoATIos/b3Sro7TXzb2WXrKo6Z80TZdY7l4fAnYGR4UoIabOPLtm xIflnm9mpmoyn9xkMWTQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1ihUu9-0004xc-0h; Wed, 18 Dec 2019 08:42:01 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1ihUtF-0004DR-6L; Wed, 18 Dec 2019 08:41:06 +0000 X-UUID: 107b70b56a5841ffab198ae4e6dc767b-20191218 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=a5FCEy2BZm61QcAEPy9+kPZfwRGbVTTgU0WkpB3/H0E=; b=lq6UXcM3E29Sj4VNDoaapn85HP2B5047kCPd/KQGUErgb87X7kvomIQHEfwUwTI4rDHHyV9LLjs4X5YH3EygTXCZCum3kblqcPwz+ZhcgAEcE94SrwPbU/ECWqsDTic1FmINNQvYVsiLsqRFPuKiUNQYTMrmPWZg+r/61wJ3h/Q=; X-UUID: 107b70b56a5841ffab198ae4e6dc767b-20191218 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 106811220; Wed, 18 Dec 2019 00:41:00 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 18 Dec 2019 00:31:20 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 18 Dec 2019 16:30:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 18 Dec 2019 16:30:30 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Rob Herring , Sascha Hauer Subject: [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support Date: Wed, 18 Dec 2019 16:30:43 +0800 Message-ID: <1576657848-14711-8-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1576657848-14711-1-git-send-email-weiyi.lu@mediatek.com> References: <1576657848-14711-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191218_004105_235411_DF26B296 X-CRM114-Status: GOOD ( 13.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org In previous patches, we introduce scpsys-ext driver that covers the functions which infracfg misc driver provided. And then replace bus_prot_mask with bp_table of all compatibles. Now, we're going to remove infracfg misc drvier which is no longer being used. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/Kconfig | 10 ----- drivers/soc/mediatek/Makefile | 3 +- drivers/soc/mediatek/mtk-infracfg.c | 79 ----------------------------------- include/linux/soc/mediatek/infracfg.h | 39 ----------------- 4 files changed, 1 insertion(+), 130 deletions(-) delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c delete mode 100644 include/linux/soc/mediatek/infracfg.h diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 2114b56..f837b3c 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -10,21 +10,12 @@ config MTK_CMDQ depends on ARCH_MEDIATEK || COMPILE_TEST select MAILBOX select MTK_CMDQ_MBOX - select MTK_INFRACFG help Say yes here to add support for the MediaTek Command Queue (CMDQ) driver. The CMDQ is used to help read/write registers with critical time limitation, such as updating display configuration during the vblank. -config MTK_INFRACFG - bool "MediaTek INFRACFG Support" - select REGMAP - help - Say yes here to add support for the MediaTek INFRACFG controller. The - INFRACFG controller contains various infrastructure registers not - directly associated to any device. - config MTK_PMIC_WRAP tristate "MediaTek PMIC Wrapper Support" depends on RESET_CONTROLLER @@ -38,7 +29,6 @@ config MTK_SCPSYS bool "MediaTek SCPSYS Support" default ARCH_MEDIATEK select REGMAP - select MTK_INFRACFG select PM_GENERIC_DOMAINS if PM help Say yes here to add support for the MediaTek SCPSYS power domain diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index b442be9..7bf7e88 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o -obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o +obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o mtk-scpsys-ext.o diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c deleted file mode 100644 index 341c7ac..0000000 --- a/drivers/soc/mediatek/mtk-infracfg.c +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015 Pengutronix, Sascha Hauer - */ - -#include -#include -#include -#include -#include - -#define MTK_POLL_DELAY_US 10 -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ)) - -#define INFRA_TOPAXI_PROTECTEN 0x0220 -#define INFRA_TOPAXI_PROTECTSTA1 0x0228 -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 - -/** - * mtk_infracfg_set_bus_protection - enable bus protection - * @regmap: The infracfg regmap - * @mask: The mask containing the protection bits to be enabled. - * @reg_update: The boolean flag determines to set the protection bits - * by regmap_update_bits with enable register(PROTECTEN) or - * by regmap_write with set register(PROTECTEN_SET). - * - * This function enables the bus protection bits for disabled power - * domains so that the system does not hang when some unit accesses the - * bus while in power down. - */ -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update) -{ - u32 val; - int ret; - - if (reg_update) - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, - mask); - else - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); - - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, - val, (val & mask) == mask, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); - - return ret; -} - -/** - * mtk_infracfg_clear_bus_protection - disable bus protection - * @regmap: The infracfg regmap - * @mask: The mask containing the protection bits to be disabled. - * @reg_update: The boolean flag determines to clear the protection bits - * by regmap_update_bits with enable register(PROTECTEN) or - * by regmap_write with clear register(PROTECTEN_CLR). - * - * This function disables the bus protection bits previously enabled with - * mtk_infracfg_set_bus_protection. - */ - -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update) -{ - int ret; - u32 val; - - if (reg_update) - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); - else - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); - - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, - val, !(val & mask), - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); - - return ret; -} diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h deleted file mode 100644 index fd25f01..0000000 --- a/include/linux/soc/mediatek/infracfg.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __SOC_MEDIATEK_INFRACFG_H -#define __SOC_MEDIATEK_INFRACFG_H - -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6) -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9) -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11) -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12) -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13) -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15) -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16) -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17) -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18) -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19) -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20) -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) - -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) - -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ - BIT(28)) -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ - BIT(7) | BIT(8)) - -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update); -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update); -#endif /* __SOC_MEDIATEK_INFRACFG_H */ -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel