From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sowjanya Komatineni Subject: [PATCH v5 01/19] dt-bindings: clock: tegra: Change CLK_M_DIV to OSC_DIV clocks Date: Fri, 20 Dec 2019 14:26:47 -0800 Message-ID: <1576880825-15010-2-git-send-email-skomatineni@nvidia.com> References: <1576880825-15010-1-git-send-email-skomatineni@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1576880825-15010-1-git-send-email-skomatineni@nvidia.com> Sender: linux-kernel-owner@vger.kernel.org To: skomatineni@nvidia.com, thierry.reding@gmail.com, jonathanh@nvidia.com, broonie@kernel.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, digetx@gmail.com, mperttunen@nvidia.com, gregkh@linuxfoundation.org, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, spujar@nvidia.com, josephl@nvidia.com, daniel.lezcano@linaro.org, mmaddireddy@nvidia.com, markz@nvidia.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-tegra@vger.kernel.org Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks and instead it has OSC_DIV2 and OSC_DIV4 clocks from OSC pads. This patch changes CLK_M_DIV2 and CLK_M_DIV4 clock ids to OSC_DIV2 and OSC_DIV4 clock ids for Tegra30 through Tegra210. Acked-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/clock/tegra114-car.h | 4 ++-- include/dt-bindings/clock/tegra124-car-common.h | 4 ++-- include/dt-bindings/clock/tegra210-car.h | 4 ++-- include/dt-bindings/clock/tegra30-car.h | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index bb5c2c999c05..f4880959b094 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h @@ -226,8 +226,8 @@ #define TEGRA114_CLK_FUSE_BURN 199 #define TEGRA114_CLK_CLK_32K 200 #define TEGRA114_CLK_CLK_M 201 -#define TEGRA114_CLK_CLK_M_DIV2 202 -#define TEGRA114_CLK_CLK_M_DIV4 203 +#define TEGRA114_CLK_OSC_DIV2 202 +#define TEGRA114_CLK_OSC_DIV4 203 #define TEGRA114_CLK_PLL_REF 204 #define TEGRA114_CLK_PLL_C 205 #define TEGRA114_CLK_PLL_C_OUT1 206 diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h index 0c4f5be0a742..e7e601a88d3d 100644 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -225,8 +225,8 @@ #define TEGRA124_CLK_FUSE_BURN 199 #define TEGRA124_CLK_CLK_32K 200 #define TEGRA124_CLK_CLK_M 201 -#define TEGRA124_CLK_CLK_M_DIV2 202 -#define TEGRA124_CLK_CLK_M_DIV4 203 +#define TEGRA124_CLK_OSC_DIV2 202 +#define TEGRA124_CLK_OSC_DIV4 203 #define TEGRA124_CLK_PLL_REF 204 #define TEGRA124_CLK_PLL_C 205 #define TEGRA124_CLK_PLL_C_OUT1 206 diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 44f60623f99b..6f65c14bf013 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -260,8 +260,8 @@ #define TEGRA210_CLK_FUSE_BURN 231 #define TEGRA210_CLK_CLK_32K 232 #define TEGRA210_CLK_CLK_M 233 -#define TEGRA210_CLK_CLK_M_DIV2 234 -#define TEGRA210_CLK_CLK_M_DIV4 235 +#define TEGRA210_CLK_OSC_DIV2 234 +#define TEGRA210_CLK_OSC_DIV4 235 #define TEGRA210_CLK_PLL_REF 236 #define TEGRA210_CLK_PLL_C 237 #define TEGRA210_CLK_PLL_C_OUT1 238 diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h index 3c90f1535551..907a8a04c280 100644 --- a/include/dt-bindings/clock/tegra30-car.h +++ b/include/dt-bindings/clock/tegra30-car.h @@ -194,8 +194,8 @@ #define TEGRA30_CLK_TVO 169 #define TEGRA30_CLK_CLK_32K 170 #define TEGRA30_CLK_CLK_M 171 -#define TEGRA30_CLK_CLK_M_DIV2 172 -#define TEGRA30_CLK_CLK_M_DIV4 173 +#define TEGRA30_CLK_OSC_DIV2 172 +#define TEGRA30_CLK_OSC_DIV4 173 #define TEGRA30_CLK_PLL_REF 174 #define TEGRA30_CLK_PLL_C 175 #define TEGRA30_CLK_PLL_C_OUT1 176 -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1D25C2D0D2 for ; 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by hqpgpgate101.nvidia.com on Fri, 20 Dec 2019 14:27:11 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 20 Dec 2019 22:27:10 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 20 Dec 2019 22:27:10 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.169.197]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 20 Dec 2019 14:27:10 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v5 01/19] dt-bindings: clock: tegra: Change CLK_M_DIV to OSC_DIV clocks Date: Fri, 20 Dec 2019 14:26:47 -0800 Message-ID: <1576880825-15010-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576880825-15010-1-git-send-email-skomatineni@nvidia.com> References: <1576880825-15010-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1576880800; bh=tTwiFKJGD2fvNPpDQ2HGSrTalMLKBHc/83/PBOLVEn0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=rGX7HkXX+eMC5S4hzgt9f5vc6hgO0C20AyePAX7m3kpBRmpWGkYh4A/JXJMmlwJD1 2Jw4dpsBWu3csBitXNNt6Y0y7SR3uDfw8GOX4vcWi4VTKwMs4eJitiLbC7qsT2FQNC rHgSCT42jK9fKs997ykVIEsqVsL7tneXh+hqKjh/aRbIsnntQs9GWRtcsNB+22GA+M DdJOqzbDe+aBQMGx6BcyRink7QQ4DC5nedhyldBOfrAJ9rwb6D8WldpGkXdeBtCjdV k49OEbHrad1AazCC/sHlTJKWq905pLHcDW6WmyfU+h/5cRpx6eXLvuW/NFhhgyfYHc 99BA/JHCa3AlQ== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks and instead it has OSC_DIV2 and OSC_DIV4 clocks from OSC pads. This patch changes CLK_M_DIV2 and CLK_M_DIV4 clock ids to OSC_DIV2 and OSC_DIV4 clock ids for Tegra30 through Tegra210. Acked-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/clock/tegra114-car.h | 4 ++-- include/dt-bindings/clock/tegra124-car-common.h | 4 ++-- include/dt-bindings/clock/tegra210-car.h | 4 ++-- include/dt-bindings/clock/tegra30-car.h | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index bb5c2c999c05..f4880959b094 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h @@ -226,8 +226,8 @@ #define TEGRA114_CLK_FUSE_BURN 199 #define TEGRA114_CLK_CLK_32K 200 #define TEGRA114_CLK_CLK_M 201 -#define TEGRA114_CLK_CLK_M_DIV2 202 -#define TEGRA114_CLK_CLK_M_DIV4 203 +#define TEGRA114_CLK_OSC_DIV2 202 +#define TEGRA114_CLK_OSC_DIV4 203 #define TEGRA114_CLK_PLL_REF 204 #define TEGRA114_CLK_PLL_C 205 #define TEGRA114_CLK_PLL_C_OUT1 206 diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h index 0c4f5be0a742..e7e601a88d3d 100644 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -225,8 +225,8 @@ #define TEGRA124_CLK_FUSE_BURN 199 #define TEGRA124_CLK_CLK_32K 200 #define TEGRA124_CLK_CLK_M 201 -#define TEGRA124_CLK_CLK_M_DIV2 202 -#define TEGRA124_CLK_CLK_M_DIV4 203 +#define TEGRA124_CLK_OSC_DIV2 202 +#define TEGRA124_CLK_OSC_DIV4 203 #define TEGRA124_CLK_PLL_REF 204 #define TEGRA124_CLK_PLL_C 205 #define TEGRA124_CLK_PLL_C_OUT1 206 diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 44f60623f99b..6f65c14bf013 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -260,8 +260,8 @@ #define TEGRA210_CLK_FUSE_BURN 231 #define TEGRA210_CLK_CLK_32K 232 #define TEGRA210_CLK_CLK_M 233 -#define TEGRA210_CLK_CLK_M_DIV2 234 -#define TEGRA210_CLK_CLK_M_DIV4 235 +#define TEGRA210_CLK_OSC_DIV2 234 +#define TEGRA210_CLK_OSC_DIV4 235 #define TEGRA210_CLK_PLL_REF 236 #define TEGRA210_CLK_PLL_C 237 #define TEGRA210_CLK_PLL_C_OUT1 238 diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h index 3c90f1535551..907a8a04c280 100644 --- a/include/dt-bindings/clock/tegra30-car.h +++ b/include/dt-bindings/clock/tegra30-car.h @@ -194,8 +194,8 @@ #define TEGRA30_CLK_TVO 169 #define TEGRA30_CLK_CLK_32K 170 #define TEGRA30_CLK_CLK_M 171 -#define TEGRA30_CLK_CLK_M_DIV2 172 -#define TEGRA30_CLK_CLK_M_DIV4 173 +#define TEGRA30_CLK_OSC_DIV2 172 +#define TEGRA30_CLK_OSC_DIV4 173 #define TEGRA30_CLK_PLL_REF 174 #define TEGRA30_CLK_PLL_C 175 #define TEGRA30_CLK_PLL_C_OUT1 176 -- 2.7.4