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From: Chris Wilson <chris@chris-wilson.co.uk>
To: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 5/5] drm/i915/gt: Split logical ring context manipulation into intel_lrc.c
Date: Tue, 28 Jan 2020 22:08:36 +0000	[thread overview]
Message-ID: <158024931625.7621.2130972792240757300@skylake-alporthouse-com> (raw)
In-Reply-To: <0f1a8ffd-e146-95a5-0c65-c48d77bc12ef@intel.com>

Quoting Daniele Ceraolo Spurio (2020-01-28 21:55:02)
> 
> 
> On 1/28/20 12:43 PM, Chris Wilson wrote:
> > Extract the core functions for setting up the machine dependent logical
> > ring context to intel_lrc.c. This will be shared by all submission
> > backends that utilise logical ring contexts.
> > 
> 
> I still don't understand why you don't want to put the lrc and ring 
> object creation and initial setup (populate_lr_context) somewhere 

The initial setup is common in intel_lrc.c, the rest is really just
mapping the local context layout, which will vary depending on the
different abstractions for the backends.

> common. I see no way we could do that differently for GuC submission, 
> since the HW obviously requires the same objects and IMO it makes sense 
> to keep the same initialization flow, so we'd have to copy that logic 
> and maintain 2 identical copies of it. The redzone is the only thing 
> that is not hw-enforced, but I believe it makes sense to keep that on 
> the GuC side as well to catch possible issues. Or am I missing something?

They don't have the same execution flow, and I expect the differences in
context bookkeeping will continue to grow. Certainly there's an
abstraction around virtual engines to come, because the current struct
is heavily tied into the backend.

populate_lr_context is one that might be shared, but I just didn't see
much point in sharing a couple of very minor routines, when the
common mechanism is available. I'm still waiting for the other shoe to
fall and wide-contexts to become a necessity again.
-Chris
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  reply	other threads:[~2020-01-28 22:08 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-28 20:43 [Intel-gfx] [PATCH 1/5] drm/i915/execlist: Mark up racy read of execlists->pending[0] Chris Wilson
2020-01-28 20:43 ` [Intel-gfx] [PATCH 2/5] drm/i915/gt: Hook up CS_MASTER_ERROR_INTERRUPT Chris Wilson
2020-01-28 20:43 ` [Intel-gfx] [PATCH 3/5] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore Chris Wilson
2020-01-28 20:43 ` [Intel-gfx] [PATCH 4/5] drm/i915/gt: Rename lrc.c to execlists_submission.c Chris Wilson
2020-01-28 21:37   ` Daniele Ceraolo Spurio
2020-01-28 20:43 ` [Intel-gfx] [PATCH 5/5] drm/i915/gt: Split logical ring context manipulation into intel_lrc.c Chris Wilson
2020-01-28 21:55   ` Daniele Ceraolo Spurio
2020-01-28 22:08     ` Chris Wilson [this message]
2020-01-28 22:44       ` Daniele Ceraolo Spurio
2020-01-28 23:50   ` Daniele Ceraolo Spurio
2020-01-29  2:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915/execlist: Mark up racy read of execlists->pending[0] Patchwork
2020-01-29  2:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-29 13:11 ` [Intel-gfx] [PATCH 1/5] " Mika Kuoppala
2020-01-31  2:30 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] " Patchwork

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