[Intel-gfx] [PATCH v2] drm/i915/selftests/perf: measure memcpy bw between regions

[Intel-gfx] [PATCH v2] drm/i915/selftests/perf: measure memcpy bw between regions

[Matthew Auld]

Measure the memcpy bw between our CPU accessible regions, trying all
supported mapping combinations(WC, WB) across various sizes.

v2:
    use smaller sizes
    throw in memcpy32/memcpy64/memcpy_from_wc

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 .../drm/i915/selftests/i915_perf_selftests.h  |   1 +
 .../drm/i915/selftests/intel_memory_region.c  | 218 ++++++++++++++++++
 2 files changed, 219 insertions(+)

diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index 5a577a1332f5..3bf7f53e9924 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -17,3 +17,4 @@
  */
 selftest(engine_cs, intel_engine_cs_perf_selftests)
 selftest(blt, i915_gem_object_blt_perf_selftests)
+selftest(region, intel_memory_region_perf_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 3ef3620e0da5..2ae9e9a22ce2 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -4,6 +4,7 @@
  */
 
 #include <linux/prime_numbers.h>
+#include <linux/sort.h>
 
 #include "../i915_selftest.h"
 
@@ -19,6 +20,7 @@
 #include "gem/selftests/mock_context.h"
 #include "gt/intel_engine_user.h"
 #include "gt/intel_gt.h"
+#include "i915_memcpy.h"
 #include "selftests/igt_flush_test.h"
 #include "selftests/i915_random.h"
 
@@ -572,6 +574,210 @@ static int igt_lmem_write_cpu(void *arg)
 	return err;
 }
 
+static const char *repr_type(u32 type)
+{
+	switch (type) {
+	case I915_MAP_WB:
+		return "WB";
+	case I915_MAP_WC:
+		return "WC";
+	}
+
+	return "";
+}
+
+static struct drm_i915_gem_object *
+create_region_for_mapping(struct intel_memory_region *mr, u64 size, u32 type,
+			  void **out_addr)
+{
+	struct drm_i915_gem_object *obj;
+	void *addr;
+
+	obj = i915_gem_object_create_region(mr, size, 0);
+	if (IS_ERR(obj))
+		return obj;
+
+	addr = i915_gem_object_pin_map(obj, type);
+	if (IS_ERR(addr)) {
+		i915_gem_object_put(obj);
+		if (PTR_ERR(addr) == -ENXIO)
+			return ERR_PTR(-ENODEV);
+		return addr;
+	}
+
+	*out_addr = addr;
+	return obj;
+}
+
+static int wrap_ktime_compare(const void *A, const void *B)
+{
+	const ktime_t *a = A, *b = B;
+
+	return ktime_compare(*a, *b);
+}
+
+static void igt_memcpy32(void *dst, const void *src, size_t size)
+{
+	u32 *tmp = dst;
+	const u32 *s = src;
+
+	size = size / sizeof(u32);
+	while (size--)
+		*tmp++ = *s++;
+}
+
+static void igt_memcpy64(void *dst, const void *src, size_t size)
+{
+	u64 *tmp = dst;
+	const u64 *s = src;
+
+	size = size / sizeof(u64);
+	while (size--)
+		*tmp++ = *s++;
+}
+
+static inline void igt_memcpy(void *dst, const void *src, size_t size)
+{
+	memcpy(dst, src, size);
+}
+
+static inline void igt_memcpy_from_wc(void *dst, const void *src, size_t size)
+{
+	i915_memcpy_from_wc(dst, src, size);
+}
+
+static int _perf_memcpy(struct intel_memory_region *src_mr,
+			struct intel_memory_region *dst_mr,
+			u64 size, u32 src_type, u32 dst_type)
+{
+	const struct {
+		const char *name;
+		void (*copy)(void *dst, const void *src, size_t size);
+		bool skip;
+	} tests[] = {
+		{
+			"memcpy32",
+			igt_memcpy32,
+		},
+		{
+			"memcpy64",
+			igt_memcpy64,
+		},
+		{
+			"memcpy",
+			igt_memcpy,
+		},
+		{
+			"memcpy_from_wc",
+			igt_memcpy_from_wc,
+			src_type != I915_MAP_WC || !i915_has_memcpy_from_wc(),
+		},
+	};
+	struct drm_i915_gem_object *src, *dst;
+	void *src_addr, *dst_addr;
+	int ret = 0;
+	int i;
+
+	src = create_region_for_mapping(src_mr, size, src_type, &src_addr);
+	if (IS_ERR(src)) {
+		ret = PTR_ERR(src);
+		goto out;
+	}
+
+	dst = create_region_for_mapping(dst_mr, size, dst_type, &dst_addr);
+	if (IS_ERR(dst)) {
+		ret = PTR_ERR(dst);
+		goto out_unpin_src;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(tests); ++i) {
+		ktime_t t[5];
+		int pass;
+
+		if (tests[i].skip)
+			continue;
+
+		for (pass = 0; pass < ARRAY_SIZE(t); pass++) {
+			ktime_t t0, t1;
+
+			t0 = ktime_get();
+
+			tests[i].copy(dst_addr, src_addr, size);
+
+			t1 = ktime_get();
+			t[pass] = ktime_sub(t1, t0);
+		}
+
+		sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
+		pr_info("%s src(%s, %s) -> dst(%s, %s) %s %llu KiB copy: %lld MiB/s\n",
+			__func__,
+			src_mr->name,
+			repr_type(src_type),
+			dst_mr->name,
+			repr_type(dst_type),
+			tests[i].name,
+			size >> 10,
+			div64_u64(mul_u32_u32(4 * size,
+					      1000 * 1000 * 1000),
+				  t[1] + 2 * t[2] + t[3]) >> 20);
+
+		cond_resched();
+	}
+
+	i915_gem_object_unpin_map(dst);
+	__i915_gem_object_put_pages(dst);
+
+	i915_gem_object_put(dst);
+out_unpin_src:
+	i915_gem_object_unpin_map(src);
+	__i915_gem_object_put_pages(src);
+
+	i915_gem_object_put(src);
+out:
+	if (ret == -ENODEV)
+		ret = 0;
+
+	return ret;
+}
+
+static int perf_memcpy(void *arg)
+{
+	struct drm_i915_private *i915 = arg;
+	static const u32 types[] = {
+		I915_MAP_WB,
+		I915_MAP_WC,
+	};
+	static const u32 sizes[] = {
+		SZ_4K,
+		SZ_64K,
+		SZ_4M,
+	};
+	struct intel_memory_region *src_mr, *dst_mr;
+	int src_id, dst_id;
+	int i, j, k;
+	int ret;
+
+	for_each_memory_region(src_mr, i915, src_id) {
+		for_each_memory_region(dst_mr, i915, dst_id) {
+			for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
+				for (j = 0; j < ARRAY_SIZE(types); ++j) {
+					for (k = 0; k < ARRAY_SIZE(types); ++k) {
+						ret = _perf_memcpy(src_mr,
+								   dst_mr,
+								   sizes[i],
+								   types[j],
+								   types[k]);
+						if (ret)
+							return ret;
+					}
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
 int intel_memory_region_mock_selftests(void)
 {
 	static const struct i915_subtest tests[] = {
@@ -619,3 +825,15 @@ int intel_memory_region_live_selftests(struct drm_i915_private *i915)
 
 	return i915_live_subtests(tests, i915);
 }
+
+int intel_memory_region_perf_selftests(struct drm_i915_private *i915)
+{
+	static const struct i915_subtest tests[] = {
+		SUBTEST(perf_memcpy),
+	};
+
+	if (intel_gt_is_wedged(&i915->gt))
+		return 0;
+
+	return i915_live_subtests(tests, i915);
+}
-- 
2.20.1

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Re: [Intel-gfx] [PATCH v2] drm/i915/selftests/perf: measure memcpy bw between regions

[Chris Wilson]

Quoting Matthew Auld (2020-01-28 18:38:06)
> Measure the memcpy bw between our CPU accessible regions, trying all
> supported mapping combinations(WC, WB) across various sizes.
> 
> v2:
>     use smaller sizes
>     throw in memcpy32/memcpy64/memcpy_from_wc
> 
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  .../drm/i915/selftests/i915_perf_selftests.h  |   1 +
>  .../drm/i915/selftests/intel_memory_region.c  | 218 ++++++++++++++++++
>  2 files changed, 219 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
> index 5a577a1332f5..3bf7f53e9924 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
> +++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
> @@ -17,3 +17,4 @@
>   */
>  selftest(engine_cs, intel_engine_cs_perf_selftests)
>  selftest(blt, i915_gem_object_blt_perf_selftests)
> +selftest(region, intel_memory_region_perf_selftests)
> diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> index 3ef3620e0da5..2ae9e9a22ce2 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> @@ -4,6 +4,7 @@
>   */
>  
>  #include <linux/prime_numbers.h>
> +#include <linux/sort.h>
>  
>  #include "../i915_selftest.h"
>  
> @@ -19,6 +20,7 @@
>  #include "gem/selftests/mock_context.h"
>  #include "gt/intel_engine_user.h"
>  #include "gt/intel_gt.h"
> +#include "i915_memcpy.h"
>  #include "selftests/igt_flush_test.h"
>  #include "selftests/i915_random.h"
>  
> @@ -572,6 +574,210 @@ static int igt_lmem_write_cpu(void *arg)
>         return err;
>  }
>  
> +static const char *repr_type(u32 type)
> +{
> +       switch (type) {
> +       case I915_MAP_WB:
> +               return "WB";
> +       case I915_MAP_WC:
> +               return "WC";
> +       }
> +
> +       return "";
> +}
> +
> +static struct drm_i915_gem_object *
> +create_region_for_mapping(struct intel_memory_region *mr, u64 size, u32 type,
> +                         void **out_addr)
> +{
> +       struct drm_i915_gem_object *obj;
> +       void *addr;
> +
> +       obj = i915_gem_object_create_region(mr, size, 0);
> +       if (IS_ERR(obj))
> +               return obj;
> +
> +       addr = i915_gem_object_pin_map(obj, type);
> +       if (IS_ERR(addr)) {
> +               i915_gem_object_put(obj);
> +               if (PTR_ERR(addr) == -ENXIO)
> +                       return ERR_PTR(-ENODEV);
> +               return addr;
> +       }
> +
> +       *out_addr = addr;
> +       return obj;
> +}
> +
> +static int wrap_ktime_compare(const void *A, const void *B)
> +{
> +       const ktime_t *a = A, *b = B;
> +
> +       return ktime_compare(*a, *b);
> +}
> +
> +static void igt_memcpy32(void *dst, const void *src, size_t size)
> +{
> +       u32 *tmp = dst;
> +       const u32 *s = src;
> +
> +       size = size / sizeof(u32);
> +       while (size--)
> +               *tmp++ = *s++;
> +}
> +
> +static void igt_memcpy64(void *dst, const void *src, size_t size)
> +{
> +       u64 *tmp = dst;
> +       const u64 *s = src;
> +
> +       size = size / sizeof(u64);
> +       while (size--)
> +               *tmp++ = *s++;

memcpy64 will do. I was mainly worrying about the effect of reps being
always on WC memory. So potentially bad memcpy, mediocre memcpy64 and
memcpy_from_wc should cover the possibilities.

Hmm. How about memcpy_long instead (that should give us x32/x64
agnosticism).

> +}
> +
> +static inline void igt_memcpy(void *dst, const void *src, size_t size)
> +{
> +       memcpy(dst, src, size);
> +}
> +
> +static inline void igt_memcpy_from_wc(void *dst, const void *src, size_t size)
> +{
> +       i915_memcpy_from_wc(dst, src, size);
> +}
> +
> +static int _perf_memcpy(struct intel_memory_region *src_mr,
> +                       struct intel_memory_region *dst_mr,
> +                       u64 size, u32 src_type, u32 dst_type)
> +{
> +       const struct {
> +               const char *name;
> +               void (*copy)(void *dst, const void *src, size_t size);
> +               bool skip;
> +       } tests[] = {
> +               {
> +                       "memcpy32",
> +                       igt_memcpy32,
> +               },
> +               {
> +                       "memcpy64",
> +                       igt_memcpy64,
> +               },
> +               {
> +                       "memcpy",
> +                       igt_memcpy,
> +               },
> +               {
> +                       "memcpy_from_wc",
> +                       igt_memcpy_from_wc,
> +                       src_type != I915_MAP_WC || !i915_has_memcpy_from_wc(),

Should be safe for any source mapping (at least according to
experiments), so just !i915_has_memcpy_from_wc.

> +               },
> +       };
> +       struct drm_i915_gem_object *src, *dst;
> +       void *src_addr, *dst_addr;
> +       int ret = 0;
> +       int i;
> +
> +       src = create_region_for_mapping(src_mr, size, src_type, &src_addr);
> +       if (IS_ERR(src)) {
> +               ret = PTR_ERR(src);
> +               goto out;
> +       }
> +
> +       dst = create_region_for_mapping(dst_mr, size, dst_type, &dst_addr);
> +       if (IS_ERR(dst)) {
> +               ret = PTR_ERR(dst);
> +               goto out_unpin_src;
> +       }
> +
> +       for (i = 0; i < ARRAY_SIZE(tests); ++i) {
> +               ktime_t t[5];
> +               int pass;
> +
> +               if (tests[i].skip)
> +                       continue;
> +
> +               for (pass = 0; pass < ARRAY_SIZE(t); pass++) {
> +                       ktime_t t0, t1;
> +
> +                       t0 = ktime_get();
> +
> +                       tests[i].copy(dst_addr, src_addr, size);
> +
> +                       t1 = ktime_get();
> +                       t[pass] = ktime_sub(t1, t0);
> +               }
> +
> +               sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
> +               pr_info("%s src(%s, %s) -> dst(%s, %s) %s %llu KiB copy: %lld MiB/s\n",
> +                       __func__,
> +                       src_mr->name,
> +                       repr_type(src_type),
> +                       dst_mr->name,
> +                       repr_type(dst_type),
> +                       tests[i].name,
> +                       size >> 10,
> +                       div64_u64(mul_u32_u32(4 * size,
> +                                             1000 * 1000 * 1000),
> +                                 t[1] + 2 * t[2] + t[3]) >> 20);

Should this be >> 22 ? (20 /* to MiB */ + 2 /* for avergage */)

> +
> +               cond_resched();
> +       }
> +
> +       i915_gem_object_unpin_map(dst);
> +       __i915_gem_object_put_pages(dst);

put_pages() to speed up the reaping?

How about skipping that leaving it to the ordinary free to cleanup, and
flushing the free?

	object_unpin_map(dst);
	object_put(dst);

	object_unpin_map(src);
	object_put(src);

	i915_gem_drain_freed_objects();

> +
> +       i915_gem_object_put(dst);
> +out_unpin_src:
> +       i915_gem_object_unpin_map(src);
> +       __i915_gem_object_put_pages(src);
> +
> +       i915_gem_object_put(src);
> +out:
> +       if (ret == -ENODEV)
> +               ret = 0;
> +
> +       return ret;
> +}
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915/selftests/perf: measure memcpy bw between regions

[Chris Wilson]

Quoting Chris Wilson (2020-01-28 18:54:18)
> Quoting Matthew Auld (2020-01-28 18:38:06)
> > +               sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
> > +               pr_info("%s src(%s, %s) -> dst(%s, %s) %s %llu KiB copy: %lld MiB/s\n",
> > +                       __func__,
> > +                       src_mr->name,
> > +                       repr_type(src_type),
> > +                       dst_mr->name,
> > +                       repr_type(dst_type),
> > +                       tests[i].name,
> > +                       size >> 10,
> > +                       div64_u64(mul_u32_u32(4 * size,
> > +                                             1000 * 1000 * 1000),
> > +                                 t[1] + 2 * t[2] + t[3]) >> 20);
> 
> Should this be >> 22 ? (20 /* to MiB */ + 2 /* for avergage */)

Ah, 4*size.
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915/selftests/perf: measure memcpy bw between regions

[Chris Wilson]

Quoting Matthew Auld (2020-01-28 18:38:06)
> +               sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
> +               pr_info("%s src(%s, %s) -> dst(%s, %s) %s %llu KiB copy: %lld MiB/s\n",

pr_info("%s src(%s, %s) -> dst(%s, %s) %14s %4llu KiB copy: %5lld MiB/s\n",

should make it line up and be a little less disorganised.

Exporting the results in a more convenient format than dmesg is a
problem to be solved at a later date.
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests/perf: measure memcpy bw between regions (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/selftests/perf: measure memcpy bw between regions (rev2)
URL   : https://patchwork.freedesktop.org/series/72621/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d20c84c0e130 drm/i915/selftests/perf: measure memcpy bw between regions
-:242: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring
#242: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:770:
+						if (ret)

total: 0 errors, 1 warnings, 0 checks, 243 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests/perf: measure memcpy bw between regions (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/selftests/perf: measure memcpy bw between regions (rev2)
URL   : https://patchwork.freedesktop.org/series/72621/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7833 -> Patchwork_16306
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16306/index.html

Known issues
------------

  Here are the changes found in Patchwork_16306 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_parallel@fds:
    - fi-byt-n2820:       [PASS][1] -> [TIMEOUT][2] ([fdo#112271])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7833/fi-byt-n2820/igt@gem_exec_parallel@fds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16306/fi-byt-n2820/igt@gem_exec_parallel@fds.html

  
#### Possible fixes ####

  * igt@gem_close_race@basic-threads:
    - fi-hsw-peppy:       [INCOMPLETE][3] ([i915#816]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7833/fi-hsw-peppy/igt@gem_close_race@basic-threads.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16306/fi-hsw-peppy/igt@gem_close_race@basic-threads.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-icl-u2:          [FAIL][5] ([fdo#103375]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7833/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16306/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-icl-u2:          [FAIL][7] ([fdo#111550]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7833/fi-icl-u2/igt@gem_exec_suspend@basic-s4-devices.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16306/fi-icl-u2/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770r:       [DMESG-FAIL][9] ([i915#563]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7833/fi-hsw-4770r/igt@i915_selftest@live_blt.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16306/fi-hsw-4770r/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-icl-guc:         [INCOMPLETE][11] ([i915#140]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7833/fi-icl-guc/igt@i915_selftest@live_gem_contexts.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16306/fi-icl-guc/igt@i915_selftest@live_gem_contexts.html

  
#### Warnings ####

  * igt@gem_exec_parallel@contexts:
    - fi-byt-n2820:       [TIMEOUT][13] ([fdo#112271]) -> [FAIL][14] ([i915#694])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7833/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16306/fi-byt-n2820/igt@gem_exec_parallel@contexts.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-guc:         [FAIL][15] ([i915#579]) -> [SKIP][16] ([fdo#109271])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7833/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16306/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-icl-u2:          [FAIL][17] ([fdo#103375]) -> [DMESG-WARN][18] ([IGT#4] / [i915#263])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7833/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16306/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html

  
  [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
  [i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263
  [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
  [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
  [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
  [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816


Participating hosts (50 -> 35)
------------------------------

  Missing    (15): fi-ilk-m540 fi-bdw-samus fi-kbl-7560u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-byt-clapper fi-ivb-3770 fi-cfl-8109u fi-skl-6700k2 fi-blb-e6850 fi-bsw-kefka fi-skl-6600u fi-snb-2600 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7833 -> Patchwork_16306

  CI-20190529: 20190529
  CI_DRM_7833: 8210f0f999e2d396a8611e0cabc2f6c6a52468de @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5394: 991fd07bcd7add7a5beca2c95b72a994e62fbb75 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16306: d20c84c0e13065645fa82138503ceeb83767656b @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

d20c84c0e130 drm/i915/selftests/perf: measure memcpy bw between regions

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16306/index.html
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