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From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: riku.voipio@iki.fi, richard.henderson@linaro.org,
	laurent@vivier.eu, Taylor Simpson <tsimpson@quicinc.com>,
	philmd@redhat.com, aleksandar.m.mail@gmail.com
Subject: [RFC PATCH 30/66] Hexagon macros to interface with the generator
Date: Mon, 10 Feb 2020 18:40:08 -0600	[thread overview]
Message-ID: <1581381644-13678-31-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1581381644-13678-1-git-send-email-tsimpson@quicinc.com>

Various forms of declare, read, write, free

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/macros.h | 388 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 388 insertions(+)
 create mode 100644 target/hexagon/macros.h

diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
new file mode 100644
index 0000000..4399585
--- /dev/null
+++ b/target/hexagon/macros.h
@@ -0,0 +1,388 @@
+/*
+ *  Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MACROS_H
+#define MACROS_H
+
+#include "cpu.h"
+#include "hex_regs.h"
+#include "reg_fields.h"
+
+#ifdef QEMU_GENERATE
+#define DECL_REG(NAME, NUM, X, OFF) \
+    TCGv NAME = tcg_temp_local_new(); \
+    int NUM = REGNO(X) + OFF
+
+#define DECL_REG_WRITABLE(NAME, NUM, X, OFF) \
+    TCGv NAME = tcg_temp_local_new(); \
+    int NUM = REGNO(X) + OFF; \
+    do { \
+        int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); \
+        if (is_predicated && !is_preloaded(ctx, NUM)) { \
+            tcg_gen_mov_tl(hex_new_value[NUM], hex_gpr[NUM]); \
+        } \
+    } while (0)
+/*
+ * For read-only temps, avoid allocating and freeing
+ */
+#define DECL_REG_READONLY(NAME, NUM, X, OFF) \
+    TCGv NAME; \
+    int NUM = REGNO(X) + OFF
+
+#define DECL_RREG_d(NAME, NUM, X, OFF) \
+    DECL_REG_WRITABLE(NAME, NUM, X, OFF)
+#define DECL_RREG_e(NAME, NUM, X, OFF) \
+    DECL_REG(NAME, NUM, X, OFF)
+#define DECL_RREG_s(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+#define DECL_RREG_t(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+#define DECL_RREG_u(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+#define DECL_RREG_v(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+#define DECL_RREG_x(NAME, NUM, X, OFF) \
+    DECL_REG_WRITABLE(NAME, NUM, X, OFF)
+#define DECL_RREG_y(NAME, NUM, X, OFF) \
+    DECL_REG_WRITABLE(NAME, NUM, X, OFF)
+
+#define DECL_PREG_d(NAME, NUM, X, OFF) \
+    DECL_REG(NAME, NUM, X, OFF)
+#define DECL_PREG_e(NAME, NUM, X, OFF) \
+    DECL_REG(NAME, NUM, X, OFF)
+#define DECL_PREG_s(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+#define DECL_PREG_t(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+#define DECL_PREG_u(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+#define DECL_PREG_v(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+#define DECL_PREG_x(NAME, NUM, X, OFF) \
+    DECL_REG(NAME, NUM, X, OFF)
+#define DECL_PREG_y(NAME, NUM, X, OFF) \
+    DECL_REG(NAME, NUM, X, OFF)
+
+#define DECL_CREG_d(NAME, NUM, X, OFF) \
+    DECL_REG(NAME, NUM, X, OFF)
+#define DECL_CREG_s(NAME, NUM, X, OFF) \
+    DECL_REG(NAME, NUM, X, OFF)
+
+#define DECL_MREG_u(NAME, NUM, X, OFF) \
+    DECL_REG(NAME, NUM, X, OFF)
+
+#define DECL_NEW_NREG_s(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+#define DECL_NEW_NREG_t(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+
+#define DECL_NEW_PREG_t(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+#define DECL_NEW_PREG_u(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+#define DECL_NEW_PREG_v(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+
+#define DECL_NEW_OREG_s(NAME, NUM, X, OFF) \
+    DECL_REG_READONLY(NAME, NUM, X, OFF)
+
+#define DECL_PAIR(NAME, NUM, X, OFF) \
+    TCGv_i64 NAME = tcg_temp_local_new_i64(); \
+    size1u_t NUM = REGNO(X) + OFF
+
+#define DECL_PAIR_WRITABLE(NAME, NUM, X, OFF) \
+    TCGv_i64 NAME = tcg_temp_local_new_i64(); \
+    size1u_t NUM = REGNO(X) + OFF; \
+    do { \
+        int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); \
+        if (is_predicated) { \
+            if (!is_preloaded(ctx, NUM)) { \
+                tcg_gen_mov_tl(hex_new_value[NUM], hex_gpr[NUM]); \
+            } \
+            if (!is_preloaded(ctx, NUM + 1)) { \
+                tcg_gen_mov_tl(hex_new_value[NUM + 1], hex_gpr[NUM + 1]); \
+            } \
+        } \
+    } while (0)
+
+#define DECL_RREG_dd(NAME, NUM, X, OFF) \
+    DECL_PAIR_WRITABLE(NAME, NUM, X, OFF)
+#define DECL_RREG_ss(NAME, NUM, X, OFF) \
+    DECL_PAIR(NAME, NUM, X, OFF)
+#define DECL_RREG_tt(NAME, NUM, X, OFF) \
+    DECL_PAIR(NAME, NUM, X, OFF)
+#define DECL_RREG_xx(NAME, NUM, X, OFF) \
+    DECL_PAIR_WRITABLE(NAME, NUM, X, OFF)
+#define DECL_RREG_yy(NAME, NUM, X, OFF) \
+    DECL_PAIR_WRITABLE(NAME, NUM, X, OFF)
+
+#define DECL_CREG_dd(NAME, NUM, X, OFF) \
+    DECL_PAIR_WRITABLE(NAME, NUM, X, OFF)
+#define DECL_CREG_ss(NAME, NUM, X, OFF) \
+    DECL_PAIR(NAME, NUM, X, OFF)
+
+#define DECL_IMM(NAME, X) \
+    int NAME = IMMNO(X); \
+    do { \
+        NAME = NAME; \
+    } while (0)
+#define DECL_TCG_IMM(TCG_NAME, VAL) \
+    TCGv TCG_NAME = tcg_const_tl(VAL)
+
+#define DECL_EA \
+    TCGv EA; \
+    do { \
+        if (GET_ATTRIB(insn->opcode, A_CONDEXEC)) { \
+            EA = tcg_temp_local_new(); \
+        } else { \
+            EA = tcg_temp_new(); \
+        } \
+    } while (0)
+
+#define LOG_REG_WRITE(RNUM, VAL)\
+    do { \
+        int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); \
+        gen_log_reg_write(RNUM, VAL, insn->slot, is_predicated); \
+        ctx_log_reg_write(ctx, (RNUM)); \
+    } while (0)
+
+#define LOG_PRED_WRITE(PNUM, VAL) \
+    do { \
+        gen_log_pred_write(PNUM, VAL); \
+        ctx_log_pred_write(ctx, (PNUM)); \
+    } while (0)
+
+#define FREE_REG(NAME) \
+    tcg_temp_free(NAME)
+#define FREE_REG_READONLY(NAME) \
+    /* Nothing */
+
+#define FREE_RREG_d(NAME)            FREE_REG(NAME)
+#define FREE_RREG_e(NAME)            FREE_REG(NAME)
+#define FREE_RREG_s(NAME)            FREE_REG_READONLY(NAME)
+#define FREE_RREG_t(NAME)            FREE_REG_READONLY(NAME)
+#define FREE_RREG_u(NAME)            FREE_REG_READONLY(NAME)
+#define FREE_RREG_v(NAME)            FREE_REG_READONLY(NAME)
+#define FREE_RREG_x(NAME)            FREE_REG(NAME)
+#define FREE_RREG_y(NAME)            FREE_REG(NAME)
+
+#define FREE_PREG_d(NAME)            FREE_REG(NAME)
+#define FREE_PREG_e(NAME)            FREE_REG(NAME)
+#define FREE_PREG_s(NAME)            FREE_REG_READONLY(NAME)
+#define FREE_PREG_t(NAME)            FREE_REG_READONLY(NAME)
+#define FREE_PREG_u(NAME)            FREE_REG_READONLY(NAME)
+#define FREE_PREG_v(NAME)            FREE_REG_READONLY(NAME)
+#define FREE_PREG_x(NAME)            FREE_REG(NAME)
+
+#define FREE_CREG_d(NAME)            FREE_REG(NAME)
+#define FREE_CREG_s(NAME)            FREE_REG_READONLY(NAME)
+
+#define FREE_MREG_u(NAME)            FREE_REG_READONLY(NAME)
+
+#define FREE_NEW_NREG_s(NAME)        FREE_REG(NAME)
+#define FREE_NEW_NREG_t(NAME)        FREE_REG(NAME)
+
+#define FREE_NEW_PREG_t(NAME)        FREE_REG_READONLY(NAME)
+#define FREE_NEW_PREG_u(NAME)        FREE_REG_READONLY(NAME)
+#define FREE_NEW_PREG_v(NAME)        FREE_REG_READONLY(NAME)
+
+#define FREE_NEW_OREG_s(NAME)        FREE_REG(NAME)
+
+#define FREE_REG_PAIR(NAME) \
+    tcg_temp_free_i64(NAME)
+
+#define FREE_RREG_dd(NAME)           FREE_REG_PAIR(NAME)
+#define FREE_RREG_ss(NAME)           FREE_REG_PAIR(NAME)
+#define FREE_RREG_tt(NAME)           FREE_REG_PAIR(NAME)
+#define FREE_RREG_xx(NAME)           FREE_REG_PAIR(NAME)
+#define FREE_RREG_yy(NAME)           FREE_REG_PAIR(NAME)
+
+#define FREE_CREG_dd(NAME)           FREE_REG_PAIR(NAME)
+#define FREE_CREG_ss(NAME)           FREE_REG_PAIR(NAME)
+
+#define FREE_IMM(NAME)               /* nothing */
+#define FREE_TCG_IMM(NAME)           tcg_temp_free(NAME)
+
+#define FREE_EA \
+    tcg_temp_free(EA)
+#else
+#define LOG_REG_WRITE(RNUM, VAL)\
+  log_reg_write(env, RNUM, VAL, slot)
+#define LOG_PRED_WRITE(RNUM, VAL)\
+    log_pred_write(env, RNUM, VAL)
+#endif
+
+#define SLOT_WRAP(CODE) \
+    do { \
+        TCGv slot = tcg_const_tl(insn->slot); \
+        CODE; \
+        tcg_temp_free(slot); \
+    } while (0)
+
+#define PART1_WRAP(CODE) \
+    do { \
+        TCGv part1 = tcg_const_tl(insn->part1); \
+        CODE; \
+        tcg_temp_free(part1); \
+    } while (0)
+
+#define MARK_LATE_PRED_WRITE(RNUM) /* Not modelled in qemu */
+
+#define REGNO(NUM) (insn->regno[NUM])
+#define IMMNO(NUM) (insn->immed[NUM])
+
+#ifdef QEMU_GENERATE
+#define READ_REG(dest, NUM) \
+    gen_read_reg(dest, NUM)
+#define READ_REG_READONLY(dest, NUM) \
+    do { dest = hex_gpr[NUM]; } while (0)
+
+#define READ_RREG_s(dest, NUM) \
+    READ_REG_READONLY(dest, NUM)
+#define READ_RREG_t(dest, NUM) \
+    READ_REG_READONLY(dest, NUM)
+#define READ_RREG_u(dest, NUM) \
+    READ_REG_READONLY(dest, NUM)
+#define READ_RREG_x(dest, NUM) \
+    READ_REG(dest, NUM)
+#define READ_RREG_y(dest, NUM) \
+    READ_REG(dest, NUM)
+
+#define READ_OREG_s(dest, NUM) \
+    READ_REG_READONLY(dest, NUM)
+
+#ifdef QEMU_GENERATE
+#define READ_CREG_s(dest, NUM) \
+    do { \
+        if ((NUM) + HEX_REG_SA0 == HEX_REG_P3_0) { \
+            gen_read_p3_0(dest); \
+        } else { \
+            READ_REG_READONLY(dest, ((NUM) + HEX_REG_SA0)); \
+        } \
+    } while (0)
+#else
+static inline int32_t read_p3_0(CPUHexagonState *env)
+{
+    int32_t control_reg = 0;
+    int i;
+    for (i = NUM_PREGS - 1; i >= 0; i--) {
+        control_reg <<= 8;
+        control_reg |= env->pred[i] & 0xff;
+    }
+    return control_reg;
+}
+
+#define READ_CREG_s(dest, NUM) \
+    do { \
+        if (NUM == HEX_REG_P3_0) { \
+            dest = read_p3_0(env); \
+        } else { \
+            READ_REG_READONLY(dest, ((NUM) + HEX_REG_SA0)); \
+        } \
+    } while (0)
+#endif
+#define READ_MREG_u(dest, NUM) \
+    do { \
+        READ_REG_READONLY(dest, ((NUM) + HEX_REG_M0)); \
+        dest = dest; \
+    } while (0)
+#else
+#define READ_REG(NUM) \
+    (env->gpr[(NUM)])
+#define READ_MREG(NUM) \
+    (env->gpr[NUM + REG_M])
+#define READ_CSREG(NUM) \
+    (env->gpr[NUM + HEX_REG_CS0])
+#endif
+
+#ifdef QEMU_GENERATE
+#define READ_REG_PAIR(tmp, NUM) \
+    tcg_gen_concat_i32_i64(tmp, hex_gpr[NUM], hex_gpr[(NUM) + 1])
+#define READ_RREG_ss(tmp, NUM)          READ_REG_PAIR(tmp, NUM)
+#define READ_RREG_tt(tmp, NUM)          READ_REG_PAIR(tmp, NUM)
+#define READ_RREG_xx(tmp, NUM)          READ_REG_PAIR(tmp, NUM)
+#define READ_RREG_yy(tmp, NUM)          READ_REG_PAIR(tmp, NUM)
+
+#define READ_CREG_PAIR(tmp, i) \
+    READ_REG_PAIR(tmp, ((i) + HEX_REG_SA0))
+#define READ_CREG_ss(tmp, i)            READ_CREG_PAIR(tmp, i)
+#endif
+
+#ifdef QEMU_GENERATE
+#define READ_PREG(dest, NUM)             gen_read_preg(dest, (NUM))
+#define READ_PREG_READONLY(dest, NUM)    do { dest = hex_pred[NUM]; } while (0)
+
+#define READ_PREG_s(dest, NUM)           READ_PREG_READONLY(dest, NUM)
+#define READ_PREG_t(dest, NUM)           READ_PREG_READONLY(dest, NUM)
+#define READ_PREG_u(dest, NUM)           READ_PREG_READONLY(dest, NUM)
+#define READ_PREG_v(dest, NUM)           READ_PREG_READONLY(dest, NUM)
+#define READ_PREG_x(dest, NUM)           READ_PREG(dest, NUM)
+
+#define READ_NEW_PREG(pred, PNUM) \
+    do { pred = hex_new_pred_value[PNUM]; } while (0)
+#define READ_NEW_PREG_t(pred, PNUM)      READ_NEW_PREG(pred, PNUM)
+#define READ_NEW_PREG_u(pred, PNUM)      READ_NEW_PREG(pred, PNUM)
+#define READ_NEW_PREG_v(pred, PNUM)      READ_NEW_PREG(pred, PNUM)
+
+#define READ_NEW_REG(tmp, i) \
+    do { tmp = tcg_const_tl(i); } while (0)
+#define READ_NEW_NREG_s(tmp, i)          READ_NEW_REG(tmp, i)
+#define READ_NEW_NREG_t(tmp, i)          READ_NEW_REG(tmp, i)
+#define READ_NEW_OREG_s(tmp, i)          READ_NEW_REG(tmp, i)
+#else
+#define READ_PREG(NUM)                (env->pred[NUM])
+#endif
+
+
+#define WRITE_RREG(NUM, VAL)             LOG_REG_WRITE(NUM, VAL)
+#define WRITE_RREG_d(NUM, VAL)           LOG_REG_WRITE(NUM, VAL)
+#define WRITE_RREG_e(NUM, VAL)           LOG_REG_WRITE(NUM, VAL)
+#define WRITE_RREG_x(NUM, VAL)           LOG_REG_WRITE(NUM, VAL)
+#define WRITE_RREG_y(NUM, VAL)           LOG_REG_WRITE(NUM, VAL)
+
+#define WRITE_PREG(NUM, VAL)             LOG_PRED_WRITE(NUM, VAL)
+#define WRITE_PREG_d(NUM, VAL)           LOG_PRED_WRITE(NUM, VAL)
+#define WRITE_PREG_e(NUM, VAL)           LOG_PRED_WRITE(NUM, VAL)
+#define WRITE_PREG_x(NUM, VAL)           LOG_PRED_WRITE(NUM, VAL)
+
+#ifdef QEMU_GENERATE
+#define WRITE_CREG(i, tmp) \
+    do { \
+        if (i + HEX_REG_SA0 == HEX_REG_P3_0) { \
+            gen_write_p3_0(tmp); \
+        } else { \
+            WRITE_RREG((i) + HEX_REG_SA0, tmp); \
+        } \
+    } while (0)
+#define WRITE_CREG_d(NUM, VAL)           WRITE_CREG(NUM, VAL)
+
+#define WRITE_CREG_PAIR(i, tmp)          WRITE_REG_PAIR((i) + HEX_REG_SA0, tmp)
+#define WRITE_CREG_dd(NUM, VAL)          WRITE_CREG_PAIR(NUM, VAL)
+
+#define WRITE_REG_PAIR(NUM, VAL) \
+    do { \
+        int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); \
+        gen_log_reg_write_pair(NUM, VAL, insn->slot, is_predicated); \
+        ctx_log_reg_write(ctx, (NUM)); \
+        ctx_log_reg_write(ctx, (NUM) + 1); \
+    } while (0)
+
+#define WRITE_RREG_dd(NUM, VAL)          WRITE_REG_PAIR(NUM, VAL)
+#define WRITE_RREG_xx(NUM, VAL)          WRITE_REG_PAIR(NUM, VAL)
+#define WRITE_RREG_yy(NUM, VAL)          WRITE_REG_PAIR(NUM, VAL)
+#endif
+
-- 
2.7.4


  parent reply	other threads:[~2020-02-11  1:05 UTC|newest]

Thread overview: 94+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-11  0:39 [RFC PATCH 00/66] Hexagon patch series Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 01/66] Hexagon Maintainers Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 02/66] Hexagon ELF Machine Definition Taylor Simpson
2020-02-11  7:16   ` Philippe Mathieu-Daudé
2020-02-11  0:39 ` [RFC PATCH 03/66] Hexagon CPU Scalar Core Definition Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 04/66] Hexagon register names Taylor Simpson
2020-02-11  7:18   ` Philippe Mathieu-Daudé
2020-02-11  0:39 ` [RFC PATCH 05/66] Hexagon Disassembler Taylor Simpson
2020-02-11  7:20   ` Philippe Mathieu-Daudé
2020-02-11  0:39 ` [RFC PATCH 06/66] Hexagon CPU Scalar Core Helpers Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 07/66] Hexagon GDB Stub Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 08/66] Hexagon instruction and packet types Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 09/66] Hexagon architecture types Taylor Simpson
2020-02-11  7:23   ` Philippe Mathieu-Daudé
2020-02-11  0:39 ` [RFC PATCH 10/66] Hexagon register fields Taylor Simpson
2020-02-11 15:29   ` Philippe Mathieu-Daudé
2020-02-11  0:39 ` [RFC PATCH 11/66] Hexagon instruction attributes Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 12/66] Hexagon register map Taylor Simpson
2020-02-11  7:26   ` Philippe Mathieu-Daudé
2020-02-11  0:39 ` [RFC PATCH 13/66] Hexagon instruction/packet decode Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 14/66] Hexagon instruction printing Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 15/66] Hexagon arch import - instruction semantics definitions Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 16/66] Hexagon arch import - macro definitions Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 17/66] Hexagon arch import - instruction encoding Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 18/66] Hexagon instruction class definitions Taylor Simpson
2020-02-11  0:39 ` [RFC PATCH 19/66] Hexagon instruction utility functions Taylor Simpson
2020-02-11  7:29   ` Philippe Mathieu-Daudé
2020-02-11  0:39 ` [RFC PATCH 20/66] Hexagon generator phase 1 - C preprocessor for semantics Taylor Simpson
2020-02-11  7:30   ` Philippe Mathieu-Daudé
2020-02-11  0:39 ` [RFC PATCH 21/66] Hexagon generator phase 2 - qemu_def_generated.h Taylor Simpson
2020-02-11  7:33   ` Philippe Mathieu-Daudé
2020-02-11  0:40 ` [RFC PATCH 22/66] Hexagon generator phase 2 - qemu_wrap_generated.h Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 23/66] Hexagon generator phase 2 - opcodes_def_generated.h Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 24/66] Hexagon generator phase 2 - op_attribs_generated.h Taylor Simpson
2020-02-11  8:01   ` Philippe Mathieu-Daudé
2020-02-11  0:40 ` [RFC PATCH 25/66] Hexagon generator phase 2 - op_regs_generated.h Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 26/66] Hexagon generator phase 2 - printinsn-generated.h Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 27/66] Hexagon generator phase 3 - C preprocessor for decode tree Taylor Simpson
2020-02-11  7:35   ` Philippe Mathieu-Daudé
2020-02-11  0:40 ` [RFC PATCH 28/66] Hexagon generater phase 4 - Decode tree Taylor Simpson
2020-02-11  7:37   ` Philippe Mathieu-Daudé
2020-02-11  8:03     ` Philippe Mathieu-Daudé
2020-02-11  0:40 ` [RFC PATCH 29/66] Hexagon opcode data structures Taylor Simpson
2020-02-11  7:40   ` Philippe Mathieu-Daudé
2020-02-12 17:36     ` Taylor Simpson
2020-02-11  0:40 ` Taylor Simpson [this message]
2020-02-11  0:40 ` [RFC PATCH 31/66] Hexagon macros referenced in instruction semantics Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 32/66] Hexagon instruction classes Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 33/66] Hexagon TCG generation helpers - step 1 Taylor Simpson
2020-02-11 15:22   ` Philippe Mathieu-Daudé
2020-02-11  0:40 ` [RFC PATCH 34/66] Hexagon TCG generation helpers - step 2 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 35/66] Hexagon TCG generation helpers - step 3 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 36/66] Hexagon TCG generation helpers - step 4 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 37/66] Hexagon TCG generation helpers - step 5 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 38/66] Hexagon TCG generation - step 01 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 39/66] Hexagon TCG generation - step 02 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 40/66] Hexagon TCG generation - step 03 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 41/66] Hexagon TCG generation - step 04 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 42/66] Hexagon TCG generation - step 05 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 43/66] Hexagon TCG generation - step 06 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 44/66] Hexagon TCG generation - step 07 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 45/66] Hexagon TCG generation - step 08 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 46/66] Hexagon TCG generation - step 09 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 47/66] Hexagon TCG generation - step 10 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 48/66] Hexagon TCG generation - step 11 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 49/66] Hexagon TCG generation - step 12 Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 50/66] Hexagon translation Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 51/66] Hexagon Linux user emulation Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 52/66] Hexagon build infrastructure Taylor Simpson
2020-02-11  7:15   ` Philippe Mathieu-Daudé
2020-02-11  0:40 ` [RFC PATCH 53/66] Hexagon - Add Hexagon Vector eXtensions (HVX) to core definition Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 54/66] Hexagon HVX support in gdbstub Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 55/66] Hexagon HVX import instruction encodings Taylor Simpson
2020-02-11  7:02   ` Philippe Mathieu-Daudé
2020-02-11 14:35     ` Taylor Simpson
2020-02-11 14:40       ` Philippe Mathieu-Daudé
2020-02-11 14:43         ` Philippe Mathieu-Daudé
2020-02-11  0:40 ` [RFC PATCH 56/66] Hexagon HVX import semantics Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 57/66] Hexagon HVX import macro definitions Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 58/66] Hexagon HVX semantics generator Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 59/66] Hexagon HVX instruction decoding Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 60/66] Hexagon HVX instruction utility functions Taylor Simpson
2020-02-11  7:46   ` Philippe Mathieu-Daudé
2020-02-11  0:40 ` [RFC PATCH 61/66] Hexagon HVX macros to interface with the generator Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 62/66] Hexagon HVX macros referenced in instruction semantics Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 63/66] Hexagon HVX helper to commit vector stores (masked and scatter/gather) Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 64/66] Hexagon HVX TCG generation Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 65/66] Hexagon HVX translation Taylor Simpson
2020-02-11  0:40 ` [RFC PATCH 66/66] Hexagon HVX build infrastructure Taylor Simpson
2020-02-11  1:31 ` [RFC PATCH 00/66] Hexagon patch series no-reply
2020-02-11  7:49   ` Philippe Mathieu-Daudé
2020-02-11  7:53 ` Philippe Mathieu-Daudé
2020-02-11 15:32 ` Philippe Mathieu-Daudé
2020-02-26 16:13   ` Taylor Simpson

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