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* [Bug 1862167] [NEW] Variation of SVE register size (qemu-user-aarch64)
@ 2020-02-06 13:02 Kentaro Kawakami
  2020-02-11 11:57 ` [Bug 1862167] " Laurent Vivier
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Kentaro Kawakami @ 2020-02-06 13:02 UTC (permalink / raw)
  To: qemu-devel

Public bug reported:

Specification of ARMv8-A SVE extention allows various values ​​for the
size of the SVE register. On the other hand, it seems that the current
qemu-aarch64 supports only the maximum length of 2048 bits as the SVE
register size. I am writing an assembler program for a CPU that is
compliant with ARMv8-A + SVE and has a 512-bit SVE register, but when
this is run with qemu-user-aarch64, a 2048-bit load / store instruction
is executed This causes a segmentation fault. Shouldn't qeum-user-
aarch64 have an option to specify the SVE register size?

** Affects: qemu
     Importance: Undecided
         Status: New

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https://bugs.launchpad.net/bugs/1862167

Title:
  Variation of SVE register size (qemu-user-aarch64)

Status in QEMU:
  New

Bug description:
  Specification of ARMv8-A SVE extention allows various values ​​for the
  size of the SVE register. On the other hand, it seems that the current
  qemu-aarch64 supports only the maximum length of 2048 bits as the SVE
  register size. I am writing an assembler program for a CPU that is
  compliant with ARMv8-A + SVE and has a 512-bit SVE register, but when
  this is run with qemu-user-aarch64, a 2048-bit load / store
  instruction is executed This causes a segmentation fault. Shouldn't
  qeum-user-aarch64 have an option to specify the SVE register size?

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1862167/+subscriptions


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Bug 1862167] Re: Variation of SVE register size (qemu-user-aarch64)
  2020-02-06 13:02 [Bug 1862167] [NEW] Variation of SVE register size (qemu-user-aarch64) Kentaro Kawakami
@ 2020-02-11 11:57 ` Laurent Vivier
  2020-02-11 12:42 ` Peter Maydell
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Laurent Vivier @ 2020-02-11 11:57 UTC (permalink / raw)
  To: qemu-devel

This is already managed by a cpu property.

0df9142d27d5 ("target/arm/cpu64: max cpu: Introduce sve<N> properties")

See docs/arm-cpu-features.rst

Try "-cpu max,sve512=on".

-- 
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https://bugs.launchpad.net/bugs/1862167

Title:
  Variation of SVE register size (qemu-user-aarch64)

Status in QEMU:
  New

Bug description:
  Specification of ARMv8-A SVE extention allows various values ​​for the
  size of the SVE register. On the other hand, it seems that the current
  qemu-aarch64 supports only the maximum length of 2048 bits as the SVE
  register size. I am writing an assembler program for a CPU that is
  compliant with ARMv8-A + SVE and has a 512-bit SVE register, but when
  this is run with qemu-user-aarch64, a 2048-bit load / store
  instruction is executed This causes a segmentation fault. Shouldn't
  qeum-user-aarch64 have an option to specify the SVE register size?

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1862167/+subscriptions


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Bug 1862167] Re: Variation of SVE register size (qemu-user-aarch64)
  2020-02-06 13:02 [Bug 1862167] [NEW] Variation of SVE register size (qemu-user-aarch64) Kentaro Kawakami
  2020-02-11 11:57 ` [Bug 1862167] " Laurent Vivier
@ 2020-02-11 12:42 ` Peter Maydell
  2020-02-11 13:03 ` Alex Bennée
  2020-02-13 14:48 ` Kentaro Kawakami
  3 siblings, 0 replies; 5+ messages in thread
From: Peter Maydell @ 2020-02-11 12:42 UTC (permalink / raw)
  To: qemu-devel

Note also that the vector length in SVE is not fixed -- you should be
writing your guest code to support arbitrary vector lengths, because
otherwise it will not run on all SVE-supporting CPUs.

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https://bugs.launchpad.net/bugs/1862167

Title:
  Variation of SVE register size (qemu-user-aarch64)

Status in QEMU:
  New

Bug description:
  Specification of ARMv8-A SVE extention allows various values ​​for the
  size of the SVE register. On the other hand, it seems that the current
  qemu-aarch64 supports only the maximum length of 2048 bits as the SVE
  register size. I am writing an assembler program for a CPU that is
  compliant with ARMv8-A + SVE and has a 512-bit SVE register, but when
  this is run with qemu-user-aarch64, a 2048-bit load / store
  instruction is executed This causes a segmentation fault. Shouldn't
  qeum-user-aarch64 have an option to specify the SVE register size?

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1862167/+subscriptions


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Bug 1862167] Re: Variation of SVE register size (qemu-user-aarch64)
  2020-02-06 13:02 [Bug 1862167] [NEW] Variation of SVE register size (qemu-user-aarch64) Kentaro Kawakami
  2020-02-11 11:57 ` [Bug 1862167] " Laurent Vivier
  2020-02-11 12:42 ` Peter Maydell
@ 2020-02-11 13:03 ` Alex Bennée
  2020-02-13 14:48 ` Kentaro Kawakami
  3 siblings, 0 replies; 5+ messages in thread
From: Alex Bennée @ 2020-02-11 13:03 UTC (permalink / raw)
  To: qemu-devel

** Tags added: arm

** Changed in: qemu
       Status: New => Invalid

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https://bugs.launchpad.net/bugs/1862167

Title:
  Variation of SVE register size (qemu-user-aarch64)

Status in QEMU:
  Invalid

Bug description:
  Specification of ARMv8-A SVE extention allows various values ​​for the
  size of the SVE register. On the other hand, it seems that the current
  qemu-aarch64 supports only the maximum length of 2048 bits as the SVE
  register size. I am writing an assembler program for a CPU that is
  compliant with ARMv8-A + SVE and has a 512-bit SVE register, but when
  this is run with qemu-user-aarch64, a 2048-bit load / store
  instruction is executed This causes a segmentation fault. Shouldn't
  qeum-user-aarch64 have an option to specify the SVE register size?

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1862167/+subscriptions


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Bug 1862167] Re: Variation of SVE register size (qemu-user-aarch64)
  2020-02-06 13:02 [Bug 1862167] [NEW] Variation of SVE register size (qemu-user-aarch64) Kentaro Kawakami
                   ` (2 preceding siblings ...)
  2020-02-11 13:03 ` Alex Bennée
@ 2020-02-13 14:48 ` Kentaro Kawakami
  3 siblings, 0 replies; 5+ messages in thread
From: Kentaro Kawakami @ 2020-02-13 14:48 UTC (permalink / raw)
  To: qemu-devel

Thank you for your kind advice. I'll try it.

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1862167

Title:
  Variation of SVE register size (qemu-user-aarch64)

Status in QEMU:
  Invalid

Bug description:
  Specification of ARMv8-A SVE extention allows various values ​​for the
  size of the SVE register. On the other hand, it seems that the current
  qemu-aarch64 supports only the maximum length of 2048 bits as the SVE
  register size. I am writing an assembler program for a CPU that is
  compliant with ARMv8-A + SVE and has a 512-bit SVE register, but when
  this is run with qemu-user-aarch64, a 2048-bit load / store
  instruction is executed This causes a segmentation fault. Shouldn't
  qeum-user-aarch64 have an option to specify the SVE register size?

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1862167/+subscriptions


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2020-02-13 15:23 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-06 13:02 [Bug 1862167] [NEW] Variation of SVE register size (qemu-user-aarch64) Kentaro Kawakami
2020-02-11 11:57 ` [Bug 1862167] " Laurent Vivier
2020-02-11 12:42 ` Peter Maydell
2020-02-11 13:03 ` Alex Bennée
2020-02-13 14:48 ` Kentaro Kawakami

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