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* [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-02-14  4:49 ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-02-14  4:49 UTC (permalink / raw)
  To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
  Cc: Philipp Zabel, YT Shen, Thierry Reding, CK Hu, linux-arm-kernel,
	tfiga, drinkcat, linux-kernel, srv_heupstream, Bibby Hsieh,
	Yongqiang Niu

In order to use GCE function, we need add some information
into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index be4428c92f35..8b522b039a37 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/power/mt8183-power.h>
+#include <dt-bindings/gce/mt8183-gce.h>
 #include "mt8183-pinfunc.h"
 
 / {
@@ -664,6 +665,9 @@
 			reg = <0 0x14000000 0 0x1000>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			#clock-cells = <1>;
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 		};
 
 		ovl0: ovl@14008000 {
@@ -672,6 +676,7 @@
 			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
 		};
 
 		ovl_2l0: ovl@14009000 {
@@ -680,6 +685,7 @@
 			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
 		};
 
 		ovl_2l1: ovl@1400a000 {
@@ -688,6 +694,7 @@
 			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
 		};
 
 		rdma0: rdma@1400b000 {
@@ -697,6 +704,7 @@
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
 			mediatek,rdma_fifo_size = <5120>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
 		};
 
 		rdma1: rdma@1400c000 {
@@ -706,6 +714,7 @@
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
 			mediatek,rdma_fifo_size = <2048>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
 		};
 
 		color0: color@1400e000 {
@@ -715,6 +724,7 @@
 			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
 		};
 
 		ccorr0: ccorr@1400f000 {
@@ -723,6 +733,7 @@
 			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
 		};
 
 		aal0: aal@14010000 {
@@ -732,6 +743,7 @@
 			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
 		};
 
 		gamma0: gamma@14011000 {
@@ -741,6 +753,7 @@
 			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
 		};
 
 		dither0: dither@14012000 {
@@ -749,6 +762,7 @@
 			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
 		};
 
 		mutex: mutex@14016000 {
@@ -756,6 +770,8 @@
 			reg = <0 0x14016000 0 0x1000>;
 			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
+					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
 		};
 
 		smi_common: smi@14019000 {
-- 
2.18.0

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-02-14  4:49 ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-02-14  4:49 UTC (permalink / raw)
  To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, Bibby Hsieh, srv_heupstream, Yongqiang Niu,
	linux-kernel, tfiga, CK Hu, Thierry Reding, Philipp Zabel,
	linux-arm-kernel

In order to use GCE function, we need add some information
into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index be4428c92f35..8b522b039a37 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/power/mt8183-power.h>
+#include <dt-bindings/gce/mt8183-gce.h>
 #include "mt8183-pinfunc.h"
 
 / {
@@ -664,6 +665,9 @@
 			reg = <0 0x14000000 0 0x1000>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			#clock-cells = <1>;
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 		};
 
 		ovl0: ovl@14008000 {
@@ -672,6 +676,7 @@
 			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
 		};
 
 		ovl_2l0: ovl@14009000 {
@@ -680,6 +685,7 @@
 			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
 		};
 
 		ovl_2l1: ovl@1400a000 {
@@ -688,6 +694,7 @@
 			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
 		};
 
 		rdma0: rdma@1400b000 {
@@ -697,6 +704,7 @@
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
 			mediatek,rdma_fifo_size = <5120>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
 		};
 
 		rdma1: rdma@1400c000 {
@@ -706,6 +714,7 @@
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
 			mediatek,rdma_fifo_size = <2048>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
 		};
 
 		color0: color@1400e000 {
@@ -715,6 +724,7 @@
 			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
 		};
 
 		ccorr0: ccorr@1400f000 {
@@ -723,6 +733,7 @@
 			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
 		};
 
 		aal0: aal@14010000 {
@@ -732,6 +743,7 @@
 			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
 		};
 
 		gamma0: gamma@14011000 {
@@ -741,6 +753,7 @@
 			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
 		};
 
 		dither0: dither@14012000 {
@@ -749,6 +762,7 @@
 			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
 		};
 
 		mutex: mutex@14016000 {
@@ -756,6 +770,8 @@
 			reg = <0 0x14016000 0 0x1000>;
 			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
+					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
 		};
 
 		smi_common: smi@14019000 {
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-02-14  4:49 ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-02-14  4:49 UTC (permalink / raw)
  To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, Bibby Hsieh, srv_heupstream, Yongqiang Niu,
	linux-kernel, tfiga, CK Hu, Thierry Reding, Philipp Zabel,
	YT Shen, linux-arm-kernel

In order to use GCE function, we need add some information
into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index be4428c92f35..8b522b039a37 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/power/mt8183-power.h>
+#include <dt-bindings/gce/mt8183-gce.h>
 #include "mt8183-pinfunc.h"
 
 / {
@@ -664,6 +665,9 @@
 			reg = <0 0x14000000 0 0x1000>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			#clock-cells = <1>;
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 		};
 
 		ovl0: ovl@14008000 {
@@ -672,6 +676,7 @@
 			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
 		};
 
 		ovl_2l0: ovl@14009000 {
@@ -680,6 +685,7 @@
 			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
 		};
 
 		ovl_2l1: ovl@1400a000 {
@@ -688,6 +694,7 @@
 			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
 		};
 
 		rdma0: rdma@1400b000 {
@@ -697,6 +704,7 @@
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
 			mediatek,rdma_fifo_size = <5120>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
 		};
 
 		rdma1: rdma@1400c000 {
@@ -706,6 +714,7 @@
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
 			mediatek,rdma_fifo_size = <2048>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
 		};
 
 		color0: color@1400e000 {
@@ -715,6 +724,7 @@
 			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
 		};
 
 		ccorr0: ccorr@1400f000 {
@@ -723,6 +733,7 @@
 			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
 		};
 
 		aal0: aal@14010000 {
@@ -732,6 +743,7 @@
 			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
 		};
 
 		gamma0: gamma@14011000 {
@@ -741,6 +753,7 @@
 			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
 		};
 
 		dither0: dither@14012000 {
@@ -749,6 +762,7 @@
 			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
 		};
 
 		mutex: mutex@14016000 {
@@ -756,6 +770,8 @@
 			reg = <0 0x14016000 0 0x1000>;
 			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
+					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
 		};
 
 		smi_common: smi@14019000 {
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-02-14  4:49 ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-02-14  4:49 UTC (permalink / raw)
  To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, srv_heupstream, Yongqiang Niu, linux-kernel, tfiga,
	Thierry Reding, linux-arm-kernel

In order to use GCE function, we need add some information
into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index be4428c92f35..8b522b039a37 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/power/mt8183-power.h>
+#include <dt-bindings/gce/mt8183-gce.h>
 #include "mt8183-pinfunc.h"
 
 / {
@@ -664,6 +665,9 @@
 			reg = <0 0x14000000 0 0x1000>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			#clock-cells = <1>;
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 		};
 
 		ovl0: ovl@14008000 {
@@ -672,6 +676,7 @@
 			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
 		};
 
 		ovl_2l0: ovl@14009000 {
@@ -680,6 +685,7 @@
 			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
 		};
 
 		ovl_2l1: ovl@1400a000 {
@@ -688,6 +694,7 @@
 			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
 		};
 
 		rdma0: rdma@1400b000 {
@@ -697,6 +704,7 @@
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
 			mediatek,rdma_fifo_size = <5120>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
 		};
 
 		rdma1: rdma@1400c000 {
@@ -706,6 +714,7 @@
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
 			mediatek,rdma_fifo_size = <2048>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
 		};
 
 		color0: color@1400e000 {
@@ -715,6 +724,7 @@
 			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
 		};
 
 		ccorr0: ccorr@1400f000 {
@@ -723,6 +733,7 @@
 			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
 		};
 
 		aal0: aal@14010000 {
@@ -732,6 +743,7 @@
 			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
 		};
 
 		gamma0: gamma@14011000 {
@@ -741,6 +753,7 @@
 			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
 		};
 
 		dither0: dither@14012000 {
@@ -749,6 +762,7 @@
 			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
 		};
 
 		mutex: mutex@14016000 {
@@ -756,6 +770,8 @@
 			reg = <0 0x14016000 0 0x1000>;
 			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
+					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
 		};
 
 		smi_common: smi@14019000 {
-- 
2.18.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send
  2020-02-14  4:49 ` Bibby Hsieh
  (?)
  (?)
@ 2020-02-14  4:49   ` Bibby Hsieh
  -1 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-02-14  4:49 UTC (permalink / raw)
  To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
  Cc: Philipp Zabel, YT Shen, Thierry Reding, CK Hu, linux-arm-kernel,
	tfiga, drinkcat, linux-kernel, srv_heupstream, Bibby Hsieh

Mediatek CMDQ driver removed atomic parameter and implementation
related to atomic. DRM driver need to make sure previous message
done or be aborted before we send next message.

If previous message is still waiting for event, it means the
setting hasn't been updated into display hardware register,
we can abort the message and send next message to update the
newest setting into display hardware.
If previous message already started, we have to wait it until
transmission has been completed.

So we flush mbox client before we send new message to controller
driver.

This patch depends on ptach:
[0/3] Remove atomic_exec
https://patchwork.kernel.org/cover/11381677/

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 3c53ea22208c..e35b66c5ba0f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -491,6 +491,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
 	}
 #if IS_ENABLED(CONFIG_MTK_CMDQ)
 	if (mtk_crtc->cmdq_client) {
+		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
 		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
 		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
 		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
-- 
2.18.0

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send
@ 2020-02-14  4:49   ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-02-14  4:49 UTC (permalink / raw)
  To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, Bibby Hsieh, srv_heupstream, linux-kernel, tfiga,
	CK Hu, Thierry Reding, Philipp Zabel, linux-arm-kernel

Mediatek CMDQ driver removed atomic parameter and implementation
related to atomic. DRM driver need to make sure previous message
done or be aborted before we send next message.

If previous message is still waiting for event, it means the
setting hasn't been updated into display hardware register,
we can abort the message and send next message to update the
newest setting into display hardware.
If previous message already started, we have to wait it until
transmission has been completed.

So we flush mbox client before we send new message to controller
driver.

This patch depends on ptach:
[0/3] Remove atomic_exec
https://patchwork.kernel.org/cover/11381677/

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 3c53ea22208c..e35b66c5ba0f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -491,6 +491,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
 	}
 #if IS_ENABLED(CONFIG_MTK_CMDQ)
 	if (mtk_crtc->cmdq_client) {
+		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
 		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
 		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
 		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send
@ 2020-02-14  4:49   ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-02-14  4:49 UTC (permalink / raw)
  To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, Bibby Hsieh, srv_heupstream, linux-kernel, tfiga,
	CK Hu, Thierry Reding, Philipp Zabel, YT Shen, linux-arm-kernel

Mediatek CMDQ driver removed atomic parameter and implementation
related to atomic. DRM driver need to make sure previous message
done or be aborted before we send next message.

If previous message is still waiting for event, it means the
setting hasn't been updated into display hardware register,
we can abort the message and send next message to update the
newest setting into display hardware.
If previous message already started, we have to wait it until
transmission has been completed.

So we flush mbox client before we send new message to controller
driver.

This patch depends on ptach:
[0/3] Remove atomic_exec
https://patchwork.kernel.org/cover/11381677/

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 3c53ea22208c..e35b66c5ba0f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -491,6 +491,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
 	}
 #if IS_ENABLED(CONFIG_MTK_CMDQ)
 	if (mtk_crtc->cmdq_client) {
+		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
 		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
 		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
 		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send
@ 2020-02-14  4:49   ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-02-14  4:49 UTC (permalink / raw)
  To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, srv_heupstream, linux-kernel, tfiga, Thierry Reding,
	linux-arm-kernel

Mediatek CMDQ driver removed atomic parameter and implementation
related to atomic. DRM driver need to make sure previous message
done or be aborted before we send next message.

If previous message is still waiting for event, it means the
setting hasn't been updated into display hardware register,
we can abort the message and send next message to update the
newest setting into display hardware.
If previous message already started, we have to wait it until
transmission has been completed.

So we flush mbox client before we send new message to controller
driver.

This patch depends on ptach:
[0/3] Remove atomic_exec
https://patchwork.kernel.org/cover/11381677/

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 3c53ea22208c..e35b66c5ba0f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -491,6 +491,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
 	}
 #if IS_ENABLED(CONFIG_MTK_CMDQ)
 	if (mtk_crtc->cmdq_client) {
+		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
 		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
 		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
 		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
-- 
2.18.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH 3/3] drm/mediatek: move gce event property to mutex device node
  2020-02-14  4:49 ` Bibby Hsieh
  (?)
  (?)
@ 2020-02-14  4:49   ` Bibby Hsieh
  -1 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-02-14  4:49 UTC (permalink / raw)
  To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
  Cc: Philipp Zabel, YT Shen, Thierry Reding, CK Hu, linux-arm-kernel,
	tfiga, drinkcat, linux-kernel, srv_heupstream, Bibby Hsieh

According mtk hardware design, stream_done0 and stream_done1 are
generated by mutex, so we move gce event property to mutex device mode.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index e35b66c5ba0f..e1cc7703a312 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -820,7 +820,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
 			drm_crtc_index(&mtk_crtc->base));
 		mtk_crtc->cmdq_client = NULL;
 	}
-	ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
+	ret = of_property_read_u32_index(priv->mutex_node, "mediatek,gce-events",
 					 drm_crtc_index(&mtk_crtc->base),
 					 &mtk_crtc->cmdq_event);
 	if (ret)
-- 
2.18.0

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH 3/3] drm/mediatek: move gce event property to mutex device node
@ 2020-02-14  4:49   ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-02-14  4:49 UTC (permalink / raw)
  To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, Bibby Hsieh, srv_heupstream, linux-kernel, tfiga,
	CK Hu, Thierry Reding, Philipp Zabel, linux-arm-kernel

According mtk hardware design, stream_done0 and stream_done1 are
generated by mutex, so we move gce event property to mutex device mode.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index e35b66c5ba0f..e1cc7703a312 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -820,7 +820,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
 			drm_crtc_index(&mtk_crtc->base));
 		mtk_crtc->cmdq_client = NULL;
 	}
-	ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
+	ret = of_property_read_u32_index(priv->mutex_node, "mediatek,gce-events",
 					 drm_crtc_index(&mtk_crtc->base),
 					 &mtk_crtc->cmdq_event);
 	if (ret)
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH 3/3] drm/mediatek: move gce event property to mutex device node
@ 2020-02-14  4:49   ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-02-14  4:49 UTC (permalink / raw)
  To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, Bibby Hsieh, srv_heupstream, linux-kernel, tfiga,
	CK Hu, Thierry Reding, Philipp Zabel, YT Shen, linux-arm-kernel

According mtk hardware design, stream_done0 and stream_done1 are
generated by mutex, so we move gce event property to mutex device mode.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index e35b66c5ba0f..e1cc7703a312 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -820,7 +820,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
 			drm_crtc_index(&mtk_crtc->base));
 		mtk_crtc->cmdq_client = NULL;
 	}
-	ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
+	ret = of_property_read_u32_index(priv->mutex_node, "mediatek,gce-events",
 					 drm_crtc_index(&mtk_crtc->base),
 					 &mtk_crtc->cmdq_event);
 	if (ret)
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH 3/3] drm/mediatek: move gce event property to mutex device node
@ 2020-02-14  4:49   ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-02-14  4:49 UTC (permalink / raw)
  To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, srv_heupstream, linux-kernel, tfiga, Thierry Reding,
	linux-arm-kernel

According mtk hardware design, stream_done0 and stream_done1 are
generated by mutex, so we move gce event property to mutex device mode.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index e35b66c5ba0f..e1cc7703a312 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -820,7 +820,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
 			drm_crtc_index(&mtk_crtc->base));
 		mtk_crtc->cmdq_client = NULL;
 	}
-	ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
+	ret = of_property_read_u32_index(priv->mutex_node, "mediatek,gce-events",
 					 drm_crtc_index(&mtk_crtc->base),
 					 &mtk_crtc->cmdq_event);
 	if (ret)
-- 
2.18.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* Re: [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send
  2020-02-14  4:49   ` Bibby Hsieh
  (?)
  (?)
@ 2020-02-14  6:48     ` CK Hu
  -1 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2020-02-14  6:48 UTC (permalink / raw)
  To: Bibby Hsieh
  Cc: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel,
	linux-mediatek, Philipp Zabel, YT Shen, Thierry Reding,
	linux-arm-kernel, tfiga, drinkcat, linux-kernel, srv_heupstream

Hi, Bibby:

On Fri, 2020-02-14 at 12:49 +0800, Bibby Hsieh wrote:
> Mediatek CMDQ driver removed atomic parameter and implementation
> related to atomic. DRM driver need to make sure previous message
> done or be aborted before we send next message.
> 
> If previous message is still waiting for event, it means the
> setting hasn't been updated into display hardware register,
> we can abort the message and send next message to update the
> newest setting into display hardware.
> If previous message already started, we have to wait it until
> transmission has been completed.
> 
> So we flush mbox client before we send new message to controller
> driver.
> 

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> This patch depends on ptach:
> [0/3] Remove atomic_exec
> https://patchwork.kernel.org/cover/11381677/
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 3c53ea22208c..e35b66c5ba0f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -491,6 +491,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
>  	}
>  #if IS_ENABLED(CONFIG_MTK_CMDQ)
>  	if (mtk_crtc->cmdq_client) {
> +		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
>  		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
>  		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
>  		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);


^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send
@ 2020-02-14  6:48     ` CK Hu
  0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2020-02-14  6:48 UTC (permalink / raw)
  To: Bibby Hsieh
  Cc: drinkcat, srv_heupstream, David Airlie, Daniel Vetter,
	linux-kernel, dri-devel, tfiga, Thierry Reding, linux-mediatek,
	Philipp Zabel, Matthias Brugger, linux-arm-kernel

Hi, Bibby:

On Fri, 2020-02-14 at 12:49 +0800, Bibby Hsieh wrote:
> Mediatek CMDQ driver removed atomic parameter and implementation
> related to atomic. DRM driver need to make sure previous message
> done or be aborted before we send next message.
> 
> If previous message is still waiting for event, it means the
> setting hasn't been updated into display hardware register,
> we can abort the message and send next message to update the
> newest setting into display hardware.
> If previous message already started, we have to wait it until
> transmission has been completed.
> 
> So we flush mbox client before we send new message to controller
> driver.
> 

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> This patch depends on ptach:
> [0/3] Remove atomic_exec
> https://patchwork.kernel.org/cover/11381677/
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 3c53ea22208c..e35b66c5ba0f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -491,6 +491,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
>  	}
>  #if IS_ENABLED(CONFIG_MTK_CMDQ)
>  	if (mtk_crtc->cmdq_client) {
> +		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
>  		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
>  		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
>  		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send
@ 2020-02-14  6:48     ` CK Hu
  0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2020-02-14  6:48 UTC (permalink / raw)
  To: Bibby Hsieh
  Cc: drinkcat, srv_heupstream, David Airlie, Daniel Vetter,
	linux-kernel, dri-devel, tfiga, YT Shen, Thierry Reding,
	linux-mediatek, Philipp Zabel, Matthias Brugger,
	linux-arm-kernel

Hi, Bibby:

On Fri, 2020-02-14 at 12:49 +0800, Bibby Hsieh wrote:
> Mediatek CMDQ driver removed atomic parameter and implementation
> related to atomic. DRM driver need to make sure previous message
> done or be aborted before we send next message.
> 
> If previous message is still waiting for event, it means the
> setting hasn't been updated into display hardware register,
> we can abort the message and send next message to update the
> newest setting into display hardware.
> If previous message already started, we have to wait it until
> transmission has been completed.
> 
> So we flush mbox client before we send new message to controller
> driver.
> 

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> This patch depends on ptach:
> [0/3] Remove atomic_exec
> https://patchwork.kernel.org/cover/11381677/
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 3c53ea22208c..e35b66c5ba0f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -491,6 +491,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
>  	}
>  #if IS_ENABLED(CONFIG_MTK_CMDQ)
>  	if (mtk_crtc->cmdq_client) {
> +		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
>  		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
>  		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
>  		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send
@ 2020-02-14  6:48     ` CK Hu
  0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2020-02-14  6:48 UTC (permalink / raw)
  To: Bibby Hsieh
  Cc: drinkcat, srv_heupstream, David Airlie, Daniel Vetter,
	linux-kernel, dri-devel, tfiga, Thierry Reding, linux-mediatek,
	Matthias Brugger, linux-arm-kernel

Hi, Bibby:

On Fri, 2020-02-14 at 12:49 +0800, Bibby Hsieh wrote:
> Mediatek CMDQ driver removed atomic parameter and implementation
> related to atomic. DRM driver need to make sure previous message
> done or be aborted before we send next message.
> 
> If previous message is still waiting for event, it means the
> setting hasn't been updated into display hardware register,
> we can abort the message and send next message to update the
> newest setting into display hardware.
> If previous message already started, we have to wait it until
> transmission has been completed.
> 
> So we flush mbox client before we send new message to controller
> driver.
> 

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> This patch depends on ptach:
> [0/3] Remove atomic_exec
> https://patchwork.kernel.org/cover/11381677/
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 3c53ea22208c..e35b66c5ba0f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -491,6 +491,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
>  	}
>  #if IS_ENABLED(CONFIG_MTK_CMDQ)
>  	if (mtk_crtc->cmdq_client) {
> +		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
>  		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
>  		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
>  		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
  2020-02-14  4:49 ` Bibby Hsieh
  (?)
  (?)
@ 2020-02-14 10:06   ` Matthias Brugger
  -1 siblings, 0 replies; 36+ messages in thread
From: Matthias Brugger @ 2020-02-14 10:06 UTC (permalink / raw)
  To: Bibby Hsieh, David Airlie, Daniel Vetter, dri-devel, linux-mediatek
  Cc: Philipp Zabel, YT Shen, Thierry Reding, CK Hu, linux-arm-kernel,
	tfiga, drinkcat, linux-kernel, srv_heupstream, Yongqiang Niu



On 14/02/2020 05:49, Bibby Hsieh wrote:
> In order to use GCE function, we need add some information
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---

For the next time please provide some context on which patches this are based
on. Bet below the '---' with a link.

For this time, on which patch/series is this based? :)

Thanks,
Matthias

>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index be4428c92f35..8b522b039a37 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -9,6 +9,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/power/mt8183-power.h>
> +#include <dt-bindings/gce/mt8183-gce.h>
>  #include "mt8183-pinfunc.h"
>  
>  / {
> @@ -664,6 +665,9 @@
>  			reg = <0 0x14000000 0 0x1000>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			#clock-cells = <1>;
> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>  		};
>  
>  		ovl0: ovl@14008000 {
> @@ -672,6 +676,7 @@
>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>  		};
>  
>  		ovl_2l0: ovl@14009000 {
> @@ -680,6 +685,7 @@
>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>  		};
>  
>  		ovl_2l1: ovl@1400a000 {
> @@ -688,6 +694,7 @@
>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>  		};
>  
>  		rdma0: rdma@1400b000 {
> @@ -697,6 +704,7 @@
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>  			mediatek,rdma_fifo_size = <5120>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>  		};
>  
>  		rdma1: rdma@1400c000 {
> @@ -706,6 +714,7 @@
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>  			mediatek,rdma_fifo_size = <2048>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>  		};
>  
>  		color0: color@1400e000 {
> @@ -715,6 +724,7 @@
>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>  		};
>  
>  		ccorr0: ccorr@1400f000 {
> @@ -723,6 +733,7 @@
>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>  		};
>  
>  		aal0: aal@14010000 {
> @@ -732,6 +743,7 @@
>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>  		};
>  
>  		gamma0: gamma@14011000 {
> @@ -741,6 +753,7 @@
>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>  		};
>  
>  		dither0: dither@14012000 {
> @@ -749,6 +762,7 @@
>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>  		};
>  
>  		mutex: mutex@14016000 {
> @@ -756,6 +770,8 @@
>  			reg = <0 0x14016000 0 0x1000>;
>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>  		};
>  
>  		smi_common: smi@14019000 {
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-02-14 10:06   ` Matthias Brugger
  0 siblings, 0 replies; 36+ messages in thread
From: Matthias Brugger @ 2020-02-14 10:06 UTC (permalink / raw)
  To: Bibby Hsieh, David Airlie, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, Yongqiang Niu, srv_heupstream, linux-kernel, tfiga,
	CK Hu, Thierry Reding, Philipp Zabel, linux-arm-kernel



On 14/02/2020 05:49, Bibby Hsieh wrote:
> In order to use GCE function, we need add some information
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---

For the next time please provide some context on which patches this are based
on. Bet below the '---' with a link.

For this time, on which patch/series is this based? :)

Thanks,
Matthias

>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index be4428c92f35..8b522b039a37 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -9,6 +9,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/power/mt8183-power.h>
> +#include <dt-bindings/gce/mt8183-gce.h>
>  #include "mt8183-pinfunc.h"
>  
>  / {
> @@ -664,6 +665,9 @@
>  			reg = <0 0x14000000 0 0x1000>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			#clock-cells = <1>;
> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>  		};
>  
>  		ovl0: ovl@14008000 {
> @@ -672,6 +676,7 @@
>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>  		};
>  
>  		ovl_2l0: ovl@14009000 {
> @@ -680,6 +685,7 @@
>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>  		};
>  
>  		ovl_2l1: ovl@1400a000 {
> @@ -688,6 +694,7 @@
>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>  		};
>  
>  		rdma0: rdma@1400b000 {
> @@ -697,6 +704,7 @@
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>  			mediatek,rdma_fifo_size = <5120>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>  		};
>  
>  		rdma1: rdma@1400c000 {
> @@ -706,6 +714,7 @@
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>  			mediatek,rdma_fifo_size = <2048>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>  		};
>  
>  		color0: color@1400e000 {
> @@ -715,6 +724,7 @@
>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>  		};
>  
>  		ccorr0: ccorr@1400f000 {
> @@ -723,6 +733,7 @@
>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>  		};
>  
>  		aal0: aal@14010000 {
> @@ -732,6 +743,7 @@
>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>  		};
>  
>  		gamma0: gamma@14011000 {
> @@ -741,6 +753,7 @@
>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>  		};
>  
>  		dither0: dither@14012000 {
> @@ -749,6 +762,7 @@
>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>  		};
>  
>  		mutex: mutex@14016000 {
> @@ -756,6 +770,8 @@
>  			reg = <0 0x14016000 0 0x1000>;
>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>  		};
>  
>  		smi_common: smi@14019000 {
> 

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-02-14 10:06   ` Matthias Brugger
  0 siblings, 0 replies; 36+ messages in thread
From: Matthias Brugger @ 2020-02-14 10:06 UTC (permalink / raw)
  To: Bibby Hsieh, David Airlie, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, Yongqiang Niu, srv_heupstream, linux-kernel, tfiga,
	CK Hu, Thierry Reding, Philipp Zabel, YT Shen, linux-arm-kernel



On 14/02/2020 05:49, Bibby Hsieh wrote:
> In order to use GCE function, we need add some information
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---

For the next time please provide some context on which patches this are based
on. Bet below the '---' with a link.

For this time, on which patch/series is this based? :)

Thanks,
Matthias

>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index be4428c92f35..8b522b039a37 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -9,6 +9,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/power/mt8183-power.h>
> +#include <dt-bindings/gce/mt8183-gce.h>
>  #include "mt8183-pinfunc.h"
>  
>  / {
> @@ -664,6 +665,9 @@
>  			reg = <0 0x14000000 0 0x1000>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			#clock-cells = <1>;
> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>  		};
>  
>  		ovl0: ovl@14008000 {
> @@ -672,6 +676,7 @@
>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>  		};
>  
>  		ovl_2l0: ovl@14009000 {
> @@ -680,6 +685,7 @@
>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>  		};
>  
>  		ovl_2l1: ovl@1400a000 {
> @@ -688,6 +694,7 @@
>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>  		};
>  
>  		rdma0: rdma@1400b000 {
> @@ -697,6 +704,7 @@
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>  			mediatek,rdma_fifo_size = <5120>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>  		};
>  
>  		rdma1: rdma@1400c000 {
> @@ -706,6 +714,7 @@
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>  			mediatek,rdma_fifo_size = <2048>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>  		};
>  
>  		color0: color@1400e000 {
> @@ -715,6 +724,7 @@
>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>  		};
>  
>  		ccorr0: ccorr@1400f000 {
> @@ -723,6 +733,7 @@
>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>  		};
>  
>  		aal0: aal@14010000 {
> @@ -732,6 +743,7 @@
>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>  		};
>  
>  		gamma0: gamma@14011000 {
> @@ -741,6 +753,7 @@
>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>  		};
>  
>  		dither0: dither@14012000 {
> @@ -749,6 +762,7 @@
>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>  		};
>  
>  		mutex: mutex@14016000 {
> @@ -756,6 +770,8 @@
>  			reg = <0 0x14016000 0 0x1000>;
>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>  		};
>  
>  		smi_common: smi@14019000 {
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-02-14 10:06   ` Matthias Brugger
  0 siblings, 0 replies; 36+ messages in thread
From: Matthias Brugger @ 2020-02-14 10:06 UTC (permalink / raw)
  To: Bibby Hsieh, David Airlie, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, Yongqiang Niu, srv_heupstream, linux-kernel, tfiga,
	Thierry Reding, linux-arm-kernel



On 14/02/2020 05:49, Bibby Hsieh wrote:
> In order to use GCE function, we need add some information
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> 
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---

For the next time please provide some context on which patches this are based
on. Bet below the '---' with a link.

For this time, on which patch/series is this based? :)

Thanks,
Matthias

>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index be4428c92f35..8b522b039a37 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -9,6 +9,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/power/mt8183-power.h>
> +#include <dt-bindings/gce/mt8183-gce.h>
>  #include "mt8183-pinfunc.h"
>  
>  / {
> @@ -664,6 +665,9 @@
>  			reg = <0 0x14000000 0 0x1000>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			#clock-cells = <1>;
> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>  		};
>  
>  		ovl0: ovl@14008000 {
> @@ -672,6 +676,7 @@
>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>  		};
>  
>  		ovl_2l0: ovl@14009000 {
> @@ -680,6 +685,7 @@
>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>  		};
>  
>  		ovl_2l1: ovl@1400a000 {
> @@ -688,6 +694,7 @@
>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>  		};
>  
>  		rdma0: rdma@1400b000 {
> @@ -697,6 +704,7 @@
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>  			mediatek,rdma_fifo_size = <5120>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>  		};
>  
>  		rdma1: rdma@1400c000 {
> @@ -706,6 +714,7 @@
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>  			mediatek,rdma_fifo_size = <2048>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>  		};
>  
>  		color0: color@1400e000 {
> @@ -715,6 +724,7 @@
>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>  		};
>  
>  		ccorr0: ccorr@1400f000 {
> @@ -723,6 +733,7 @@
>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>  		};
>  
>  		aal0: aal@14010000 {
> @@ -732,6 +743,7 @@
>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>  		};
>  
>  		gamma0: gamma@14011000 {
> @@ -741,6 +753,7 @@
>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>  		};
>  
>  		dither0: dither@14012000 {
> @@ -749,6 +762,7 @@
>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>  		};
>  
>  		mutex: mutex@14016000 {
> @@ -756,6 +770,8 @@
>  			reg = <0 0x14016000 0 0x1000>;
>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>  		};
>  
>  		smi_common: smi@14019000 {
> 
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send
  2020-02-14  6:48     ` CK Hu
  (?)
  (?)
@ 2020-02-18  8:22       ` CK Hu
  -1 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2020-02-18  8:22 UTC (permalink / raw)
  To: Bibby Hsieh
  Cc: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel,
	linux-mediatek, Philipp Zabel, YT Shen, Thierry Reding,
	linux-arm-kernel, tfiga, drinkcat, linux-kernel, srv_heupstream

Hi, Bibby:

On Fri, 2020-02-14 at 14:48 +0800, CK Hu wrote:
> Hi, Bibby:
> 
> On Fri, 2020-02-14 at 12:49 +0800, Bibby Hsieh wrote:
> > Mediatek CMDQ driver removed atomic parameter and implementation
> > related to atomic. DRM driver need to make sure previous message
> > done or be aborted before we send next message.
> > 
> > If previous message is still waiting for event, it means the
> > setting hasn't been updated into display hardware register,
> > we can abort the message and send next message to update the
> > newest setting into display hardware.
> > If previous message already started, we have to wait it until
> > transmission has been completed.
> > 
> > So we flush mbox client before we send new message to controller
> > driver.
> > 
> 
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> 
> > This patch depends on ptach:
> > [0/3] Remove atomic_exec
> > https://patchwork.kernel.org/cover/11381677/
> > 

This patch does not depend on any patch, so applied to
mediatek-drm-fixes-5.6 [1], thanks.

[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-fixes-5.6

Regards,
CK

> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index 3c53ea22208c..e35b66c5ba0f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -491,6 +491,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
> >  	}
> >  #if IS_ENABLED(CONFIG_MTK_CMDQ)
> >  	if (mtk_crtc->cmdq_client) {
> > +		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
> >  		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
> >  		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
> >  		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
> 


^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send
@ 2020-02-18  8:22       ` CK Hu
  0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2020-02-18  8:22 UTC (permalink / raw)
  To: Bibby Hsieh
  Cc: drinkcat, srv_heupstream, David Airlie, Daniel Vetter,
	linux-kernel, dri-devel, tfiga, Thierry Reding, linux-mediatek,
	Philipp Zabel, Matthias Brugger, linux-arm-kernel

Hi, Bibby:

On Fri, 2020-02-14 at 14:48 +0800, CK Hu wrote:
> Hi, Bibby:
> 
> On Fri, 2020-02-14 at 12:49 +0800, Bibby Hsieh wrote:
> > Mediatek CMDQ driver removed atomic parameter and implementation
> > related to atomic. DRM driver need to make sure previous message
> > done or be aborted before we send next message.
> > 
> > If previous message is still waiting for event, it means the
> > setting hasn't been updated into display hardware register,
> > we can abort the message and send next message to update the
> > newest setting into display hardware.
> > If previous message already started, we have to wait it until
> > transmission has been completed.
> > 
> > So we flush mbox client before we send new message to controller
> > driver.
> > 
> 
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> 
> > This patch depends on ptach:
> > [0/3] Remove atomic_exec
> > https://patchwork.kernel.org/cover/11381677/
> > 

This patch does not depend on any patch, so applied to
mediatek-drm-fixes-5.6 [1], thanks.

[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-fixes-5.6

Regards,
CK

> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index 3c53ea22208c..e35b66c5ba0f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -491,6 +491,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
> >  	}
> >  #if IS_ENABLED(CONFIG_MTK_CMDQ)
> >  	if (mtk_crtc->cmdq_client) {
> > +		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
> >  		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
> >  		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
> >  		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
> 

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send
@ 2020-02-18  8:22       ` CK Hu
  0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2020-02-18  8:22 UTC (permalink / raw)
  To: Bibby Hsieh
  Cc: drinkcat, srv_heupstream, David Airlie, Daniel Vetter,
	linux-kernel, dri-devel, tfiga, YT Shen, Thierry Reding,
	linux-mediatek, Philipp Zabel, Matthias Brugger,
	linux-arm-kernel

Hi, Bibby:

On Fri, 2020-02-14 at 14:48 +0800, CK Hu wrote:
> Hi, Bibby:
> 
> On Fri, 2020-02-14 at 12:49 +0800, Bibby Hsieh wrote:
> > Mediatek CMDQ driver removed atomic parameter and implementation
> > related to atomic. DRM driver need to make sure previous message
> > done or be aborted before we send next message.
> > 
> > If previous message is still waiting for event, it means the
> > setting hasn't been updated into display hardware register,
> > we can abort the message and send next message to update the
> > newest setting into display hardware.
> > If previous message already started, we have to wait it until
> > transmission has been completed.
> > 
> > So we flush mbox client before we send new message to controller
> > driver.
> > 
> 
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> 
> > This patch depends on ptach:
> > [0/3] Remove atomic_exec
> > https://patchwork.kernel.org/cover/11381677/
> > 

This patch does not depend on any patch, so applied to
mediatek-drm-fixes-5.6 [1], thanks.

[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-fixes-5.6

Regards,
CK

> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index 3c53ea22208c..e35b66c5ba0f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -491,6 +491,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
> >  	}
> >  #if IS_ENABLED(CONFIG_MTK_CMDQ)
> >  	if (mtk_crtc->cmdq_client) {
> > +		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
> >  		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
> >  		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
> >  		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send
@ 2020-02-18  8:22       ` CK Hu
  0 siblings, 0 replies; 36+ messages in thread
From: CK Hu @ 2020-02-18  8:22 UTC (permalink / raw)
  To: Bibby Hsieh
  Cc: drinkcat, srv_heupstream, David Airlie, Daniel Vetter,
	linux-kernel, dri-devel, tfiga, Thierry Reding, linux-mediatek,
	Matthias Brugger, linux-arm-kernel

Hi, Bibby:

On Fri, 2020-02-14 at 14:48 +0800, CK Hu wrote:
> Hi, Bibby:
> 
> On Fri, 2020-02-14 at 12:49 +0800, Bibby Hsieh wrote:
> > Mediatek CMDQ driver removed atomic parameter and implementation
> > related to atomic. DRM driver need to make sure previous message
> > done or be aborted before we send next message.
> > 
> > If previous message is still waiting for event, it means the
> > setting hasn't been updated into display hardware register,
> > we can abort the message and send next message to update the
> > newest setting into display hardware.
> > If previous message already started, we have to wait it until
> > transmission has been completed.
> > 
> > So we flush mbox client before we send new message to controller
> > driver.
> > 
> 
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> 
> > This patch depends on ptach:
> > [0/3] Remove atomic_exec
> > https://patchwork.kernel.org/cover/11381677/
> > 

This patch does not depend on any patch, so applied to
mediatek-drm-fixes-5.6 [1], thanks.

[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-fixes-5.6

Regards,
CK

> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index 3c53ea22208c..e35b66c5ba0f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -491,6 +491,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
> >  	}
> >  #if IS_ENABLED(CONFIG_MTK_CMDQ)
> >  	if (mtk_crtc->cmdq_client) {
> > +		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
> >  		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
> >  		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
> >  		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
> 

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
  2020-02-14 10:06   ` Matthias Brugger
  (?)
  (?)
@ 2020-05-21 10:10     ` Matthias Brugger
  -1 siblings, 0 replies; 36+ messages in thread
From: Matthias Brugger @ 2020-05-21 10:10 UTC (permalink / raw)
  To: Bibby Hsieh, David Airlie, Daniel Vetter, dri-devel, linux-mediatek
  Cc: Philipp Zabel, YT Shen, Thierry Reding, CK Hu, linux-arm-kernel,
	tfiga, drinkcat, linux-kernel, srv_heupstream, Yongqiang Niu

On 14/02/2020 11:06, Matthias Brugger wrote:
> 
> 
> On 14/02/2020 05:49, Bibby Hsieh wrote:
>> In order to use GCE function, we need add some information
>> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>>
>> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>> ---
> 
> For the next time please provide some context on which patches this are based
> on. Bet below the '---' with a link.
> 
> For this time, on which patch/series is this based? :)

Bibby can you please help and rebase the patch against my for-next branch [1].
I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
late, but we could try :)

Thanks!
Matthias

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next

> 
> Thanks,
> Matthias
> 
>>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> index be4428c92f35..8b522b039a37 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> @@ -9,6 +9,7 @@
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>  #include <dt-bindings/interrupt-controller/irq.h>
>>  #include <dt-bindings/power/mt8183-power.h>
>> +#include <dt-bindings/gce/mt8183-gce.h>
>>  #include "mt8183-pinfunc.h"
>>  
>>  / {
>> @@ -664,6 +665,9 @@
>>  			reg = <0 0x14000000 0 0x1000>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			#clock-cells = <1>;
>> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
>> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>>  		};
>>  
>>  		ovl0: ovl@14008000 {
>> @@ -672,6 +676,7 @@
>>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>>  		};
>>  
>>  		ovl_2l0: ovl@14009000 {
>> @@ -680,6 +685,7 @@
>>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>>  		};
>>  
>>  		ovl_2l1: ovl@1400a000 {
>> @@ -688,6 +694,7 @@
>>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>>  		};
>>  
>>  		rdma0: rdma@1400b000 {
>> @@ -697,6 +704,7 @@
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>>  			mediatek,rdma_fifo_size = <5120>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>>  		};
>>  
>>  		rdma1: rdma@1400c000 {
>> @@ -706,6 +714,7 @@
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>>  			mediatek,rdma_fifo_size = <2048>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>>  		};
>>  
>>  		color0: color@1400e000 {
>> @@ -715,6 +724,7 @@
>>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>>  		};
>>  
>>  		ccorr0: ccorr@1400f000 {
>> @@ -723,6 +733,7 @@
>>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>>  		};
>>  
>>  		aal0: aal@14010000 {
>> @@ -732,6 +743,7 @@
>>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>>  		};
>>  
>>  		gamma0: gamma@14011000 {
>> @@ -741,6 +753,7 @@
>>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>>  		};
>>  
>>  		dither0: dither@14012000 {
>> @@ -749,6 +762,7 @@
>>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>>  		};
>>  
>>  		mutex: mutex@14016000 {
>> @@ -756,6 +770,8 @@
>>  			reg = <0 0x14016000 0 0x1000>;
>>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
>> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>>  		};
>>  
>>  		smi_common: smi@14019000 {
>>


^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-05-21 10:10     ` Matthias Brugger
  0 siblings, 0 replies; 36+ messages in thread
From: Matthias Brugger @ 2020-05-21 10:10 UTC (permalink / raw)
  To: Bibby Hsieh, David Airlie, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, Yongqiang Niu, srv_heupstream, linux-kernel, tfiga,
	CK Hu, Thierry Reding, Philipp Zabel, linux-arm-kernel

On 14/02/2020 11:06, Matthias Brugger wrote:
> 
> 
> On 14/02/2020 05:49, Bibby Hsieh wrote:
>> In order to use GCE function, we need add some information
>> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>>
>> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>> ---
> 
> For the next time please provide some context on which patches this are based
> on. Bet below the '---' with a link.
> 
> For this time, on which patch/series is this based? :)

Bibby can you please help and rebase the patch against my for-next branch [1].
I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
late, but we could try :)

Thanks!
Matthias

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next

> 
> Thanks,
> Matthias
> 
>>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> index be4428c92f35..8b522b039a37 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> @@ -9,6 +9,7 @@
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>  #include <dt-bindings/interrupt-controller/irq.h>
>>  #include <dt-bindings/power/mt8183-power.h>
>> +#include <dt-bindings/gce/mt8183-gce.h>
>>  #include "mt8183-pinfunc.h"
>>  
>>  / {
>> @@ -664,6 +665,9 @@
>>  			reg = <0 0x14000000 0 0x1000>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			#clock-cells = <1>;
>> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
>> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>>  		};
>>  
>>  		ovl0: ovl@14008000 {
>> @@ -672,6 +676,7 @@
>>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>>  		};
>>  
>>  		ovl_2l0: ovl@14009000 {
>> @@ -680,6 +685,7 @@
>>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>>  		};
>>  
>>  		ovl_2l1: ovl@1400a000 {
>> @@ -688,6 +694,7 @@
>>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>>  		};
>>  
>>  		rdma0: rdma@1400b000 {
>> @@ -697,6 +704,7 @@
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>>  			mediatek,rdma_fifo_size = <5120>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>>  		};
>>  
>>  		rdma1: rdma@1400c000 {
>> @@ -706,6 +714,7 @@
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>>  			mediatek,rdma_fifo_size = <2048>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>>  		};
>>  
>>  		color0: color@1400e000 {
>> @@ -715,6 +724,7 @@
>>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>>  		};
>>  
>>  		ccorr0: ccorr@1400f000 {
>> @@ -723,6 +733,7 @@
>>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>>  		};
>>  
>>  		aal0: aal@14010000 {
>> @@ -732,6 +743,7 @@
>>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>>  		};
>>  
>>  		gamma0: gamma@14011000 {
>> @@ -741,6 +753,7 @@
>>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>>  		};
>>  
>>  		dither0: dither@14012000 {
>> @@ -749,6 +762,7 @@
>>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>>  		};
>>  
>>  		mutex: mutex@14016000 {
>> @@ -756,6 +770,8 @@
>>  			reg = <0 0x14016000 0 0x1000>;
>>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
>> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>>  		};
>>  
>>  		smi_common: smi@14019000 {
>>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-05-21 10:10     ` Matthias Brugger
  0 siblings, 0 replies; 36+ messages in thread
From: Matthias Brugger @ 2020-05-21 10:10 UTC (permalink / raw)
  To: Bibby Hsieh, David Airlie, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, Yongqiang Niu, srv_heupstream, linux-kernel, tfiga,
	CK Hu, Thierry Reding, Philipp Zabel, YT Shen, linux-arm-kernel

On 14/02/2020 11:06, Matthias Brugger wrote:
> 
> 
> On 14/02/2020 05:49, Bibby Hsieh wrote:
>> In order to use GCE function, we need add some information
>> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>>
>> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>> ---
> 
> For the next time please provide some context on which patches this are based
> on. Bet below the '---' with a link.
> 
> For this time, on which patch/series is this based? :)

Bibby can you please help and rebase the patch against my for-next branch [1].
I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
late, but we could try :)

Thanks!
Matthias

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next

> 
> Thanks,
> Matthias
> 
>>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> index be4428c92f35..8b522b039a37 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> @@ -9,6 +9,7 @@
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>  #include <dt-bindings/interrupt-controller/irq.h>
>>  #include <dt-bindings/power/mt8183-power.h>
>> +#include <dt-bindings/gce/mt8183-gce.h>
>>  #include "mt8183-pinfunc.h"
>>  
>>  / {
>> @@ -664,6 +665,9 @@
>>  			reg = <0 0x14000000 0 0x1000>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			#clock-cells = <1>;
>> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
>> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>>  		};
>>  
>>  		ovl0: ovl@14008000 {
>> @@ -672,6 +676,7 @@
>>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>>  		};
>>  
>>  		ovl_2l0: ovl@14009000 {
>> @@ -680,6 +685,7 @@
>>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>>  		};
>>  
>>  		ovl_2l1: ovl@1400a000 {
>> @@ -688,6 +694,7 @@
>>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>>  		};
>>  
>>  		rdma0: rdma@1400b000 {
>> @@ -697,6 +704,7 @@
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>>  			mediatek,rdma_fifo_size = <5120>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>>  		};
>>  
>>  		rdma1: rdma@1400c000 {
>> @@ -706,6 +714,7 @@
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>>  			mediatek,rdma_fifo_size = <2048>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>>  		};
>>  
>>  		color0: color@1400e000 {
>> @@ -715,6 +724,7 @@
>>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>>  		};
>>  
>>  		ccorr0: ccorr@1400f000 {
>> @@ -723,6 +733,7 @@
>>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>>  		};
>>  
>>  		aal0: aal@14010000 {
>> @@ -732,6 +743,7 @@
>>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>>  		};
>>  
>>  		gamma0: gamma@14011000 {
>> @@ -741,6 +753,7 @@
>>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>>  		};
>>  
>>  		dither0: dither@14012000 {
>> @@ -749,6 +762,7 @@
>>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>>  		};
>>  
>>  		mutex: mutex@14016000 {
>> @@ -756,6 +770,8 @@
>>  			reg = <0 0x14016000 0 0x1000>;
>>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
>> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>>  		};
>>  
>>  		smi_common: smi@14019000 {
>>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-05-21 10:10     ` Matthias Brugger
  0 siblings, 0 replies; 36+ messages in thread
From: Matthias Brugger @ 2020-05-21 10:10 UTC (permalink / raw)
  To: Bibby Hsieh, David Airlie, Daniel Vetter, dri-devel, linux-mediatek
  Cc: drinkcat, Yongqiang Niu, srv_heupstream, linux-kernel, tfiga,
	Thierry Reding, linux-arm-kernel

On 14/02/2020 11:06, Matthias Brugger wrote:
> 
> 
> On 14/02/2020 05:49, Bibby Hsieh wrote:
>> In order to use GCE function, we need add some information
>> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>>
>> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>> ---
> 
> For the next time please provide some context on which patches this are based
> on. Bet below the '---' with a link.
> 
> For this time, on which patch/series is this based? :)

Bibby can you please help and rebase the patch against my for-next branch [1].
I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
late, but we could try :)

Thanks!
Matthias

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next

> 
> Thanks,
> Matthias
> 
>>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> index be4428c92f35..8b522b039a37 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> @@ -9,6 +9,7 @@
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>  #include <dt-bindings/interrupt-controller/irq.h>
>>  #include <dt-bindings/power/mt8183-power.h>
>> +#include <dt-bindings/gce/mt8183-gce.h>
>>  #include "mt8183-pinfunc.h"
>>  
>>  / {
>> @@ -664,6 +665,9 @@
>>  			reg = <0 0x14000000 0 0x1000>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			#clock-cells = <1>;
>> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
>> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>>  		};
>>  
>>  		ovl0: ovl@14008000 {
>> @@ -672,6 +676,7 @@
>>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>>  		};
>>  
>>  		ovl_2l0: ovl@14009000 {
>> @@ -680,6 +685,7 @@
>>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>>  		};
>>  
>>  		ovl_2l1: ovl@1400a000 {
>> @@ -688,6 +694,7 @@
>>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>>  		};
>>  
>>  		rdma0: rdma@1400b000 {
>> @@ -697,6 +704,7 @@
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>>  			mediatek,rdma_fifo_size = <5120>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>>  		};
>>  
>>  		rdma1: rdma@1400c000 {
>> @@ -706,6 +714,7 @@
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>>  			mediatek,rdma_fifo_size = <2048>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>>  		};
>>  
>>  		color0: color@1400e000 {
>> @@ -715,6 +724,7 @@
>>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>>  		};
>>  
>>  		ccorr0: ccorr@1400f000 {
>> @@ -723,6 +733,7 @@
>>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>>  		};
>>  
>>  		aal0: aal@14010000 {
>> @@ -732,6 +743,7 @@
>>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>>  		};
>>  
>>  		gamma0: gamma@14011000 {
>> @@ -741,6 +753,7 @@
>>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>>  		};
>>  
>>  		dither0: dither@14012000 {
>> @@ -749,6 +762,7 @@
>>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>>  		};
>>  
>>  		mutex: mutex@14016000 {
>> @@ -756,6 +770,8 @@
>>  			reg = <0 0x14016000 0 0x1000>;
>>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
>> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>>  		};
>>  
>>  		smi_common: smi@14019000 {
>>

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
  2020-05-21 10:10     ` Matthias Brugger
  (?)
  (?)
@ 2020-05-21 10:47       ` Bibby Hsieh
  -1 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-05-21 10:47 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: David Airlie, Daniel Vetter, dri-devel, linux-mediatek,
	Philipp Zabel, YT Shen, Thierry Reding, CK Hu, linux-arm-kernel,
	tfiga, drinkcat, linux-kernel, srv_heupstream, Yongqiang Niu

On Thu, 2020-05-21 at 12:10 +0200, Matthias Brugger wrote:
> On 14/02/2020 11:06, Matthias Brugger wrote:
> > 
> > 
> > On 14/02/2020 05:49, Bibby Hsieh wrote:
> >> In order to use GCE function, we need add some information
> >> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> >>
> >> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> >> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> >> ---
> > 
> > For the next time please provide some context on which patches this are based
> > on. Bet below the '---' with a link.
> > 
> > For this time, on which patch/series is this based? :)
> 
> Bibby can you please help and rebase the patch against my for-next branch [1].
> I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
> late, but we could try :)

Hi, Matthias,

NP, but this patch[1] is depends on another patch [2].
Should I rebase them together into your for-next branch?

[1] https://patchwork.kernel.org/patch/11385863/
[2] https://patchwork.kernel.org/patch/11316277/

Bibby

> 
> Thanks!
> Matthias
> 
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
> 
> > 
> > Thanks,
> > Matthias
> > 
> >>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
> >>  1 file changed, 16 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> index be4428c92f35..8b522b039a37 100644
> >> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> @@ -9,6 +9,7 @@
> >>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>  #include <dt-bindings/interrupt-controller/irq.h>
> >>  #include <dt-bindings/power/mt8183-power.h>
> >> +#include <dt-bindings/gce/mt8183-gce.h>
> >>  #include "mt8183-pinfunc.h"
> >>  
> >>  / {
> >> @@ -664,6 +665,9 @@
> >>  			reg = <0 0x14000000 0 0x1000>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			#clock-cells = <1>;
> >> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> >> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> >>  		};
> >>  
> >>  		ovl0: ovl@14008000 {
> >> @@ -672,6 +676,7 @@
> >>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
> >>  		};
> >>  
> >>  		ovl_2l0: ovl@14009000 {
> >> @@ -680,6 +685,7 @@
> >>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> >>  		};
> >>  
> >>  		ovl_2l1: ovl@1400a000 {
> >> @@ -688,6 +694,7 @@
> >>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> >>  		};
> >>  
> >>  		rdma0: rdma@1400b000 {
> >> @@ -697,6 +704,7 @@
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> >>  			mediatek,rdma_fifo_size = <5120>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> >>  		};
> >>  
> >>  		rdma1: rdma@1400c000 {
> >> @@ -706,6 +714,7 @@
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> >>  			mediatek,rdma_fifo_size = <2048>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> >>  		};
> >>  
> >>  		color0: color@1400e000 {
> >> @@ -715,6 +724,7 @@
> >>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> >>  		};
> >>  
> >>  		ccorr0: ccorr@1400f000 {
> >> @@ -723,6 +733,7 @@
> >>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> >>  		};
> >>  
> >>  		aal0: aal@14010000 {
> >> @@ -732,6 +743,7 @@
> >>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> >>  		};
> >>  
> >>  		gamma0: gamma@14011000 {
> >> @@ -741,6 +753,7 @@
> >>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> >>  		};
> >>  
> >>  		dither0: dither@14012000 {
> >> @@ -749,6 +762,7 @@
> >>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> >>  		};
> >>  
> >>  		mutex: mutex@14016000 {
> >> @@ -756,6 +770,8 @@
> >>  			reg = <0 0x14016000 0 0x1000>;
> >>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> >> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
> >>  		};
> >>  
> >>  		smi_common: smi@14019000 {
> >>
> 


^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-05-21 10:47       ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-05-21 10:47 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: drinkcat, Yongqiang Niu, srv_heupstream, David Airlie,
	Daniel Vetter, linux-kernel, dri-devel, tfiga, CK Hu,
	Thierry Reding, linux-mediatek, Philipp Zabel, linux-arm-kernel

On Thu, 2020-05-21 at 12:10 +0200, Matthias Brugger wrote:
> On 14/02/2020 11:06, Matthias Brugger wrote:
> > 
> > 
> > On 14/02/2020 05:49, Bibby Hsieh wrote:
> >> In order to use GCE function, we need add some information
> >> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> >>
> >> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> >> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> >> ---
> > 
> > For the next time please provide some context on which patches this are based
> > on. Bet below the '---' with a link.
> > 
> > For this time, on which patch/series is this based? :)
> 
> Bibby can you please help and rebase the patch against my for-next branch [1].
> I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
> late, but we could try :)

Hi, Matthias,

NP, but this patch[1] is depends on another patch [2].
Should I rebase them together into your for-next branch?

[1] https://patchwork.kernel.org/patch/11385863/
[2] https://patchwork.kernel.org/patch/11316277/

Bibby

> 
> Thanks!
> Matthias
> 
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
> 
> > 
> > Thanks,
> > Matthias
> > 
> >>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
> >>  1 file changed, 16 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> index be4428c92f35..8b522b039a37 100644
> >> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> @@ -9,6 +9,7 @@
> >>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>  #include <dt-bindings/interrupt-controller/irq.h>
> >>  #include <dt-bindings/power/mt8183-power.h>
> >> +#include <dt-bindings/gce/mt8183-gce.h>
> >>  #include "mt8183-pinfunc.h"
> >>  
> >>  / {
> >> @@ -664,6 +665,9 @@
> >>  			reg = <0 0x14000000 0 0x1000>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			#clock-cells = <1>;
> >> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> >> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> >>  		};
> >>  
> >>  		ovl0: ovl@14008000 {
> >> @@ -672,6 +676,7 @@
> >>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
> >>  		};
> >>  
> >>  		ovl_2l0: ovl@14009000 {
> >> @@ -680,6 +685,7 @@
> >>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> >>  		};
> >>  
> >>  		ovl_2l1: ovl@1400a000 {
> >> @@ -688,6 +694,7 @@
> >>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> >>  		};
> >>  
> >>  		rdma0: rdma@1400b000 {
> >> @@ -697,6 +704,7 @@
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> >>  			mediatek,rdma_fifo_size = <5120>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> >>  		};
> >>  
> >>  		rdma1: rdma@1400c000 {
> >> @@ -706,6 +714,7 @@
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> >>  			mediatek,rdma_fifo_size = <2048>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> >>  		};
> >>  
> >>  		color0: color@1400e000 {
> >> @@ -715,6 +724,7 @@
> >>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> >>  		};
> >>  
> >>  		ccorr0: ccorr@1400f000 {
> >> @@ -723,6 +733,7 @@
> >>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> >>  		};
> >>  
> >>  		aal0: aal@14010000 {
> >> @@ -732,6 +743,7 @@
> >>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> >>  		};
> >>  
> >>  		gamma0: gamma@14011000 {
> >> @@ -741,6 +753,7 @@
> >>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> >>  		};
> >>  
> >>  		dither0: dither@14012000 {
> >> @@ -749,6 +762,7 @@
> >>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> >>  		};
> >>  
> >>  		mutex: mutex@14016000 {
> >> @@ -756,6 +770,8 @@
> >>  			reg = <0 0x14016000 0 0x1000>;
> >>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> >> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
> >>  		};
> >>  
> >>  		smi_common: smi@14019000 {
> >>
> 

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-05-21 10:47       ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-05-21 10:47 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: drinkcat, Yongqiang Niu, srv_heupstream, David Airlie,
	Daniel Vetter, linux-kernel, dri-devel, tfiga, CK Hu,
	Thierry Reding, linux-mediatek, Philipp Zabel, YT Shen,
	linux-arm-kernel

On Thu, 2020-05-21 at 12:10 +0200, Matthias Brugger wrote:
> On 14/02/2020 11:06, Matthias Brugger wrote:
> > 
> > 
> > On 14/02/2020 05:49, Bibby Hsieh wrote:
> >> In order to use GCE function, we need add some information
> >> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> >>
> >> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> >> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> >> ---
> > 
> > For the next time please provide some context on which patches this are based
> > on. Bet below the '---' with a link.
> > 
> > For this time, on which patch/series is this based? :)
> 
> Bibby can you please help and rebase the patch against my for-next branch [1].
> I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
> late, but we could try :)

Hi, Matthias,

NP, but this patch[1] is depends on another patch [2].
Should I rebase them together into your for-next branch?

[1] https://patchwork.kernel.org/patch/11385863/
[2] https://patchwork.kernel.org/patch/11316277/

Bibby

> 
> Thanks!
> Matthias
> 
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
> 
> > 
> > Thanks,
> > Matthias
> > 
> >>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
> >>  1 file changed, 16 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> index be4428c92f35..8b522b039a37 100644
> >> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> @@ -9,6 +9,7 @@
> >>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>  #include <dt-bindings/interrupt-controller/irq.h>
> >>  #include <dt-bindings/power/mt8183-power.h>
> >> +#include <dt-bindings/gce/mt8183-gce.h>
> >>  #include "mt8183-pinfunc.h"
> >>  
> >>  / {
> >> @@ -664,6 +665,9 @@
> >>  			reg = <0 0x14000000 0 0x1000>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			#clock-cells = <1>;
> >> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> >> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> >>  		};
> >>  
> >>  		ovl0: ovl@14008000 {
> >> @@ -672,6 +676,7 @@
> >>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
> >>  		};
> >>  
> >>  		ovl_2l0: ovl@14009000 {
> >> @@ -680,6 +685,7 @@
> >>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> >>  		};
> >>  
> >>  		ovl_2l1: ovl@1400a000 {
> >> @@ -688,6 +694,7 @@
> >>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> >>  		};
> >>  
> >>  		rdma0: rdma@1400b000 {
> >> @@ -697,6 +704,7 @@
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> >>  			mediatek,rdma_fifo_size = <5120>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> >>  		};
> >>  
> >>  		rdma1: rdma@1400c000 {
> >> @@ -706,6 +714,7 @@
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> >>  			mediatek,rdma_fifo_size = <2048>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> >>  		};
> >>  
> >>  		color0: color@1400e000 {
> >> @@ -715,6 +724,7 @@
> >>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> >>  		};
> >>  
> >>  		ccorr0: ccorr@1400f000 {
> >> @@ -723,6 +733,7 @@
> >>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> >>  		};
> >>  
> >>  		aal0: aal@14010000 {
> >> @@ -732,6 +743,7 @@
> >>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> >>  		};
> >>  
> >>  		gamma0: gamma@14011000 {
> >> @@ -741,6 +753,7 @@
> >>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> >>  		};
> >>  
> >>  		dither0: dither@14012000 {
> >> @@ -749,6 +762,7 @@
> >>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> >>  		};
> >>  
> >>  		mutex: mutex@14016000 {
> >> @@ -756,6 +770,8 @@
> >>  			reg = <0 0x14016000 0 0x1000>;
> >>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> >> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
> >>  		};
> >>  
> >>  		smi_common: smi@14019000 {
> >>
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-05-21 10:47       ` Bibby Hsieh
  0 siblings, 0 replies; 36+ messages in thread
From: Bibby Hsieh @ 2020-05-21 10:47 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: drinkcat, Yongqiang Niu, srv_heupstream, David Airlie,
	Daniel Vetter, linux-kernel, dri-devel, tfiga, Thierry Reding,
	linux-mediatek, linux-arm-kernel

On Thu, 2020-05-21 at 12:10 +0200, Matthias Brugger wrote:
> On 14/02/2020 11:06, Matthias Brugger wrote:
> > 
> > 
> > On 14/02/2020 05:49, Bibby Hsieh wrote:
> >> In order to use GCE function, we need add some information
> >> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> >>
> >> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> >> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> >> ---
> > 
> > For the next time please provide some context on which patches this are based
> > on. Bet below the '---' with a link.
> > 
> > For this time, on which patch/series is this based? :)
> 
> Bibby can you please help and rebase the patch against my for-next branch [1].
> I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
> late, but we could try :)

Hi, Matthias,

NP, but this patch[1] is depends on another patch [2].
Should I rebase them together into your for-next branch?

[1] https://patchwork.kernel.org/patch/11385863/
[2] https://patchwork.kernel.org/patch/11316277/

Bibby

> 
> Thanks!
> Matthias
> 
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
> 
> > 
> > Thanks,
> > Matthias
> > 
> >>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
> >>  1 file changed, 16 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> index be4428c92f35..8b522b039a37 100644
> >> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> @@ -9,6 +9,7 @@
> >>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>  #include <dt-bindings/interrupt-controller/irq.h>
> >>  #include <dt-bindings/power/mt8183-power.h>
> >> +#include <dt-bindings/gce/mt8183-gce.h>
> >>  #include "mt8183-pinfunc.h"
> >>  
> >>  / {
> >> @@ -664,6 +665,9 @@
> >>  			reg = <0 0x14000000 0 0x1000>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			#clock-cells = <1>;
> >> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> >> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> >>  		};
> >>  
> >>  		ovl0: ovl@14008000 {
> >> @@ -672,6 +676,7 @@
> >>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
> >>  		};
> >>  
> >>  		ovl_2l0: ovl@14009000 {
> >> @@ -680,6 +685,7 @@
> >>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> >>  		};
> >>  
> >>  		ovl_2l1: ovl@1400a000 {
> >> @@ -688,6 +694,7 @@
> >>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> >>  		};
> >>  
> >>  		rdma0: rdma@1400b000 {
> >> @@ -697,6 +704,7 @@
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> >>  			mediatek,rdma_fifo_size = <5120>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> >>  		};
> >>  
> >>  		rdma1: rdma@1400c000 {
> >> @@ -706,6 +714,7 @@
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> >>  			mediatek,rdma_fifo_size = <2048>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> >>  		};
> >>  
> >>  		color0: color@1400e000 {
> >> @@ -715,6 +724,7 @@
> >>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> >>  		};
> >>  
> >>  		ccorr0: ccorr@1400f000 {
> >> @@ -723,6 +733,7 @@
> >>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> >>  		};
> >>  
> >>  		aal0: aal@14010000 {
> >> @@ -732,6 +743,7 @@
> >>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> >>  		};
> >>  
> >>  		gamma0: gamma@14011000 {
> >> @@ -741,6 +753,7 @@
> >>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> >>  		};
> >>  
> >>  		dither0: dither@14012000 {
> >> @@ -749,6 +762,7 @@
> >>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> >> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> >>  		};
> >>  
> >>  		mutex: mutex@14016000 {
> >> @@ -756,6 +770,8 @@
> >>  			reg = <0 0x14016000 0 0x1000>;
> >>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
> >>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> >> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> >> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
> >>  		};
> >>  
> >>  		smi_common: smi@14019000 {
> >>
> 

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
  2020-05-21 10:47       ` Bibby Hsieh
  (?)
  (?)
@ 2020-05-21 12:38         ` Matthias Brugger
  -1 siblings, 0 replies; 36+ messages in thread
From: Matthias Brugger @ 2020-05-21 12:38 UTC (permalink / raw)
  To: Bibby Hsieh
  Cc: David Airlie, Daniel Vetter, dri-devel, linux-mediatek,
	Philipp Zabel, YT Shen, Thierry Reding, CK Hu, linux-arm-kernel,
	tfiga, drinkcat, linux-kernel, srv_heupstream, Yongqiang Niu



On 21/05/2020 12:47, Bibby Hsieh wrote:
> On Thu, 2020-05-21 at 12:10 +0200, Matthias Brugger wrote:
>> On 14/02/2020 11:06, Matthias Brugger wrote:
>>>
>>>
>>> On 14/02/2020 05:49, Bibby Hsieh wrote:
>>>> In order to use GCE function, we need add some information
>>>> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>>>>
>>>> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
>>>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>>>> ---
>>>
>>> For the next time please provide some context on which patches this are based
>>> on. Bet below the '---' with a link.
>>>
>>> For this time, on which patch/series is this based? :)
>>
>> Bibby can you please help and rebase the patch against my for-next branch [1].
>> I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
>> late, but we could try :)
> 
> Hi, Matthias,
> 
> NP, but this patch[1] is depends on another patch [2].
> Should I rebase them together into your for-next branch?
> 

I see and [2] one depends on the scpsys driver.
Then maybe better wait until we have the scpsys driver accepted.

Regards,
Matthias


> [1] https://patchwork.kernel.org/patch/11385863/
> [2] https://patchwork.kernel.org/patch/11316277/
> 
> Bibby
> 
>>
>> Thanks!
>> Matthias
>>
>> [1]
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
>>
>>>
>>> Thanks,
>>> Matthias
>>>
>>>>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>>>>  1 file changed, 16 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> index be4428c92f35..8b522b039a37 100644
>>>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> @@ -9,6 +9,7 @@
>>>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>  #include <dt-bindings/interrupt-controller/irq.h>
>>>>  #include <dt-bindings/power/mt8183-power.h>
>>>> +#include <dt-bindings/gce/mt8183-gce.h>
>>>>  #include "mt8183-pinfunc.h"
>>>>  
>>>>  / {
>>>> @@ -664,6 +665,9 @@
>>>>  			reg = <0 0x14000000 0 0x1000>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			#clock-cells = <1>;
>>>> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
>>>> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl0: ovl@14008000 {
>>>> @@ -672,6 +676,7 @@
>>>>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl_2l0: ovl@14009000 {
>>>> @@ -680,6 +685,7 @@
>>>>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl_2l1: ovl@1400a000 {
>>>> @@ -688,6 +694,7 @@
>>>>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>>>>  		};
>>>>  
>>>>  		rdma0: rdma@1400b000 {
>>>> @@ -697,6 +704,7 @@
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>>>>  			mediatek,rdma_fifo_size = <5120>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>>>>  		};
>>>>  
>>>>  		rdma1: rdma@1400c000 {
>>>> @@ -706,6 +714,7 @@
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>>>>  			mediatek,rdma_fifo_size = <2048>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>>>>  		};
>>>>  
>>>>  		color0: color@1400e000 {
>>>> @@ -715,6 +724,7 @@
>>>>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ccorr0: ccorr@1400f000 {
>>>> @@ -723,6 +733,7 @@
>>>>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>>>>  		};
>>>>  
>>>>  		aal0: aal@14010000 {
>>>> @@ -732,6 +743,7 @@
>>>>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>>>>  		};
>>>>  
>>>>  		gamma0: gamma@14011000 {
>>>> @@ -741,6 +753,7 @@
>>>>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>>>>  		};
>>>>  
>>>>  		dither0: dither@14012000 {
>>>> @@ -749,6 +762,7 @@
>>>>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>>>>  		};
>>>>  
>>>>  		mutex: mutex@14016000 {
>>>> @@ -756,6 +770,8 @@
>>>>  			reg = <0 0x14016000 0 0x1000>;
>>>>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
>>>> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>>>>  		};
>>>>  
>>>>  		smi_common: smi@14019000 {
>>>>
>>
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-05-21 12:38         ` Matthias Brugger
  0 siblings, 0 replies; 36+ messages in thread
From: Matthias Brugger @ 2020-05-21 12:38 UTC (permalink / raw)
  To: Bibby Hsieh
  Cc: drinkcat, Yongqiang Niu, srv_heupstream, David Airlie,
	Daniel Vetter, linux-kernel, dri-devel, tfiga, CK Hu,
	Thierry Reding, linux-mediatek, Philipp Zabel, linux-arm-kernel



On 21/05/2020 12:47, Bibby Hsieh wrote:
> On Thu, 2020-05-21 at 12:10 +0200, Matthias Brugger wrote:
>> On 14/02/2020 11:06, Matthias Brugger wrote:
>>>
>>>
>>> On 14/02/2020 05:49, Bibby Hsieh wrote:
>>>> In order to use GCE function, we need add some information
>>>> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>>>>
>>>> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
>>>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>>>> ---
>>>
>>> For the next time please provide some context on which patches this are based
>>> on. Bet below the '---' with a link.
>>>
>>> For this time, on which patch/series is this based? :)
>>
>> Bibby can you please help and rebase the patch against my for-next branch [1].
>> I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
>> late, but we could try :)
> 
> Hi, Matthias,
> 
> NP, but this patch[1] is depends on another patch [2].
> Should I rebase them together into your for-next branch?
> 

I see and [2] one depends on the scpsys driver.
Then maybe better wait until we have the scpsys driver accepted.

Regards,
Matthias


> [1] https://patchwork.kernel.org/patch/11385863/
> [2] https://patchwork.kernel.org/patch/11316277/
> 
> Bibby
> 
>>
>> Thanks!
>> Matthias
>>
>> [1]
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
>>
>>>
>>> Thanks,
>>> Matthias
>>>
>>>>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>>>>  1 file changed, 16 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> index be4428c92f35..8b522b039a37 100644
>>>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> @@ -9,6 +9,7 @@
>>>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>  #include <dt-bindings/interrupt-controller/irq.h>
>>>>  #include <dt-bindings/power/mt8183-power.h>
>>>> +#include <dt-bindings/gce/mt8183-gce.h>
>>>>  #include "mt8183-pinfunc.h"
>>>>  
>>>>  / {
>>>> @@ -664,6 +665,9 @@
>>>>  			reg = <0 0x14000000 0 0x1000>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			#clock-cells = <1>;
>>>> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
>>>> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl0: ovl@14008000 {
>>>> @@ -672,6 +676,7 @@
>>>>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl_2l0: ovl@14009000 {
>>>> @@ -680,6 +685,7 @@
>>>>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl_2l1: ovl@1400a000 {
>>>> @@ -688,6 +694,7 @@
>>>>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>>>>  		};
>>>>  
>>>>  		rdma0: rdma@1400b000 {
>>>> @@ -697,6 +704,7 @@
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>>>>  			mediatek,rdma_fifo_size = <5120>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>>>>  		};
>>>>  
>>>>  		rdma1: rdma@1400c000 {
>>>> @@ -706,6 +714,7 @@
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>>>>  			mediatek,rdma_fifo_size = <2048>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>>>>  		};
>>>>  
>>>>  		color0: color@1400e000 {
>>>> @@ -715,6 +724,7 @@
>>>>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ccorr0: ccorr@1400f000 {
>>>> @@ -723,6 +733,7 @@
>>>>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>>>>  		};
>>>>  
>>>>  		aal0: aal@14010000 {
>>>> @@ -732,6 +743,7 @@
>>>>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>>>>  		};
>>>>  
>>>>  		gamma0: gamma@14011000 {
>>>> @@ -741,6 +753,7 @@
>>>>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>>>>  		};
>>>>  
>>>>  		dither0: dither@14012000 {
>>>> @@ -749,6 +762,7 @@
>>>>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>>>>  		};
>>>>  
>>>>  		mutex: mutex@14016000 {
>>>> @@ -756,6 +770,8 @@
>>>>  			reg = <0 0x14016000 0 0x1000>;
>>>>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
>>>> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>>>>  		};
>>>>  
>>>>  		smi_common: smi@14019000 {
>>>>
>>
> 

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-05-21 12:38         ` Matthias Brugger
  0 siblings, 0 replies; 36+ messages in thread
From: Matthias Brugger @ 2020-05-21 12:38 UTC (permalink / raw)
  To: Bibby Hsieh
  Cc: drinkcat, Yongqiang Niu, srv_heupstream, David Airlie,
	Daniel Vetter, linux-kernel, dri-devel, tfiga, CK Hu,
	Thierry Reding, linux-mediatek, Philipp Zabel, YT Shen,
	linux-arm-kernel



On 21/05/2020 12:47, Bibby Hsieh wrote:
> On Thu, 2020-05-21 at 12:10 +0200, Matthias Brugger wrote:
>> On 14/02/2020 11:06, Matthias Brugger wrote:
>>>
>>>
>>> On 14/02/2020 05:49, Bibby Hsieh wrote:
>>>> In order to use GCE function, we need add some information
>>>> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>>>>
>>>> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
>>>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>>>> ---
>>>
>>> For the next time please provide some context on which patches this are based
>>> on. Bet below the '---' with a link.
>>>
>>> For this time, on which patch/series is this based? :)
>>
>> Bibby can you please help and rebase the patch against my for-next branch [1].
>> I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
>> late, but we could try :)
> 
> Hi, Matthias,
> 
> NP, but this patch[1] is depends on another patch [2].
> Should I rebase them together into your for-next branch?
> 

I see and [2] one depends on the scpsys driver.
Then maybe better wait until we have the scpsys driver accepted.

Regards,
Matthias


> [1] https://patchwork.kernel.org/patch/11385863/
> [2] https://patchwork.kernel.org/patch/11316277/
> 
> Bibby
> 
>>
>> Thanks!
>> Matthias
>>
>> [1]
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
>>
>>>
>>> Thanks,
>>> Matthias
>>>
>>>>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>>>>  1 file changed, 16 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> index be4428c92f35..8b522b039a37 100644
>>>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> @@ -9,6 +9,7 @@
>>>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>  #include <dt-bindings/interrupt-controller/irq.h>
>>>>  #include <dt-bindings/power/mt8183-power.h>
>>>> +#include <dt-bindings/gce/mt8183-gce.h>
>>>>  #include "mt8183-pinfunc.h"
>>>>  
>>>>  / {
>>>> @@ -664,6 +665,9 @@
>>>>  			reg = <0 0x14000000 0 0x1000>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			#clock-cells = <1>;
>>>> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
>>>> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl0: ovl@14008000 {
>>>> @@ -672,6 +676,7 @@
>>>>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl_2l0: ovl@14009000 {
>>>> @@ -680,6 +685,7 @@
>>>>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl_2l1: ovl@1400a000 {
>>>> @@ -688,6 +694,7 @@
>>>>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>>>>  		};
>>>>  
>>>>  		rdma0: rdma@1400b000 {
>>>> @@ -697,6 +704,7 @@
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>>>>  			mediatek,rdma_fifo_size = <5120>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>>>>  		};
>>>>  
>>>>  		rdma1: rdma@1400c000 {
>>>> @@ -706,6 +714,7 @@
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>>>>  			mediatek,rdma_fifo_size = <2048>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>>>>  		};
>>>>  
>>>>  		color0: color@1400e000 {
>>>> @@ -715,6 +724,7 @@
>>>>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ccorr0: ccorr@1400f000 {
>>>> @@ -723,6 +733,7 @@
>>>>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>>>>  		};
>>>>  
>>>>  		aal0: aal@14010000 {
>>>> @@ -732,6 +743,7 @@
>>>>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>>>>  		};
>>>>  
>>>>  		gamma0: gamma@14011000 {
>>>> @@ -741,6 +753,7 @@
>>>>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>>>>  		};
>>>>  
>>>>  		dither0: dither@14012000 {
>>>> @@ -749,6 +762,7 @@
>>>>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>>>>  		};
>>>>  
>>>>  		mutex: mutex@14016000 {
>>>> @@ -756,6 +770,8 @@
>>>>  			reg = <0 0x14016000 0 0x1000>;
>>>>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
>>>> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>>>>  		};
>>>>  
>>>>  		smi_common: smi@14019000 {
>>>>
>>
> 

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^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
@ 2020-05-21 12:38         ` Matthias Brugger
  0 siblings, 0 replies; 36+ messages in thread
From: Matthias Brugger @ 2020-05-21 12:38 UTC (permalink / raw)
  To: Bibby Hsieh
  Cc: drinkcat, Yongqiang Niu, srv_heupstream, David Airlie,
	Daniel Vetter, linux-kernel, dri-devel, tfiga, Thierry Reding,
	linux-mediatek, linux-arm-kernel



On 21/05/2020 12:47, Bibby Hsieh wrote:
> On Thu, 2020-05-21 at 12:10 +0200, Matthias Brugger wrote:
>> On 14/02/2020 11:06, Matthias Brugger wrote:
>>>
>>>
>>> On 14/02/2020 05:49, Bibby Hsieh wrote:
>>>> In order to use GCE function, we need add some information
>>>> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>>>>
>>>> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
>>>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>>>> ---
>>>
>>> For the next time please provide some context on which patches this are based
>>> on. Bet below the '---' with a link.
>>>
>>> For this time, on which patch/series is this based? :)
>>
>> Bibby can you please help and rebase the patch against my for-next branch [1].
>> I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
>> late, but we could try :)
> 
> Hi, Matthias,
> 
> NP, but this patch[1] is depends on another patch [2].
> Should I rebase them together into your for-next branch?
> 

I see and [2] one depends on the scpsys driver.
Then maybe better wait until we have the scpsys driver accepted.

Regards,
Matthias


> [1] https://patchwork.kernel.org/patch/11385863/
> [2] https://patchwork.kernel.org/patch/11316277/
> 
> Bibby
> 
>>
>> Thanks!
>> Matthias
>>
>> [1]
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
>>
>>>
>>> Thanks,
>>> Matthias
>>>
>>>>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
>>>>  1 file changed, 16 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> index be4428c92f35..8b522b039a37 100644
>>>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>> @@ -9,6 +9,7 @@
>>>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>  #include <dt-bindings/interrupt-controller/irq.h>
>>>>  #include <dt-bindings/power/mt8183-power.h>
>>>> +#include <dt-bindings/gce/mt8183-gce.h>
>>>>  #include "mt8183-pinfunc.h"
>>>>  
>>>>  / {
>>>> @@ -664,6 +665,9 @@
>>>>  			reg = <0 0x14000000 0 0x1000>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			#clock-cells = <1>;
>>>> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
>>>> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl0: ovl@14008000 {
>>>> @@ -672,6 +676,7 @@
>>>>  			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl_2l0: ovl@14009000 {
>>>> @@ -680,6 +685,7 @@
>>>>  			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ovl_2l1: ovl@1400a000 {
>>>> @@ -688,6 +694,7 @@
>>>>  			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>>>>  		};
>>>>  
>>>>  		rdma0: rdma@1400b000 {
>>>> @@ -697,6 +704,7 @@
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>>>>  			mediatek,rdma_fifo_size = <5120>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>>>>  		};
>>>>  
>>>>  		rdma1: rdma@1400c000 {
>>>> @@ -706,6 +714,7 @@
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
>>>>  			mediatek,rdma_fifo_size = <2048>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>>>>  		};
>>>>  
>>>>  		color0: color@1400e000 {
>>>> @@ -715,6 +724,7 @@
>>>>  			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>>>>  		};
>>>>  
>>>>  		ccorr0: ccorr@1400f000 {
>>>> @@ -723,6 +733,7 @@
>>>>  			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
>>>>  		};
>>>>  
>>>>  		aal0: aal@14010000 {
>>>> @@ -732,6 +743,7 @@
>>>>  			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
>>>>  		};
>>>>  
>>>>  		gamma0: gamma@14011000 {
>>>> @@ -741,6 +753,7 @@
>>>>  			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
>>>>  		};
>>>>  
>>>>  		dither0: dither@14012000 {
>>>> @@ -749,6 +762,7 @@
>>>>  			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>>>> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
>>>>  		};
>>>>  
>>>>  		mutex: mutex@14016000 {
>>>> @@ -756,6 +770,8 @@
>>>>  			reg = <0 0x14016000 0 0x1000>;
>>>>  			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>>>>  			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
>>>> +			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
>>>> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
>>>>  		};
>>>>  
>>>>  		smi_common: smi@14019000 {
>>>>
>>
> 
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^ permalink raw reply	[flat|nested] 36+ messages in thread
end of thread, other threads:[~2020-05-21 12:39 UTC | newest]

Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-14  4:49 [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node Bibby Hsieh
2020-02-14  4:49 ` Bibby Hsieh
2020-02-14  4:49 ` Bibby Hsieh
2020-02-14  4:49 ` Bibby Hsieh
2020-02-14  4:49 ` [PATCH 2/3] drm/mediatek: make sure previous message done or be aborted before send Bibby Hsieh
2020-02-14  4:49   ` Bibby Hsieh
2020-02-14  4:49   ` Bibby Hsieh
2020-02-14  4:49   ` Bibby Hsieh
2020-02-14  6:48   ` CK Hu
2020-02-14  6:48     ` CK Hu
2020-02-14  6:48     ` CK Hu
2020-02-14  6:48     ` CK Hu
2020-02-18  8:22     ` CK Hu
2020-02-18  8:22       ` CK Hu
2020-02-18  8:22       ` CK Hu
2020-02-18  8:22       ` CK Hu
2020-02-14  4:49 ` [PATCH 3/3] drm/mediatek: move gce event property to mutex device node Bibby Hsieh
2020-02-14  4:49   ` Bibby Hsieh
2020-02-14  4:49   ` Bibby Hsieh
2020-02-14  4:49   ` Bibby Hsieh
2020-02-14 10:06 ` [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node Matthias Brugger
2020-02-14 10:06   ` Matthias Brugger
2020-02-14 10:06   ` Matthias Brugger
2020-02-14 10:06   ` Matthias Brugger
2020-05-21 10:10   ` Matthias Brugger
2020-05-21 10:10     ` Matthias Brugger
2020-05-21 10:10     ` Matthias Brugger
2020-05-21 10:10     ` Matthias Brugger
2020-05-21 10:47     ` Bibby Hsieh
2020-05-21 10:47       ` Bibby Hsieh
2020-05-21 10:47       ` Bibby Hsieh
2020-05-21 10:47       ` Bibby Hsieh
2020-05-21 12:38       ` Matthias Brugger
2020-05-21 12:38         ` Matthias Brugger
2020-05-21 12:38         ` Matthias Brugger
2020-05-21 12:38         ` Matthias Brugger

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