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<1581922564-24914-1-git-send-email-chun-hung.wu@mediatek.com> References: <1581922564-24914-1-git-send-email-chun-hung.wu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org U3VwcG9ydCBjb21tYW5kIHF1ZXVlIGZvciBtdDY3NzkgcGxhdGZvcm0uDQphLiBBZGQgbXNkY19z ZXRfYnVzeV90aW1lb3V0KCkgdG8gY2FsY3VsYXRlIGVtbWMgd3JpdGUgdGltZW91dA0KYi4gQ29u bmVjdCBtdGsgbXNkYyBkcml2ZXIgdG8gY3FoY2kgZHJpdmVyIHRocm91Z2gNCiAgIGhvc3QtPmNx X2hvc3QtPm9wcyA9ICZtc2RjX2NtZHFfb3BzOw0KYy4gbXNkY19jbWRxX2lycSgpIHdpbGwgbGlu ayB1cCB3aXRoIGNxY2hpX2lycSgpLiBCZXNpZGVzLCBpdCBwcm92aWRlcw0KICAgbW9yZSBpcnEg ZXJyb3IgbWVzc2FnZXMgbGlrZSBSU1BDUkNFUlIvQ01EVE8vREFUQUNSQ0VSUi9EQVRUTU8uDQpk LiBVc2UgdGhlIG9wdGlvbnMgYmVsb3cgdG8gc2VwYXJhdGUgc3VwcG9ydCBmb3IgQ1FIQ0kgb3Ig bm90LCBiZWNhdXNlDQogICBzb21lIG9mIG91ciBwbGF0Zm9ybSBkb2VzIG5vdCBzdXBwb3J0IENR SENJIGhlbmNlIG5vIGtlcm5lbCBvcHRpb246DQogICBDT05GSUdfTU1DX0NRSENJLg0KICAgI2lm IElTX0VOQUJMRUQoQ09ORklHX01NQ19DUUhDSSkNCiAgIFhYWCAvL1N1cHBvcnQgQ1FIQ0kNCiAg ICNlbHNlDQogICBYWFggLy9Ob3Qgc3VwcG9ydCBDUUhDSQ0KICAgI2VuZGlmDQoNClNpZ25lZC1v ZmYtYnk6IENodW4tSHVuZyBXdSA8Y2h1bi1odW5nLnd1QG1lZGlhdGVrLmNvbT4NCi0tLQ0KIGRy aXZlcnMvbW1jL2hvc3QvbXRrLXNkLmMgfCAxMTkgKysrKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrKysrKw0KIDEgZmlsZSBjaGFuZ2VkLCAxMTkgaW5zZXJ0aW9ucygrKQ0K DQpkaWZmIC0tZ2l0IGEvZHJpdmVycy9tbWMvaG9zdC9tdGstc2QuYyBiL2RyaXZlcnMvbW1jL2hv c3QvbXRrLXNkLmMNCmluZGV4IDEyN2IwY2YuLmIxMzIzOTcgMTAwNjQ0DQotLS0gYS9kcml2ZXJz L21tYy9ob3N0L210ay1zZC5jDQorKysgYi9kcml2ZXJzL21tYy9ob3N0L210ay1zZC5jDQpAQCAt MzEsNiArMzEsOCBAQA0KICNpbmNsdWRlIDxsaW51eC9tbWMvc2Rpby5oPg0KICNpbmNsdWRlIDxs aW51eC9tbWMvc2xvdC1ncGlvLmg+DQogDQorI2luY2x1ZGUgImNxaGNpLmgiDQorDQogI2RlZmlu ZSBNQVhfQkRfTlVNICAgICAgICAgIDEwMjQNCiANCiAvKi0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tKi8NCkBA IC0xNTEsNiArMTUzLDcgQEANCiAjZGVmaW5lIE1TRENfSU5UX0RNQV9CRENTRVJSICAgICgweDEg PDwgMTcpCS8qIFcxQyAqLw0KICNkZWZpbmUgTVNEQ19JTlRfRE1BX0dQRENTRVJSICAgKDB4MSA8 PCAxOCkJLyogVzFDICovDQogI2RlZmluZSBNU0RDX0lOVF9ETUFfUFJPVEVDVCAgICAoMHgxIDw8 IDE5KQkvKiBXMUMgKi8NCisjZGVmaW5lIE1TRENfSU5UX0NNRFEgICAgICAgICAgICgweDEgPDwg MjgpCS8qIFcxQyAqLw0KIA0KIC8qIE1TRENfSU5URU4gbWFzayAqLw0KICNkZWZpbmUgTVNEQ19J TlRFTl9NTUNJUlEgICAgICAgKDB4MSA8PCAwKQkvKiBSVyAqLw0KQEAgLTE4MSw2ICsxODQsNyBA QA0KIC8qIFNEQ19DRkcgbWFzayAqLw0KICNkZWZpbmUgU0RDX0NGR19TRElPSU5UV0tVUCAgICAg KDB4MSA8PCAwKQkvKiBSVyAqLw0KICNkZWZpbmUgU0RDX0NGR19JTlNXS1VQICAgICAgICAgKDB4 MSA8PCAxKQkvKiBSVyAqLw0KKyNkZWZpbmUgU0RDX0NGR19XUkRUT0MgICAgICAgICAgKDB4MWZm ZiAgPDwgMikgIC8qIFJXICovDQogI2RlZmluZSBTRENfQ0ZHX0JVU1dJRFRIICAgICAgICAoMHgz IDw8IDE2KQkvKiBSVyAqLw0KICNkZWZpbmUgU0RDX0NGR19TRElPICAgICAgICAgICAgKDB4MSA8 PCAxOSkJLyogUlcgKi8NCiAjZGVmaW5lIFNEQ19DRkdfU0RJT0lERSAgICAgICAgICgweDEgPDwg MjApCS8qIFJXICovDQpAQCAtMjI4LDYgKzIzMiw3IEBADQogI2RlZmluZSBNU0RDX1BBVENIX0JJ VF9TUENQVVNIICAgICgweDEgPDwgMjkpCS8qIFJXICovDQogI2RlZmluZSBNU0RDX1BBVENIX0JJ VF9ERUNSQ1RNTyAgICgweDEgPDwgMzApCS8qIFJXICovDQogDQorI2RlZmluZSBNU0RDX1BCMV9C VVNZX0NIRUNLX1NFTCAgICgweDEgPDwgNykgICAgLyogUlcgKi8NCiAjZGVmaW5lIE1TRENfUEFU Q0hfQklUMV9TVE9QX0RMWSAgKDB4ZiA8PCA4KSAgICAvKiBSVyAqLw0KIA0KICNkZWZpbmUgTVNE Q19QQVRDSF9CSVQyX0NGR1JFU1AgICAoMHgxIDw8IDE1KSAgIC8qIFJXICovDQpAQCAtNDMxLDYg KzQzNiw3IEBAIHN0cnVjdCBtc2RjX2hvc3Qgew0KIAlzdHJ1Y3QgbXNkY19zYXZlX3BhcmEgc2F2 ZV9wYXJhOyAvKiB1c2VkIHdoZW4gZ2F0ZSBIQ0xLICovDQogCXN0cnVjdCBtc2RjX3R1bmVfcGFy YSBkZWZfdHVuZV9wYXJhOyAvKiBkZWZhdWx0IHR1bmUgc2V0dGluZyAqLw0KIAlzdHJ1Y3QgbXNk Y190dW5lX3BhcmEgc2F2ZWRfdHVuZV9wYXJhOyAvKiB0dW5lIHJlc3VsdCBvZiBDTUQyMS9DTUQx OSAqLw0KKwlzdHJ1Y3QgY3FoY2lfaG9zdCAqY3FfaG9zdDsNCiB9Ow0KIA0KIHN0YXRpYyBjb25z dCBzdHJ1Y3QgbXRrX21tY19jb21wYXRpYmxlIG10ODEzNV9jb21wYXQgPSB7DQpAQCAtNTI3LDYg KzUzMywxOCBAQCBzdHJ1Y3QgbXNkY19ob3N0IHsNCiAJLnVzZV9pbnRlcm5hbF9jZCA9IHRydWUs DQogfTsNCiANCitzdGF0aWMgY29uc3Qgc3RydWN0IG10a19tbWNfY29tcGF0aWJsZSBtdDY3Nzlf Y29tcGF0ID0gew0KKwkuY2xrX2Rpdl9iaXRzID0gMTIsDQorCS5oczQwMF90dW5lID0gZmFsc2Us DQorCS5wYWRfdHVuZV9yZWcgPSBNU0RDX1BBRF9UVU5FMCwNCisJLmFzeW5jX2ZpZm8gPSB0cnVl LA0KKwkuZGF0YV90dW5lID0gdHJ1ZSwNCisJLmJ1c3lfY2hlY2sgPSB0cnVlLA0KKwkuc3RvcF9j bGtfZml4ID0gdHJ1ZSwNCisJLmVuaGFuY2VfcnggPSB0cnVlLA0KKwkuc3VwcG9ydF82NGcgPSB0 cnVlLA0KK307DQorDQogc3RhdGljIGNvbnN0IHN0cnVjdCBvZl9kZXZpY2VfaWQgbXNkY19vZl9p ZHNbXSA9IHsNCiAJeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDgxMzUtbW1jIiwgLmRhdGEg PSAmbXQ4MTM1X2NvbXBhdH0sDQogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLW1t YyIsIC5kYXRhID0gJm10ODE3M19jb21wYXR9LA0KQEAgLTUzNiw2ICs1NTQsNyBAQCBzdHJ1Y3Qg bXNkY19ob3N0IHsNCiAJeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDc2MjItbW1jIiwgLmRh dGEgPSAmbXQ3NjIyX2NvbXBhdH0sDQogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4NTE2 LW1tYyIsIC5kYXRhID0gJm10ODUxNl9jb21wYXR9LA0KIAl7IC5jb21wYXRpYmxlID0gIm1lZGlh dGVrLG10NzYyMC1tbWMiLCAuZGF0YSA9ICZtdDc2MjBfY29tcGF0fSwNCisJeyAuY29tcGF0aWJs ZSA9ICJtZWRpYXRlayxtdDY3NzktbW1jIiwgLmRhdGEgPSAmbXQ2Nzc5X2NvbXBhdH0sDQogCXt9 DQogfTsNCiBNT0RVTEVfREVWSUNFX1RBQkxFKG9mLCBtc2RjX29mX2lkcyk7DQpAQCAtNzM5LDYg Kzc1OCwxNSBAQCBzdGF0aWMgdm9pZCBtc2RjX3NldF90aW1lb3V0KHN0cnVjdCBtc2RjX2hvc3Qg Kmhvc3QsIHU2NCBucywgdTY0IGNsa3MpDQogCQkgICAgICAodTMyKSh0aW1lb3V0ID4gMjU1ID8g MjU1IDogdGltZW91dCkpOw0KIH0NCiANCitzdGF0aWMgdm9pZCBtc2RjX3NldF9idXN5X3RpbWVv dXQoc3RydWN0IG1zZGNfaG9zdCAqaG9zdCwgdTY0IG5zLCB1NjQgY2xrcykNCit7DQorCXU2NCB0 aW1lb3V0Ow0KKw0KKwl0aW1lb3V0ID0gbXNkY190aW1lb3V0X2NhbChob3N0LCBucywgY2xrcyk7 DQorCXNkcl9zZXRfZmllbGQoaG9zdC0+YmFzZSArIFNEQ19DRkcsIFNEQ19DRkdfV1JEVE9DLA0K KwkJICAgICAgKHUzMikodGltZW91dCA+IDgxOTEgPyA4MTkxIDogdGltZW91dCkpOw0KK30NCisN CiBzdGF0aWMgdm9pZCBtc2RjX2dhdGVfY2xvY2soc3RydWN0IG1zZGNfaG9zdCAqaG9zdCkNCiB7 DQogCWNsa19kaXNhYmxlX3VucHJlcGFyZShob3N0LT5zcmNfY2xrX2NnKTsNCkBAIC0xNDI1LDYg KzE0NTMsMzYgQEAgc3RhdGljIHZvaWQgbXNkY19lbmFibGVfc2Rpb19pcnEoc3RydWN0IG1tY19o b3N0ICptbWMsIGludCBlbmIpDQogCQlwbV9ydW50aW1lX3B1dF9ub2lkbGUoaG9zdC0+ZGV2KTsN CiB9DQogDQorI2lmIElTX0VOQUJMRUQoQ09ORklHX01NQ19DUUhDSSkNCitzdGF0aWMgaXJxcmV0 dXJuX3QgbXNkY19jbWRxX2lycShzdHJ1Y3QgbXNkY19ob3N0ICpob3N0LCB1MzIgaW50c3RzKQ0K K3sNCisJaW50IGNtZF9lcnIgPSAwLCBkYXRfZXJyID0gMDsNCisNCisJaWYgKGludHN0cyAmIE1T RENfSU5UX1JTUENSQ0VSUikgew0KKwkJY21kX2VyciA9ICh1bnNpZ25lZCBpbnQpLUVJTFNFUTsN CisJCWRldl9lcnIoaG9zdC0+ZGV2LCAiJXM6IENNRCBDUkMgRVJSIiwgX19mdW5jX18pOw0KKwl9 IGVsc2UgaWYgKGludHN0cyAmIE1TRENfSU5UX0NNRFRNTykgew0KKwkJY21kX2VyciA9ICh1bnNp Z25lZCBpbnQpLUVUSU1FRE9VVDsNCisJCWRldl9lcnIoaG9zdC0+ZGV2LCAiJXM6IENNRCBUSU1F T1VUIEVSUiIsIF9fZnVuY19fKTsNCisJfQ0KKw0KKwlpZiAoaW50c3RzICYgTVNEQ19JTlRfREFU Q1JDRVJSKSB7DQorCQlkYXRfZXJyID0gKHVuc2lnbmVkIGludCktRUlMU0VROw0KKwkJZGV2X2Vy cihob3N0LT5kZXYsICIlczogREFUQSBDUkMgRVJSIiwgX19mdW5jX18pOw0KKwl9IGVsc2UgaWYg KGludHN0cyAmIE1TRENfSU5UX0RBVFRNTykgew0KKwkJZGF0X2VyciA9ICh1bnNpZ25lZCBpbnQp LUVUSU1FRE9VVDsNCisJCWRldl9lcnIoaG9zdC0+ZGV2LCAiJXM6IERBVEEgVElNRU9VVCBFUlIi LCBfX2Z1bmNfXyk7DQorCX0NCisNCisJaWYgKGNtZF9lcnIgfHwgZGF0X2Vycikgew0KKwkJZGV2 X2Vycihob3N0LT5kZXYsICJjbWRfZXJyID0gJWQsIGRhdF9lcnIgPSVkLCBpbnRzdHMgPSAweCV4 IiwNCisJCQljbWRfZXJyLCBkYXRfZXJyLCBpbnRzdHMpOw0KKwl9DQorDQorCXJldHVybiBjcWhj aV9pcnEoaG9zdC0+bW1jLCAwLCBjbWRfZXJyLCBkYXRfZXJyKTsNCit9DQorI2VuZGlmDQorDQog c3RhdGljIGlycXJldHVybl90IG1zZGNfaXJxKGludCBpcnEsIHZvaWQgKmRldl9pZCkNCiB7DQog CXN0cnVjdCBtc2RjX2hvc3QgKmhvc3QgPSAoc3RydWN0IG1zZGNfaG9zdCAqKSBkZXZfaWQ7DQpA QCAtMTQ2MSw2ICsxNTE5LDE2IEBAIHN0YXRpYyBpcnFyZXR1cm5fdCBtc2RjX2lycShpbnQgaXJx LCB2b2lkICpkZXZfaWQpDQogCQlpZiAoIShldmVudHMgJiAoZXZlbnRfbWFzayAmIH5NU0RDX0lO VF9TRElPSVJRKSkpDQogCQkJYnJlYWs7DQogDQorI2lmIElTX0VOQUJMRUQoQ09ORklHX01NQ19D UUhDSSkNCisJCWlmICgoaG9zdC0+bW1jLT5jYXBzMiAmIE1NQ19DQVAyX0NRRSkgJiYNCisJCSAg ICAoZXZlbnRzICYgTVNEQ19JTlRfQ01EUSkpIHsNCisJCQltc2RjX2NtZHFfaXJxKGhvc3QsIGV2 ZW50cyk7DQorCQkJLyogY2xlYXIgaW50ZXJydXB0cyAqLw0KKwkJCXdyaXRlbChldmVudHMsIGhv c3QtPmJhc2UgKyBNU0RDX0lOVCk7DQorCQkJcmV0dXJuIElSUV9IQU5ETEVEOw0KKwkJfQ0KKyNl bmRpZg0KKw0KIAkJaWYgKCFtcnEpIHsNCiAJCQlkZXZfZXJyKGhvc3QtPmRldiwNCiAJCQkJIiVz OiBNUlE9TlVMTDsgZXZlbnRzPSUwOFg7IGV2ZW50X21hc2s9JTA4WFxuIiwNCkBAIC0yMTQ0LDYg KzIyMTIsMzYgQEAgc3RhdGljIGludCBtc2RjX2dldF9jZChzdHJ1Y3QgbW1jX2hvc3QgKm1tYykN CiAJCXJldHVybiAhdmFsOw0KIH0NCiANCitzdGF0aWMgdm9pZCBtc2RjX2NxZV9lbmFibGUoc3Ry dWN0IG1tY19ob3N0ICptbWMpDQorew0KKwlzdHJ1Y3QgbXNkY19ob3N0ICpob3N0ID0gbW1jX3By aXYobW1jKTsNCisNCisJLyogZW5hYmxlIGNtZHEgaXJxICovDQorCXdyaXRlbChNU0RDX0lOVF9D TURRLCBob3N0LT5iYXNlICsgTVNEQ19JTlRFTik7DQorCS8qIGVuYWJsZSBidXN5IGNoZWNrICov DQorCXNkcl9zZXRfYml0cyhob3N0LT5iYXNlICsgTVNEQ19QQVRDSF9CSVQxLCBNU0RDX1BCMV9C VVNZX0NIRUNLX1NFTCk7DQorCS8qIGRlZmF1bHQgd3JpdGUgZGF0YSAvIGJ1c3kgdGltZW91dCAy MHMgKi8NCisJbXNkY19zZXRfYnVzeV90aW1lb3V0KGhvc3QsIDIwICogMTAwMDAwMDAwMFVMTCwg MCk7DQorCS8qIGRlZmF1bHQgcmVhZCBkYXRhIHRpbWVvdXQgMXMgKi8NCisJbXNkY19zZXRfdGlt ZW91dChob3N0LCAxMDAwMDAwMDAwVUxMLCAwKTsNCit9DQorDQordm9pZCBtc2RjX2NxZV9kaXNh YmxlKHN0cnVjdCBtbWNfaG9zdCAqbW1jLCBib29sIHJlY292ZXJ5KQ0KK3sNCisJc3RydWN0IG1z ZGNfaG9zdCAqaG9zdCA9IG1tY19wcml2KG1tYyk7DQorDQorCS8qIGRpc2FibGUgY21kcSBpcnEg Ki8NCisJc2RyX2Nscl9iaXRzKGhvc3QtPmJhc2UgKyBNU0RDX0lOVEVOLCBNU0RDX0lOVF9DTURR KTsNCisJLyogZGlzYWJsZSBidXN5IGNoZWNrICovDQorCXNkcl9jbHJfYml0cyhob3N0LT5iYXNl ICsgTVNEQ19QQVRDSF9CSVQxLCBNU0RDX1BCMV9CVVNZX0NIRUNLX1NFTCk7DQorDQorCWlmIChy ZWNvdmVyeSkgew0KKwkJc2RyX3NldF9maWVsZChob3N0LT5iYXNlICsgTVNEQ19ETUFfQ1RSTCwN CisJCQkgICAgICBNU0RDX0RNQV9DVFJMX1NUT1AsIDEpOw0KKwkJbXNkY19yZXNldF9odyhob3N0 KTsNCisJfQ0KK30NCisNCiBzdGF0aWMgY29uc3Qgc3RydWN0IG1tY19ob3N0X29wcyBtdF9tc2Rj X29wcyA9IHsNCiAJLnBvc3RfcmVxID0gbXNkY19wb3N0X3JlcSwNCiAJLnByZV9yZXEgPSBtc2Rj X3ByZV9yZXEsDQpAQCAtMjE2MCw2ICsyMjU4LDExIEBAIHN0YXRpYyBpbnQgbXNkY19nZXRfY2Qo c3RydWN0IG1tY19ob3N0ICptbWMpDQogCS5od19yZXNldCA9IG1zZGNfaHdfcmVzZXQsDQogfTsN CiANCitzdGF0aWMgY29uc3Qgc3RydWN0IGNxaGNpX2hvc3Rfb3BzIG1zZGNfY21kcV9vcHMgPSB7 DQorCS5lbmFibGUgICAgICAgICA9IG1zZGNfY3FlX2VuYWJsZSwNCisJLmRpc2FibGUgICAgICAg ID0gbXNkY19jcWVfZGlzYWJsZSwNCit9Ow0KKw0KIHN0YXRpYyB2b2lkIG1zZGNfb2ZfcHJvcGVy dHlfcGFyc2Uoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldiwNCiAJCQkJICAgc3RydWN0IG1z ZGNfaG9zdCAqaG9zdCkNCiB7DQpAQCAtMjMxMSw2ICsyNDE0LDIyIEBAIHN0YXRpYyBpbnQgbXNk Y19kcnZfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikNCiAJCWhvc3QtPmRtYV9t YXNrID0gRE1BX0JJVF9NQVNLKDMyKTsNCiAJbW1jX2RldihtbWMpLT5kbWFfbWFzayA9ICZob3N0 LT5kbWFfbWFzazsNCiANCisjaWYgSVNfRU5BQkxFRChDT05GSUdfTU1DX0NRSENJKQ0KKwlpZiAo bW1jLT5jYXBzMiAmIE1NQ19DQVAyX0NRRSkgew0KKwkJaG9zdC0+Y3FfaG9zdCA9IGRldm1fa3ph bGxvYyhob3N0LT5tbWMtPnBhcmVudCwNCisJCQkJCSAgICAgc2l6ZW9mKCpob3N0LT5jcV9ob3N0 KSwNCisJCQkJCSAgICAgR0ZQX0tFUk5FTCk7DQorCQlob3N0LT5jcV9ob3N0LT5jYXBzIHw9IENR SENJX1RBU0tfREVTQ19TWl8xMjg7DQorCQlob3N0LT5jcV9ob3N0LT5tbWlvID0gaG9zdC0+YmFz ZSArIDB4ODAwOw0KKwkJaG9zdC0+Y3FfaG9zdC0+b3BzID0gJm1zZGNfY21kcV9vcHM7DQorCQlj cWhjaV9pbml0KGhvc3QtPmNxX2hvc3QsIG1tYywgdHJ1ZSk7DQorCQltbWMtPm1heF9zZWdzID0g MTI4Ow0KKwkJLyogY3FoY2kgMTZiaXQgbGVuZ3RoICovDQorCQkvKiAwIHNpemUsIG1lYW5zIDY1 NTM2IHNvIHdlIGRvbid0IGhhdmUgdG8gLTEgaGVyZSAqLw0KKwkJbW1jLT5tYXhfc2VnX3NpemUg PSA2NCAqIDEwMjQ7DQorCX0NCisjZW5kaWYNCisNCiAJaG9zdC0+dGltZW91dF9jbGtzID0gMyAq IDEwNDg1NzY7DQogCWhvc3QtPmRtYS5ncGQgPSBkbWFfYWxsb2NfY29oZXJlbnQoJnBkZXYtPmRl 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MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 17 Feb 2020 14:54:44 +0800 From: Chun-Hung Wu To: Chaotian Jing , Ulf Hansson , Rob Herring , Mark Rutland , Matthias Brugger , "Linus Walleij" , Pavel Machek , Kate Stewart , Greg Kroah-Hartman , Martin Blumenstingl , Pan Bian , "Thomas Gleixner" , Allison Randal , "Mathieu Malaterre" , Stanley Chu , "Kuohong Wang" Subject: [PATCH v3 3/4] mmc: mediatek: command queue support Date: Mon, 17 Feb 2020 14:56:03 +0800 Message-ID: <1581922564-24914-4-git-send-email-chun-hung.wu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1581922564-24914-1-git-send-email-chun-hung.wu@mediatek.com> References: <1581922564-24914-1-git-send-email-chun-hung.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200216_230638_074070_D20C12FA X-CRM114-Status: GOOD ( 15.95 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, wsd_upstream@mediatek.com, Chun-Hung Wu , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, kernel-team@android.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Support command queue for mt6779 platform. a. Add msdc_set_busy_timeout() to calculate emmc write timeout b. Connect mtk msdc driver to cqhci driver through host->cq_host->ops = &msdc_cmdq_ops; c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO. d. Use the options below to separate support for CQHCI or not, because some of our platform does not support CQHCI hence no kernel option: CONFIG_MMC_CQHCI. #if IS_ENABLED(CONFIG_MMC_CQHCI) XXX //Support CQHCI #else XXX //Not support CQHCI #endif Signed-off-by: Chun-Hung Wu --- drivers/mmc/host/mtk-sd.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 127b0cf..b132397 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -31,6 +31,8 @@ #include #include +#include "cqhci.h" + #define MAX_BD_NUM 1024 /*--------------------------------------------------------------------------*/ @@ -151,6 +153,7 @@ #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ +#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ /* MSDC_INTEN mask */ #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ @@ -181,6 +184,7 @@ /* SDC_CFG mask */ #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ +#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ #define SDC_CFG_SDIO (0x1 << 19) /* RW */ #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ @@ -228,6 +232,7 @@ #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ +#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ @@ -431,6 +436,7 @@ struct msdc_host { struct msdc_save_para save_para; /* used when gate HCLK */ struct msdc_tune_para def_tune_para; /* default tune setting */ struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ + struct cqhci_host *cq_host; }; static const struct mtk_mmc_compatible mt8135_compat = { @@ -527,6 +533,18 @@ struct msdc_host { .use_internal_cd = true, }; +static const struct mtk_mmc_compatible mt6779_compat = { + .clk_div_bits = 12, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE0, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, + .support_64g = true, +}; + static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, @@ -536,6 +554,7 @@ struct msdc_host { { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, + { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, {} }; MODULE_DEVICE_TABLE(of, msdc_of_ids); @@ -739,6 +758,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) (u32)(timeout > 255 ? 255 : timeout)); } +static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, + (u32)(timeout > 8191 ? 8191 : timeout)); +} + static void msdc_gate_clock(struct msdc_host *host) { clk_disable_unprepare(host->src_clk_cg); @@ -1425,6 +1453,36 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) pm_runtime_put_noidle(host->dev); } +#if IS_ENABLED(CONFIG_MMC_CQHCI) +static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) +{ + int cmd_err = 0, dat_err = 0; + + if (intsts & MSDC_INT_RSPCRCERR) { + cmd_err = (unsigned int)-EILSEQ; + dev_err(host->dev, "%s: CMD CRC ERR", __func__); + } else if (intsts & MSDC_INT_CMDTMO) { + cmd_err = (unsigned int)-ETIMEDOUT; + dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); + } + + if (intsts & MSDC_INT_DATCRCERR) { + dat_err = (unsigned int)-EILSEQ; + dev_err(host->dev, "%s: DATA CRC ERR", __func__); + } else if (intsts & MSDC_INT_DATTMO) { + dat_err = (unsigned int)-ETIMEDOUT; + dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); + } + + if (cmd_err || dat_err) { + dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", + cmd_err, dat_err, intsts); + } + + return cqhci_irq(host->mmc, 0, cmd_err, dat_err); +} +#endif + static irqreturn_t msdc_irq(int irq, void *dev_id) { struct msdc_host *host = (struct msdc_host *) dev_id; @@ -1461,6 +1519,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) break; +#if IS_ENABLED(CONFIG_MMC_CQHCI) + if ((host->mmc->caps2 & MMC_CAP2_CQE) && + (events & MSDC_INT_CMDQ)) { + msdc_cmdq_irq(host, events); + /* clear interrupts */ + writel(events, host->base + MSDC_INT); + return IRQ_HANDLED; + } +#endif + if (!mrq) { dev_err(host->dev, "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", @@ -2144,6 +2212,36 @@ static int msdc_get_cd(struct mmc_host *mmc) return !val; } +static void msdc_cqe_enable(struct mmc_host *mmc) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* enable cmdq irq */ + writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); + /* enable busy check */ + sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + /* default write data / busy timeout 20s */ + msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); + /* default read data timeout 1s */ + msdc_set_timeout(host, 1000000000ULL, 0); +} + +void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* disable cmdq irq */ + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); + /* disable busy check */ + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + + if (recovery) { + sdr_set_field(host->base + MSDC_DMA_CTRL, + MSDC_DMA_CTRL_STOP, 1); + msdc_reset_hw(host); + } +} + static const struct mmc_host_ops mt_msdc_ops = { .post_req = msdc_post_req, .pre_req = msdc_pre_req, @@ -2160,6 +2258,11 @@ static int msdc_get_cd(struct mmc_host *mmc) .hw_reset = msdc_hw_reset, }; +static const struct cqhci_host_ops msdc_cmdq_ops = { + .enable = msdc_cqe_enable, + .disable = msdc_cqe_disable, +}; + static void msdc_of_property_parse(struct platform_device *pdev, struct msdc_host *host) { @@ -2311,6 +2414,22 @@ static int msdc_drv_probe(struct platform_device *pdev) host->dma_mask = DMA_BIT_MASK(32); mmc_dev(mmc)->dma_mask = &host->dma_mask; +#if IS_ENABLED(CONFIG_MMC_CQHCI) + if (mmc->caps2 & MMC_CAP2_CQE) { + host->cq_host = devm_kzalloc(host->mmc->parent, + sizeof(*host->cq_host), + GFP_KERNEL); + host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; + host->cq_host->mmio = host->base + 0x800; + host->cq_host->ops = &msdc_cmdq_ops; + cqhci_init(host->cq_host, mmc, true); + mmc->max_segs = 128; + /* cqhci 16bit length */ + /* 0 size, means 65536 so we don't have to -1 here */ + mmc->max_seg_size = 64 * 1024; + } +#endif + host->timeout_clks = 3 * 1048576; host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2 * sizeof(struct mt_gpdma_desc), -- 1.9.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93696C7619B for ; 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Mon, 17 Feb 2020 14:55:50 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 17 Feb 2020 14:54:44 +0800 From: Chun-Hung Wu To: Chaotian Jing , Ulf Hansson , Rob Herring , Mark Rutland , Matthias Brugger , "Linus Walleij" , Pavel Machek , Kate Stewart , Greg Kroah-Hartman , Martin Blumenstingl , Pan Bian , "Thomas Gleixner" , Allison Randal , "Mathieu Malaterre" , Stanley Chu , "Kuohong Wang" Subject: [PATCH v3 3/4] mmc: mediatek: command queue support Date: Mon, 17 Feb 2020 14:56:03 +0800 Message-ID: <1581922564-24914-4-git-send-email-chun-hung.wu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1581922564-24914-1-git-send-email-chun-hung.wu@mediatek.com> References: <1581922564-24914-1-git-send-email-chun-hung.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200216_230638_074070_D20C12FA X-CRM114-Status: GOOD ( 15.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, wsd_upstream@mediatek.com, Chun-Hung Wu , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, kernel-team@android.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Support command queue for mt6779 platform. a. Add msdc_set_busy_timeout() to calculate emmc write timeout b. Connect mtk msdc driver to cqhci driver through host->cq_host->ops = &msdc_cmdq_ops; c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO. d. Use the options below to separate support for CQHCI or not, because some of our platform does not support CQHCI hence no kernel option: CONFIG_MMC_CQHCI. #if IS_ENABLED(CONFIG_MMC_CQHCI) XXX //Support CQHCI #else XXX //Not support CQHCI #endif Signed-off-by: Chun-Hung Wu --- drivers/mmc/host/mtk-sd.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 127b0cf..b132397 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -31,6 +31,8 @@ #include #include +#include "cqhci.h" + #define MAX_BD_NUM 1024 /*--------------------------------------------------------------------------*/ @@ -151,6 +153,7 @@ #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ +#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ /* MSDC_INTEN mask */ #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ @@ -181,6 +184,7 @@ /* SDC_CFG mask */ #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ +#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ #define SDC_CFG_SDIO (0x1 << 19) /* RW */ #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ @@ -228,6 +232,7 @@ #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ +#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ @@ -431,6 +436,7 @@ struct msdc_host { struct msdc_save_para save_para; /* used when gate HCLK */ struct msdc_tune_para def_tune_para; /* default tune setting */ struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ + struct cqhci_host *cq_host; }; static const struct mtk_mmc_compatible mt8135_compat = { @@ -527,6 +533,18 @@ struct msdc_host { .use_internal_cd = true, }; +static const struct mtk_mmc_compatible mt6779_compat = { + .clk_div_bits = 12, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE0, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, + .support_64g = true, +}; + static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, @@ -536,6 +554,7 @@ struct msdc_host { { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, + { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, {} }; MODULE_DEVICE_TABLE(of, msdc_of_ids); @@ -739,6 +758,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) (u32)(timeout > 255 ? 255 : timeout)); } +static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, + (u32)(timeout > 8191 ? 8191 : timeout)); +} + static void msdc_gate_clock(struct msdc_host *host) { clk_disable_unprepare(host->src_clk_cg); @@ -1425,6 +1453,36 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) pm_runtime_put_noidle(host->dev); } +#if IS_ENABLED(CONFIG_MMC_CQHCI) +static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) +{ + int cmd_err = 0, dat_err = 0; + + if (intsts & MSDC_INT_RSPCRCERR) { + cmd_err = (unsigned int)-EILSEQ; + dev_err(host->dev, "%s: CMD CRC ERR", __func__); + } else if (intsts & MSDC_INT_CMDTMO) { + cmd_err = (unsigned int)-ETIMEDOUT; + dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); + } + + if (intsts & MSDC_INT_DATCRCERR) { + dat_err = (unsigned int)-EILSEQ; + dev_err(host->dev, "%s: DATA CRC ERR", __func__); + } else if (intsts & MSDC_INT_DATTMO) { + dat_err = (unsigned int)-ETIMEDOUT; + dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); + } + + if (cmd_err || dat_err) { + dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", + cmd_err, dat_err, intsts); + } + + return cqhci_irq(host->mmc, 0, cmd_err, dat_err); +} +#endif + static irqreturn_t msdc_irq(int irq, void *dev_id) { struct msdc_host *host = (struct msdc_host *) dev_id; @@ -1461,6 +1519,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) break; +#if IS_ENABLED(CONFIG_MMC_CQHCI) + if ((host->mmc->caps2 & MMC_CAP2_CQE) && + (events & MSDC_INT_CMDQ)) { + msdc_cmdq_irq(host, events); + /* clear interrupts */ + writel(events, host->base + MSDC_INT); + return IRQ_HANDLED; + } +#endif + if (!mrq) { dev_err(host->dev, "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", @@ -2144,6 +2212,36 @@ static int msdc_get_cd(struct mmc_host *mmc) return !val; } +static void msdc_cqe_enable(struct mmc_host *mmc) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* enable cmdq irq */ + writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); + /* enable busy check */ + sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + /* default write data / busy timeout 20s */ + msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); + /* default read data timeout 1s */ + msdc_set_timeout(host, 1000000000ULL, 0); +} + +void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* disable cmdq irq */ + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); + /* disable busy check */ + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + + if (recovery) { + sdr_set_field(host->base + MSDC_DMA_CTRL, + MSDC_DMA_CTRL_STOP, 1); + msdc_reset_hw(host); + } +} + static const struct mmc_host_ops mt_msdc_ops = { .post_req = msdc_post_req, .pre_req = msdc_pre_req, @@ -2160,6 +2258,11 @@ static int msdc_get_cd(struct mmc_host *mmc) .hw_reset = msdc_hw_reset, }; +static const struct cqhci_host_ops msdc_cmdq_ops = { + .enable = msdc_cqe_enable, + .disable = msdc_cqe_disable, +}; + static void msdc_of_property_parse(struct platform_device *pdev, struct msdc_host *host) { @@ -2311,6 +2414,22 @@ static int msdc_drv_probe(struct platform_device *pdev) host->dma_mask = DMA_BIT_MASK(32); mmc_dev(mmc)->dma_mask = &host->dma_mask; +#if IS_ENABLED(CONFIG_MMC_CQHCI) + if (mmc->caps2 & MMC_CAP2_CQE) { + host->cq_host = devm_kzalloc(host->mmc->parent, + sizeof(*host->cq_host), + GFP_KERNEL); + host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; + host->cq_host->mmio = host->base + 0x800; + host->cq_host->ops = &msdc_cmdq_ops; + cqhci_init(host->cq_host, mmc, true); + mmc->max_segs = 128; + /* cqhci 16bit length */ + /* 0 size, means 65536 so we don't have to -1 here */ + mmc->max_seg_size = 64 * 1024; + } +#endif + host->timeout_clks = 3 * 1048576; host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2 * sizeof(struct mt_gpdma_desc), -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel