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From: Julien Freche <1863685@bugs.launchpad.net>
To: qemu-devel@nongnu.org
Subject: [Bug 1863685] Re: ARM: HCR.TSW traps are not implemented
Date: Tue, 18 Feb 2020 20:20:14 -0000	[thread overview]
Message-ID: <158205721472.24554.10171255394519386166.malone@gac.canonical.com> (raw)
In-Reply-To: 158198492915.29307.8701397558481624318.malonedeb@chaenomeles.canonical.com

Sorry, I meant the operation is a write (TVM is on). The result of the
operation is setting DACR to 0 so the guest stops progressing after
that.

Anyway, since the issue could also be on my side, I don't want to block
you with this.

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https://bugs.launchpad.net/bugs/1863685

Title:
  ARM: HCR.TSW traps are not implemented

Status in QEMU:
  In Progress

Bug description:
  On 32-bit and 64-bit ARM platforms, setting HCR.TSW is supposed to
  "Trap data or unified cache maintenance instructions that operate by
  Set/Way." Quoting the ARM manual:

  If EL1 is using AArch64 state, accesses to DC ISW, DC CSW, DC CISW are trapped to EL2, reported using EC syndrome value 0x18.
  If EL1 is using AArch32 state, accesses to DCISW, DCCSW, DCCISW are trapped to EL2, reported using EC syndrome value 0x03.

  However, QEMU does not trap those instructions/registers. This was
  tested on the branch master of the git repo.

To manage notifications about this bug go to:
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  parent reply	other threads:[~2020-02-18 20:26 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-18  0:15 [Bug 1863685] [NEW] ARM: HCR.TSW traps are not implemented Julien Freche
2020-02-18 15:31 ` [Bug 1863685] " Richard Henderson
2020-02-18 16:56 ` Richard Henderson
2020-02-18 20:06 ` Julien Freche
2020-02-18 20:20 ` Julien Freche [this message]
2020-02-18 20:41 ` Richard Henderson
2020-02-18 21:03 ` Julien Freche
2020-03-10  9:05 ` Laurent Vivier
2020-04-30 13:29 ` Laurent Vivier

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