* [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping
@ 2020-02-22 2:08 José Roberto de Souza
2020-02-22 2:08 ` [Intel-gfx] [PATCH 2/8] drm/i915/tgl: Implement Wa_1409804808 José Roberto de Souza
` (9 more replies)
0 siblings, 10 replies; 19+ messages in thread
From: José Roberto de Souza @ 2020-02-22 2:08 UTC (permalink / raw)
To: intel-gfx
This workaround is only fixed in C0 stepping to extend it to B0 too.
BSpec: 52890
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4305ccc4c683..57282b719ece 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1575,6 +1575,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_ICELAKE(p) && IS_REVID(p, since, until))
#define TGL_REVID_A0 0x0
+#define TGL_REVID_B0 0x1
#define IS_TGL_REVID(p, since, until) \
(IS_TIGERLAKE(p) && IS_REVID(p, since, until))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ffac0b862ca5..33149bccd117 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6852,7 +6852,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
/* Wa_1409825376:tgl (pre-prod)*/
- if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
+ if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
TGL_VRH_GATING_DIS);
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 2/8] drm/i915/tgl: Implement Wa_1409804808
2020-02-22 2:08 [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping José Roberto de Souza
@ 2020-02-22 2:08 ` José Roberto de Souza
2020-02-24 16:20 ` Matt Roper
2020-02-22 2:08 ` [Intel-gfx] [PATCH 3/8] drm/i915/tgl: Implement Wa_1806527549 José Roberto de Souza
` (8 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: José Roberto de Souza @ 2020-02-22 2:08 UTC (permalink / raw)
To: intel-gfx
This workaround the CS not done issue on PIPE_CONTROL.
BSpec: 52890
BSpec: 46218
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 887e0dc701f7..57a5a39ee902 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1367,6 +1367,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN12_DISABLE_EARLY_READ);
}
+ if (IS_TIGERLAKE(i915)) {
+ /* Wa_1409804808:tgl */
+ wa_masked_en(wal, GEN7_ROW_CHICKEN2,
+ GEN12_PUSH_CONSTANT_DEREFERENCE_HOLD_DISABLE);
+ }
+
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f45b5e86ec63..cfc238ffd4ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9149,8 +9149,9 @@ enum {
#define THROTTLE_12_5 (7 << 2)
#define DISABLE_EARLY_EOT (1 << 1)
-#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
-#define GEN12_DISABLE_EARLY_READ BIT(14)
+#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
+#define GEN12_DISABLE_EARLY_READ BIT(14)
+#define GEN12_PUSH_CONSTANT_DEREFERENCE_HOLD_DISABLE BIT(8)
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
--
2.25.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 3/8] drm/i915/tgl: Implement Wa_1806527549
2020-02-22 2:08 [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping José Roberto de Souza
2020-02-22 2:08 ` [Intel-gfx] [PATCH 2/8] drm/i915/tgl: Implement Wa_1409804808 José Roberto de Souza
@ 2020-02-22 2:08 ` José Roberto de Souza
2020-02-22 8:53 ` Chris Wilson
2020-02-22 2:08 ` [Intel-gfx] [PATCH 4/8] drm/i915/tgl: Add Wa_1409085225, Wa_14010229206 José Roberto de Souza
` (7 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: José Roberto de Souza @ 2020-02-22 2:08 UTC (permalink / raw)
To: intel-gfx
This will whitelist the HIZ_CHICKEN register so mesa can disable the
optimizations and void hang when using D16_UNORM.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 57a5a39ee902..fbed5bdc9e04 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -598,6 +598,10 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
+ /* Wa_1806527549:tgl */
+ WA_SET_BIT_MASKED(HIZ_CHICKEN,
+ GEN12_HZ_DEPTH_TEST_LE_GE_OPTIMIZATION_DISABLE);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cfc238ffd4ae..49872a1dc7a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7843,6 +7843,7 @@ enum {
#define HIZ_CHICKEN _MMIO(0x7018)
# define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
+# define GEN12_HZ_DEPTH_TEST_LE_GE_OPTIMIZATION_DISABLE (1 << 13)
# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3)
#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
--
2.25.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 4/8] drm/i915/tgl: Add Wa_1409085225, Wa_14010229206
2020-02-22 2:08 [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping José Roberto de Souza
2020-02-22 2:08 ` [Intel-gfx] [PATCH 2/8] drm/i915/tgl: Implement Wa_1409804808 José Roberto de Souza
2020-02-22 2:08 ` [Intel-gfx] [PATCH 3/8] drm/i915/tgl: Implement Wa_1806527549 José Roberto de Souza
@ 2020-02-22 2:08 ` José Roberto de Souza
2020-02-24 16:27 ` Matt Roper
2020-02-22 2:08 ` [Intel-gfx] [PATCH 5/8] drm/i915/tgl: Extend Wa_1606931601 for all steppings José Roberto de Souza
` (6 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: José Roberto de Souza @ 2020-02-22 2:08 UTC (permalink / raw)
To: intel-gfx
From: Matt Atwood <matthew.s.atwood@intel.com>
Disable Push Constant buffer addition for TGL.
v2: typos, add additional Wa reference
v3: use REG_BIT macro, move to rcs_engine_wa_init, clean up commit
message.
Bspec: 52890
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index fbed5bdc9e04..e9619c493e6a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1369,6 +1369,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_masked_en(wal,
GEN7_ROW_CHICKEN2,
GEN12_DISABLE_EARLY_READ);
+
+ /*
+ * Wa_1409085225:tgl
+ * Wa_14010229206:tgl
+ */
+ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
}
if (IS_TIGERLAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 49872a1dc7a4..78164fa9e574 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9159,6 +9159,9 @@ enum {
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
+#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
+#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
+
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
--
2.25.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 5/8] drm/i915/tgl: Extend Wa_1606931601 for all steppings
2020-02-22 2:08 [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping José Roberto de Souza
` (2 preceding siblings ...)
2020-02-22 2:08 ` [Intel-gfx] [PATCH 4/8] drm/i915/tgl: Add Wa_1409085225, Wa_14010229206 José Roberto de Souza
@ 2020-02-22 2:08 ` José Roberto de Souza
2020-02-22 2:08 ` [Intel-gfx] [PATCH 6/8] drm/i915/tgl: Add note to Wa_1607297627 José Roberto de Souza
` (5 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: José Roberto de Souza @ 2020-02-22 2:08 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
According to BSpec. Wa_1606931601 applies for all
TGL steppings.This patch moves the WA implementation
out of A0 only block of rcs_engine_wa_init().
The WA is has also been referred to by an alternate name
Wa_1607090982.
Bspec: 46045, 52890
Fixes: 3873fd1a43c7 ("drm/i915: Use engine wa list for Wa_1607090982")
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e9619c493e6a..978a5b051ce9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1365,11 +1365,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
- /* Wa_1606931601:tgl */
- wa_masked_en(wal,
- GEN7_ROW_CHICKEN2,
- GEN12_DISABLE_EARLY_READ);
-
/*
* Wa_1409085225:tgl
* Wa_14010229206:tgl
@@ -1378,6 +1373,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
}
if (IS_TIGERLAKE(i915)) {
+ /* Wa_1606931601:tgl */
+ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+
/* Wa_1409804808:tgl */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
GEN12_PUSH_CONSTANT_DEREFERENCE_HOLD_DISABLE);
--
2.25.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 6/8] drm/i915/tgl: Add note to Wa_1607297627
2020-02-22 2:08 [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping José Roberto de Souza
` (3 preceding siblings ...)
2020-02-22 2:08 ` [Intel-gfx] [PATCH 5/8] drm/i915/tgl: Extend Wa_1606931601 for all steppings José Roberto de Souza
@ 2020-02-22 2:08 ` José Roberto de Souza
2020-02-24 16:42 ` Matt Roper
2020-02-22 2:08 ` [Intel-gfx] [PATCH 7/8] drm/i915/tgl: Add note about Wa_1607063988 José Roberto de Souza
` (4 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: José Roberto de Souza @ 2020-02-22 2:08 UTC (permalink / raw)
To: intel-gfx
Add note about the confliting information in BSpec about this WA.
BSpec: 52890
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 978a5b051ce9..bc5025c81c4f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1344,9 +1344,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN9_CTX_PREEMPT_REG,
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
- /* Wa_1607030317:tgl */
- /* Wa_1607186500:tgl */
- /* Wa_1607297627:tgl */
+ /*
+ * Wa_1607030317:tgl
+ * Wa_1607186500:tgl
+ * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2
+ * of then says it is fixed on B0 the other one says it is
+ * permanent
+ */
wa_masked_en(wal,
GEN6_RC_SLEEP_PSMI_CONTROL,
GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
--
2.25.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 7/8] drm/i915/tgl: Add note about Wa_1607063988
2020-02-22 2:08 [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping José Roberto de Souza
` (4 preceding siblings ...)
2020-02-22 2:08 ` [Intel-gfx] [PATCH 6/8] drm/i915/tgl: Add note to Wa_1607297627 José Roberto de Souza
@ 2020-02-22 2:08 ` José Roberto de Souza
2020-02-24 16:44 ` Matt Roper
2020-02-22 2:08 ` [Intel-gfx] [PATCH 8/8] drm/i915/tgl: Extend Wa_1409767108 to B0 José Roberto de Souza
` (3 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: José Roberto de Souza @ 2020-02-22 2:08 UTC (permalink / raw)
To: intel-gfx
This issue workaround in Wa_1607063988 has the same fix as
Wa_1607138336, so just adding a note in the code.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index bc5025c81c4f..cc3fbe3dfd9f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1339,7 +1339,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN9_CS_DEBUG_MODE1,
FF_DOP_CLOCK_GATE_DISABLE);
- /* Wa_1607138336:tgl */
+ /*
+ * Wa_1607138336:tgl
+ * Wa_1607063988:tgl
+ */
wa_write_or(wal,
GEN9_CTX_PREEMPT_REG,
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
--
2.25.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 8/8] drm/i915/tgl: Extend Wa_1409767108 to B0
2020-02-22 2:08 [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping José Roberto de Souza
` (5 preceding siblings ...)
2020-02-22 2:08 ` [Intel-gfx] [PATCH 7/8] drm/i915/tgl: Add note about Wa_1607063988 José Roberto de Souza
@ 2020-02-22 2:08 ` José Roberto de Souza
2020-02-24 16:49 ` Matt Roper
2020-02-22 5:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915/tgl: Extend Wa_1409825376 stepping Patchwork
` (2 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: José Roberto de Souza @ 2020-02-22 2:08 UTC (permalink / raw)
To: intel-gfx
This Wa will also be needed by B0 stepping.
BSpec: 52890
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 8ba68ec6dc24..e9af21c08ff6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4982,7 +4982,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
const struct buddy_page_mask *table;
int i;
- if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
+ if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
/* Wa_1409767108: tgl */
table = wa_1409767108_buddy_page_masks;
else
--
2.25.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915/tgl: Extend Wa_1409825376 stepping
2020-02-22 2:08 [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping José Roberto de Souza
` (6 preceding siblings ...)
2020-02-22 2:08 ` [Intel-gfx] [PATCH 8/8] drm/i915/tgl: Extend Wa_1409767108 to B0 José Roberto de Souza
@ 2020-02-22 5:03 ` Patchwork
2020-02-24 16:08 ` [Intel-gfx] [PATCH 1/8] " Matt Roper
2020-02-24 17:52 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/8] " Patchwork
9 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2020-02-22 5:03 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/8] drm/i915/tgl: Extend Wa_1409825376 stepping
URL : https://patchwork.freedesktop.org/series/73802/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7984 -> Patchwork_16675
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/index.html
Known issues
------------
Here are the changes found in Patchwork_16675 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-hsw-peppy: [PASS][1] -> [TIMEOUT][2] ([fdo#112271] / [i915#1084])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/fi-hsw-peppy/igt@gem_close_race@basic-threads.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/fi-hsw-peppy/igt@gem_close_race@basic-threads.html
- fi-byt-n2820: [PASS][3] -> [INCOMPLETE][4] ([i915#45])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/fi-byt-n2820/igt@gem_close_race@basic-threads.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/fi-byt-n2820/igt@gem_close_race@basic-threads.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [PASS][5] -> [INCOMPLETE][6] ([i915#424])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_sanitycheck:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([i915#585])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][9] -> [FAIL][10] ([i915#217])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@prime_self_import@basic-with_fd_dup:
- fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([CI#94] / [i915#402]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/fi-tgl-y/igt@prime_self_import@basic-with_fd_dup.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/fi-tgl-y/igt@prime_self_import@basic-with_fd_dup.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic:
- fi-tgl-y: [DMESG-WARN][13] ([CI#94] / [i915#402]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/fi-tgl-y/igt@gem_mmap_gtt@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/fi-tgl-y/igt@gem_mmap_gtt@basic.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [DMESG-FAIL][15] ([i915#623]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111407]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][19] ([i915#44]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#585]: https://gitlab.freedesktop.org/drm/intel/issues/585
[i915#623]: https://gitlab.freedesktop.org/drm/intel/issues/623
Participating hosts (48 -> 40)
------------------------------
Additional (4): fi-byt-j1900 fi-skl-lmem fi-gdg-551 fi-bsw-nick
Missing (12): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-ivb-3770 fi-bsw-kefka fi-blb-e6850 fi-byt-clapper fi-skl-6700k2
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7984 -> Patchwork_16675
CI-20190529: 20190529
CI_DRM_7984: ab1d770e389d9407be633b5afbe6859e0072ca9d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5458: 5f7e4ae6a91ed2c104593b8abd5b71a6cc96fc10 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16675: 4886b306e7108145337576992e1c8a4fa4a847a8 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4886b306e710 drm/i915/tgl: Extend Wa_1409767108 to B0
4e460a37a401 drm/i915/tgl: Add note about Wa_1607063988
cce9dde9f244 drm/i915/tgl: Add note to Wa_1607297627
b55a760396a9 drm/i915/tgl: Extend Wa_1606931601 for all steppings
bdb6c1fa02cf drm/i915/tgl: Add Wa_1409085225, Wa_14010229206
8b08b167819d drm/i915/tgl: Implement Wa_1806527549
28752812a817 drm/i915/tgl: Implement Wa_1409804808
26e590d36c36 drm/i915/tgl: Extend Wa_1409825376 stepping
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 3/8] drm/i915/tgl: Implement Wa_1806527549
2020-02-22 2:08 ` [Intel-gfx] [PATCH 3/8] drm/i915/tgl: Implement Wa_1806527549 José Roberto de Souza
@ 2020-02-22 8:53 ` Chris Wilson
2020-02-24 21:07 ` Souza, Jose
0 siblings, 1 reply; 19+ messages in thread
From: Chris Wilson @ 2020-02-22 8:53 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx
Quoting José Roberto de Souza (2020-02-22 02:08:10)
> This will whitelist the HIZ_CHICKEN register so mesa can disable the
> optimizations and void hang when using D16_UNORM.
But it's not added to the whitelist.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping
2020-02-22 2:08 [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping José Roberto de Souza
` (7 preceding siblings ...)
2020-02-22 5:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915/tgl: Extend Wa_1409825376 stepping Patchwork
@ 2020-02-24 16:08 ` Matt Roper
2020-02-24 18:59 ` Souza, Jose
2020-02-24 17:52 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/8] " Patchwork
9 siblings, 1 reply; 19+ messages in thread
From: Matt Roper @ 2020-02-24 16:08 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Fri, Feb 21, 2020 at 06:08:08PM -0800, José Roberto de Souza wrote:
> This workaround is only fixed in C0 stepping to extend it to B0 too.
>
> BSpec: 52890
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4305ccc4c683..57282b719ece 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1575,6 +1575,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> (IS_ICELAKE(p) && IS_REVID(p, since, until))
>
> #define TGL_REVID_A0 0x0
> +#define TGL_REVID_B0 0x1
revid 1 is CPU + GT B0, but already has display C0 stepping
incorporated. I forget...do the display workaround limits in the bspec
refer to display stepping or CPU/GT stepping?
For reference, bspec 44455.
Matt
>
> #define IS_TGL_REVID(p, since, until) \
> (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ffac0b862ca5..33149bccd117 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6852,7 +6852,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
>
> /* Wa_1409825376:tgl (pre-prod)*/
> - if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> + if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
> TGL_VRH_GATING_DIS);
> }
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 2/8] drm/i915/tgl: Implement Wa_1409804808
2020-02-22 2:08 ` [Intel-gfx] [PATCH 2/8] drm/i915/tgl: Implement Wa_1409804808 José Roberto de Souza
@ 2020-02-24 16:20 ` Matt Roper
0 siblings, 0 replies; 19+ messages in thread
From: Matt Roper @ 2020-02-24 16:20 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Fri, Feb 21, 2020 at 06:08:09PM -0800, José Roberto de Souza wrote:
> This workaround the CS not done issue on PIPE_CONTROL.
>
> BSpec: 52890
> BSpec: 46218
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 887e0dc701f7..57a5a39ee902 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1367,6 +1367,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GEN12_DISABLE_EARLY_READ);
> }
>
> + if (IS_TIGERLAKE(i915)) {
> + /* Wa_1409804808:tgl */
> + wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + GEN12_PUSH_CONSTANT_DEREFERENCE_HOLD_DISABLE);
> + }
> +
> if (IS_GEN(i915, 11)) {
> /* This is not an Wa. Enable for better image quality */
> wa_masked_en(wal,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f45b5e86ec63..cfc238ffd4ae 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9149,8 +9149,9 @@ enum {
> #define THROTTLE_12_5 (7 << 2)
> #define DISABLE_EARLY_EOT (1 << 1)
>
> -#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
> -#define GEN12_DISABLE_EARLY_READ BIT(14)
> +#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
> +#define GEN12_DISABLE_EARLY_READ BIT(14)
> +#define GEN12_PUSH_CONSTANT_DEREFERENCE_HOLD_DISABLE BIT(8)
We should probably take this opportunity to s/BIT/REG_BIT/ too.
This is also kind of a long name. You could potentially shorten some of
the words like we do for other bit names. E.g.,
GEN12_PUSH_CONST_DEREF_HOLD_DIS.. Up to you.
Otherwise,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Matt
>
> #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
> #define DOP_CLOCK_GATING_DISABLE (1 << 0)
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 4/8] drm/i915/tgl: Add Wa_1409085225, Wa_14010229206
2020-02-22 2:08 ` [Intel-gfx] [PATCH 4/8] drm/i915/tgl: Add Wa_1409085225, Wa_14010229206 José Roberto de Souza
@ 2020-02-24 16:27 ` Matt Roper
0 siblings, 0 replies; 19+ messages in thread
From: Matt Roper @ 2020-02-24 16:27 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Fri, Feb 21, 2020 at 06:08:11PM -0800, José Roberto de Souza wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
>
> Disable Push Constant buffer addition for TGL.
>
> v2: typos, add additional Wa reference
> v3: use REG_BIT macro, move to rcs_engine_wa_init, clean up commit
> message.
>
> Bspec: 52890
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index fbed5bdc9e04..e9619c493e6a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1369,6 +1369,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> wa_masked_en(wal,
> GEN7_ROW_CHICKEN2,
> GEN12_DISABLE_EARLY_READ);
> +
> + /*
> + * Wa_1409085225:tgl
> + * Wa_14010229206:tgl
> + */
> + wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
> }
>
> if (IS_TIGERLAKE(i915)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 49872a1dc7a4..78164fa9e574 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9159,6 +9159,9 @@ enum {
> #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
>
> +#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
> +#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
> +
> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 6/8] drm/i915/tgl: Add note to Wa_1607297627
2020-02-22 2:08 ` [Intel-gfx] [PATCH 6/8] drm/i915/tgl: Add note to Wa_1607297627 José Roberto de Souza
@ 2020-02-24 16:42 ` Matt Roper
0 siblings, 0 replies; 19+ messages in thread
From: Matt Roper @ 2020-02-24 16:42 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Fri, Feb 21, 2020 at 06:08:13PM -0800, José Roberto de Souza wrote:
> Add note about the confliting information in BSpec about this WA.
>
> BSpec: 52890
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 978a5b051ce9..bc5025c81c4f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1344,9 +1344,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GEN9_CTX_PREEMPT_REG,
> GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>
> - /* Wa_1607030317:tgl */
> - /* Wa_1607186500:tgl */
> - /* Wa_1607297627:tgl */
> + /*
> + * Wa_1607030317:tgl
> + * Wa_1607186500:tgl
> + * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2
> + * of then says it is fixed on B0 the other one says it is
> + * permanent
> + */
> wa_masked_en(wal,
> GEN6_RC_SLEEP_PSMI_CONTROL,
> GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 7/8] drm/i915/tgl: Add note about Wa_1607063988
2020-02-22 2:08 ` [Intel-gfx] [PATCH 7/8] drm/i915/tgl: Add note about Wa_1607063988 José Roberto de Souza
@ 2020-02-24 16:44 ` Matt Roper
0 siblings, 0 replies; 19+ messages in thread
From: Matt Roper @ 2020-02-24 16:44 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Fri, Feb 21, 2020 at 06:08:14PM -0800, José Roberto de Souza wrote:
> This issue workaround in Wa_1607063988 has the same fix as
> Wa_1607138336, so just adding a note in the code.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index bc5025c81c4f..cc3fbe3dfd9f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1339,7 +1339,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GEN9_CS_DEBUG_MODE1,
> FF_DOP_CLOCK_GATE_DISABLE);
>
> - /* Wa_1607138336:tgl */
> + /*
> + * Wa_1607138336:tgl
> + * Wa_1607063988:tgl
> + */
> wa_write_or(wal,
> GEN9_CTX_PREEMPT_REG,
> GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 8/8] drm/i915/tgl: Extend Wa_1409767108 to B0
2020-02-22 2:08 ` [Intel-gfx] [PATCH 8/8] drm/i915/tgl: Extend Wa_1409767108 to B0 José Roberto de Souza
@ 2020-02-24 16:49 ` Matt Roper
0 siblings, 0 replies; 19+ messages in thread
From: Matt Roper @ 2020-02-24 16:49 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Fri, Feb 21, 2020 at 06:08:15PM -0800, José Roberto de Souza wrote:
> This Wa will also be needed by B0 stepping.
>
> BSpec: 52890
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Same question as patch #1 --- does the bspec's stepping for display
workarounds reflect the CPU+GT stepping or the display stepping? If
it's the display stepping, then I believe we should already be covered.
Matt
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 8ba68ec6dc24..e9af21c08ff6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4982,7 +4982,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> const struct buddy_page_mask *table;
> int i;
>
> - if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> + if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> /* Wa_1409767108: tgl */
> table = wa_1409767108_buddy_page_masks;
> else
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/8] drm/i915/tgl: Extend Wa_1409825376 stepping
2020-02-22 2:08 [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping José Roberto de Souza
` (8 preceding siblings ...)
2020-02-24 16:08 ` [Intel-gfx] [PATCH 1/8] " Matt Roper
@ 2020-02-24 17:52 ` Patchwork
9 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2020-02-24 17:52 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/8] drm/i915/tgl: Extend Wa_1409825376 stepping
URL : https://patchwork.freedesktop.org/series/73802/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7984_full -> Patchwork_16675_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_16675_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb1/igt@gem_busy@busy-vcs1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb8/igt@gem_busy@busy-vcs1.html
* igt@gem_busy@close-race:
- shard-hsw: [PASS][3] -> [TIMEOUT][4] ([fdo#112271] / [i915#1084])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-hsw5/igt@gem_busy@close-race.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-hsw1/igt@gem_busy@close-race.html
* igt@gem_ctx_isolation@vcs0-s3:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-apl6/igt@gem_ctx_isolation@vcs0-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-apl6/igt@gem_ctx_isolation@vcs0-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110841])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +24 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb2/igt@gem_exec_schedule@out-order-bsd2.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb6/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +6 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb7/igt@gem_exec_schedule@preemptive-hang-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-hsw: [PASS][13] -> [FAIL][14] ([i915#694])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-hsw2/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-hsw5/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [PASS][15] -> [FAIL][16] ([i915#644])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-apl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-apl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#72])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@modeset-vs-vblank-race:
- shard-glk: [PASS][21] -> [FAIL][22] ([i915#407])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-glk7/igt@kms_flip@modeset-vs-vblank-race.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-glk4/igt@kms_flip@modeset-vs-vblank-race.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-glk: [PASS][23] -> [FAIL][24] ([i915#49])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-glk9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-glk9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-skl: [PASS][27] -> [DMESG-WARN][28] ([IGT#6])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-skl8/igt@kms_plane_multiple@atomic-pipe-c-tiling-y.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-skl7/igt@kms_plane_multiple@atomic-pipe-c-tiling-y.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-skl: [PASS][31] -> [FAIL][32] ([i915#31])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-skl7/igt@kms_setmode@basic.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-skl2/igt@kms_setmode@basic.html
* igt@sw_sync@sync_multi_producer_single_consumer:
- shard-snb: [PASS][33] -> [TIMEOUT][34] ([fdo#112271])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-snb2/igt@sw_sync@sync_multi_producer_single_consumer.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-snb1/igt@sw_sync@sync_multi_producer_single_consumer.html
- shard-iclb: [PASS][35] -> [TIMEOUT][36] ([fdo#112271])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb2/igt@sw_sync@sync_multi_producer_single_consumer.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb8/igt@sw_sync@sync_multi_producer_single_consumer.html
#### Possible fixes ####
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [SKIP][37] ([fdo#112080]) -> [PASS][38] +13 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb8/igt@gem_exec_parallel@vcs1-fds.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb4/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_reuse@baggage:
- shard-apl: [TIMEOUT][39] ([fdo#112271]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-apl7/igt@gem_exec_reuse@baggage.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-apl7/igt@gem_exec_reuse@baggage.html
* igt@gem_exec_schedule@pi-shared-iova-bsd:
- shard-iclb: [SKIP][41] ([i915#677]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb1/igt@gem_exec_schedule@pi-shared-iova-bsd.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb8/igt@gem_exec_schedule@pi-shared-iova-bsd.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][43] ([fdo#112146]) -> [PASS][44] +9 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [FAIL][45] ([i915#644]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-glk6/igt@gem_ppgtt@flink-and-close-vma-leak.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
- shard-skl: [FAIL][47] ([i915#644]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-skl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-skl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_pwrite@huge-cpu-fbr:
- shard-hsw: [TIMEOUT][49] ([fdo#112271]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-hsw5/igt@gem_pwrite@huge-cpu-fbr.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-hsw1/igt@gem_pwrite@huge-cpu-fbr.html
* igt@gem_tiled_blits@interruptible:
- shard-glk: [TIMEOUT][51] ([fdo#112271]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-glk6/igt@gem_tiled_blits@interruptible.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-glk6/igt@gem_tiled_blits@interruptible.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-glk: [FAIL][53] -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-glk4/igt@gem_userptr_blits@unsync-unmap-cycles.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-glk1/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen7_exec_parse@basic-offset:
- shard-hsw: [FAIL][55] ([i915#694]) -> [PASS][56] +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-hsw4/igt@gen7_exec_parse@basic-offset.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-hsw7/igt@gen7_exec_parse@basic-offset.html
* igt@i915_pm_dc@dc5-dpms:
- shard-iclb: [FAIL][57] ([i915#447]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb6/igt@i915_pm_dc@dc5-dpms.html
* igt@i915_pm_rps@reset:
- shard-iclb: [FAIL][59] ([i915#413]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb5/igt@i915_pm_rps@reset.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb4/igt@i915_pm_rps@reset.html
* igt@i915_selftest@mock_buddy:
- shard-skl: [INCOMPLETE][61] -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-skl3/igt@i915_selftest@mock_buddy.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-skl3/igt@i915_selftest@mock_buddy.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +3 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [FAIL][65] ([i915#79]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-glk6/igt@kms_flip@flip-vs-expired-vblank.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-glk6/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-glk: [FAIL][67] ([i915#34]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-glk5/igt@kms_flip@plain-flip-ts-check-interruptible.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-glk8/igt@kms_flip@plain-flip-ts-check-interruptible.html
- shard-kbl: [INCOMPLETE][69] ([CI#80] / [fdo#103665]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-kbl4/igt@kms_flip@plain-flip-ts-check-interruptible.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-kbl3/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-glk: [FAIL][71] ([i915#49]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-glk7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [DMESG-WARN][73] ([i915#180]) -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: [INCOMPLETE][75] ([i915#69]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-skl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-tglb: [SKIP][77] ([i915#668]) -> [PASS][78] +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-tglb5/igt@kms_psr@psr2_primary_mmap_gtt.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-tglb8/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [SKIP][79] ([fdo#109441]) -> [PASS][80] +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb8/igt@kms_psr@psr2_suspend.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb2/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][81] ([i915#31]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-kbl1/igt@kms_setmode@basic.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-kbl7/igt@kms_setmode@basic.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][83] ([fdo#109276]) -> [PASS][84] +21 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb5/igt@prime_vgem@fence-wait-bsd2.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][85] ([fdo#112080]) -> [FAIL][86] ([IGT#28])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-iclb8/igt@gem_ctx_isolation@vcs1-nonpriv.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_exec_reuse@baggage:
- shard-skl: [TIMEOUT][87] ([fdo#112271]) -> [TIMEOUT][88] ([fdo#112271] / [i915#1084])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-skl5/igt@gem_exec_reuse@baggage.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-skl3/igt@gem_exec_reuse@baggage.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [TIMEOUT][89] ([fdo#112271]) -> [INCOMPLETE][90] ([i915#69])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-skl1/igt@gem_softpin@noreloc-s3.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-skl5/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [FAIL][91] ([i915#454]) -> [SKIP][92] ([i915#468])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-tglb8/igt@i915_pm_dc@dc6-dpms.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_selftest@live_gt_lrc:
- shard-tglb: [DMESG-FAIL][93] ([i915#1233]) -> [INCOMPLETE][94] ([i915#1233])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-tglb1/igt@i915_selftest@live_gt_lrc.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-tglb6/igt@i915_selftest@live_gt_lrc.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
- shard-hsw: [INCOMPLETE][95] ([CI#80] / [i915#61]) -> [INCOMPLETE][96] ([i915#61])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7984/shard-hsw7/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/shard-hsw8/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7984 -> Patchwork_16675
CI-20190529: 20190529
CI_DRM_7984: ab1d770e389d9407be633b5afbe6859e0072ca9d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5458: 5f7e4ae6a91ed2c104593b8abd5b71a6cc96fc10 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16675: 4886b306e7108145337576992e1c8a4fa4a847a8 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16675/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping
2020-02-24 16:08 ` [Intel-gfx] [PATCH 1/8] " Matt Roper
@ 2020-02-24 18:59 ` Souza, Jose
0 siblings, 0 replies; 19+ messages in thread
From: Souza, Jose @ 2020-02-24 18:59 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx
On Mon, 2020-02-24 at 08:08 -0800, Matt Roper wrote:
> On Fri, Feb 21, 2020 at 06:08:08PM -0800, José Roberto de Souza
> wrote:
> > This workaround is only fixed in C0 stepping to extend it to B0
> > too.
> >
> > BSpec: 52890
> > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 2 +-
> > 2 files changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 4305ccc4c683..57282b719ece 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1575,6 +1575,7 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,
> > (IS_ICELAKE(p) && IS_REVID(p, since, until))
> >
> > #define TGL_REVID_A0 0x0
> > +#define TGL_REVID_B0 0x1
>
> revid 1 is CPU + GT B0, but already has display C0 stepping
> incorporated. I forget...do the display workaround limits in the
> bspec
> refer to display stepping or CPU/GT stepping?
Most of platforms don't have the display stepping column so I always
compare to GT one.
>
> For reference, bspec 44455.
>
>
> Matt
>
> >
> > #define IS_TGL_REVID(p, since, until) \
> > (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index ffac0b862ca5..33149bccd117 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6852,7 +6852,7 @@ static void tgl_init_clock_gating(struct
> > drm_i915_private *dev_priv)
> > I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
> >
> > /* Wa_1409825376:tgl (pre-prod)*/
> > - if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> > + if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> > I915_WRITE(GEN9_CLKGATE_DIS_3,
> > I915_READ(GEN9_CLKGATE_DIS_3) |
> > TGL_VRH_GATING_DIS);
> > }
> > --
> > 2.25.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 3/8] drm/i915/tgl: Implement Wa_1806527549
2020-02-22 8:53 ` Chris Wilson
@ 2020-02-24 21:07 ` Souza, Jose
0 siblings, 0 replies; 19+ messages in thread
From: Souza, Jose @ 2020-02-24 21:07 UTC (permalink / raw)
To: intel-gfx, chris
Ouch! Thanks fixed
On Sat, 2020-02-22 at 08:53 +0000, Chris Wilson wrote:
> Quoting José Roberto de Souza (2020-02-22 02:08:10)
> > This will whitelist the HIZ_CHICKEN register so mesa can disable
> > the
> > optimizations and void hang when using D16_UNORM.
>
> But it's not added to the whitelist.
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2020-02-24 21:07 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-22 2:08 [Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping José Roberto de Souza
2020-02-22 2:08 ` [Intel-gfx] [PATCH 2/8] drm/i915/tgl: Implement Wa_1409804808 José Roberto de Souza
2020-02-24 16:20 ` Matt Roper
2020-02-22 2:08 ` [Intel-gfx] [PATCH 3/8] drm/i915/tgl: Implement Wa_1806527549 José Roberto de Souza
2020-02-22 8:53 ` Chris Wilson
2020-02-24 21:07 ` Souza, Jose
2020-02-22 2:08 ` [Intel-gfx] [PATCH 4/8] drm/i915/tgl: Add Wa_1409085225, Wa_14010229206 José Roberto de Souza
2020-02-24 16:27 ` Matt Roper
2020-02-22 2:08 ` [Intel-gfx] [PATCH 5/8] drm/i915/tgl: Extend Wa_1606931601 for all steppings José Roberto de Souza
2020-02-22 2:08 ` [Intel-gfx] [PATCH 6/8] drm/i915/tgl: Add note to Wa_1607297627 José Roberto de Souza
2020-02-24 16:42 ` Matt Roper
2020-02-22 2:08 ` [Intel-gfx] [PATCH 7/8] drm/i915/tgl: Add note about Wa_1607063988 José Roberto de Souza
2020-02-24 16:44 ` Matt Roper
2020-02-22 2:08 ` [Intel-gfx] [PATCH 8/8] drm/i915/tgl: Extend Wa_1409767108 to B0 José Roberto de Souza
2020-02-24 16:49 ` Matt Roper
2020-02-22 5:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915/tgl: Extend Wa_1409825376 stepping Patchwork
2020-02-24 16:08 ` [Intel-gfx] [PATCH 1/8] " Matt Roper
2020-02-24 18:59 ` Souza, Jose
2020-02-24 17:52 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/8] " Patchwork
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