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From: Babu Moger <babu.moger@amd.com>
To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com,
	pbonzini@redhat.com, rth@twiddle.net, mst@redhat.com,
	imammedo@redhat.com
Cc: qemu-devel@nongnu.org
Subject: [PATCH v5 03/16] hw/i386: Consolidate topology functions
Date: Tue, 03 Mar 2020 13:57:11 -0600	[thread overview]
Message-ID: <158326543195.40452.7437947098625099601.stgit@naples-babu.amd.com> (raw)
In-Reply-To: <158326531474.40452.11433722850425537745.stgit@naples-babu.amd.com>

Now that we have all the parameters in X86CPUTopoInfo, we can just
pass the structure to calculate the offsets and width.

Signed-off-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
 include/hw/i386/topology.h |   68 ++++++++++++++------------------------------
 target/i386/cpu.c          |   23 +++++++--------
 2 files changed, 32 insertions(+), 59 deletions(-)

diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 7ea507f376..ba52d49079 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -69,56 +69,42 @@ static unsigned apicid_bitwidth_for_count(unsigned count)
 
 /* Bit width of the SMT_ID (thread ID) field on the APIC ID
  */
-static inline unsigned apicid_smt_width(unsigned nr_dies,
-                                        unsigned nr_cores,
-                                        unsigned nr_threads)
+static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
 {
-    return apicid_bitwidth_for_count(nr_threads);
+    return apicid_bitwidth_for_count(topo_info->threads_per_core);
 }
 
 /* Bit width of the Core_ID field
  */
-static inline unsigned apicid_core_width(unsigned nr_dies,
-                                         unsigned nr_cores,
-                                         unsigned nr_threads)
+static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
 {
-    return apicid_bitwidth_for_count(nr_cores);
+    return apicid_bitwidth_for_count(topo_info->cores_per_die);
 }
 
 /* Bit width of the Die_ID field */
-static inline unsigned apicid_die_width(unsigned nr_dies,
-                                        unsigned nr_cores,
-                                        unsigned nr_threads)
+static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info)
 {
-    return apicid_bitwidth_for_count(nr_dies);
+    return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
 }
 
 /* Bit offset of the Core_ID field
  */
-static inline unsigned apicid_core_offset(unsigned nr_dies,
-                                          unsigned nr_cores,
-                                          unsigned nr_threads)
+static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
 {
-    return apicid_smt_width(nr_dies, nr_cores, nr_threads);
+    return apicid_smt_width(topo_info);
 }
 
 /* Bit offset of the Die_ID field */
-static inline unsigned apicid_die_offset(unsigned nr_dies,
-                                          unsigned nr_cores,
-                                           unsigned nr_threads)
+static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info)
 {
-    return apicid_core_offset(nr_dies, nr_cores, nr_threads) +
-           apicid_core_width(nr_dies, nr_cores, nr_threads);
+    return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
 }
 
 /* Bit offset of the Pkg_ID (socket ID) field
  */
-static inline unsigned apicid_pkg_offset(unsigned nr_dies,
-                                         unsigned nr_cores,
-                                         unsigned nr_threads)
+static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
 {
-    return apicid_die_offset(nr_dies, nr_cores, nr_threads) +
-           apicid_die_width(nr_dies, nr_cores, nr_threads);
+    return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
 }
 
 /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
@@ -128,16 +114,9 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies,
 static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
                                              const X86CPUTopoIDs *topo_ids)
 {
-    unsigned nr_dies = topo_info->dies_per_pkg;
-    unsigned nr_cores = topo_info->cores_per_die;
-    unsigned nr_threads = topo_info->threads_per_core;
-
-    return (topo_ids->pkg_id  <<
-               apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) |
-           (topo_ids->die_id  <<
-               apicid_die_offset(nr_dies, nr_cores, nr_threads)) |
-           (topo_ids->core_id <<
-               apicid_core_offset(nr_dies, nr_cores, nr_threads)) |
+    return (topo_ids->pkg_id  << apicid_pkg_offset(topo_info)) |
+           (topo_ids->die_id  << apicid_die_offset(topo_info)) |
+           (topo_ids->core_id << apicid_core_offset(topo_info)) |
            topo_ids->smt_id;
 }
 
@@ -165,20 +144,15 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
                                             X86CPUTopoInfo *topo_info,
                                             X86CPUTopoIDs *topo_ids)
 {
-    unsigned nr_dies = topo_info->dies_per_pkg;
-    unsigned nr_cores = topo_info->cores_per_die;
-    unsigned nr_threads = topo_info->threads_per_core;
-
     topo_ids->smt_id = apicid &
-            ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads));
+            ~(0xFFFFFFFFUL << apicid_smt_width(topo_info));
     topo_ids->core_id =
-            (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) &
-            ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_threads));
+            (apicid >> apicid_core_offset(topo_info)) &
+            ~(0xFFFFFFFFUL << apicid_core_width(topo_info));
     topo_ids->die_id =
-            (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) &
-            ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threads));
-    topo_ids->pkg_id =
-            apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads);
+            (apicid >> apicid_die_offset(topo_info)) &
+            ~(0xFFFFFFFFUL << apicid_die_width(topo_info));
+    topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info);
 }
 
 /* Make APIC ID for the CPU 'cpu_index'
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 92fafa2659..1263271edd 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5369,6 +5369,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
     uint32_t die_offset;
     uint32_t limit;
     uint32_t signature[3];
+    X86CPUTopoInfo topo_info;
+
+    topo_info.dies_per_pkg = env->nr_dies;
+    topo_info.cores_per_die = cs->nr_cores;
+    topo_info.threads_per_core = cs->nr_threads;
 
     /* Calculate & apply limits for different index ranges */
     if (index >= 0xC0000000) {
@@ -5455,8 +5460,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
                                     eax, ebx, ecx, edx);
                 break;
             case 3: /* L3 cache info */
-                die_offset = apicid_die_offset(env->nr_dies,
-                                        cs->nr_cores, cs->nr_threads);
+                die_offset = apicid_die_offset(&topo_info);
                 if (cpu->enable_l3_cache) {
                     encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
                                         (1 << die_offset), cs->nr_cores,
@@ -5547,14 +5551,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
 
         switch (count) {
         case 0:
-            *eax = apicid_core_offset(env->nr_dies,
-                                      cs->nr_cores, cs->nr_threads);
+            *eax = apicid_core_offset(&topo_info);
             *ebx = cs->nr_threads;
             *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
             break;
         case 1:
-            *eax = apicid_pkg_offset(env->nr_dies,
-                                     cs->nr_cores, cs->nr_threads);
+            *eax = apicid_pkg_offset(&topo_info);
             *ebx = cs->nr_cores * cs->nr_threads;
             *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
             break;
@@ -5578,20 +5580,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
         *edx = cpu->apic_id;
         switch (count) {
         case 0:
-            *eax = apicid_core_offset(env->nr_dies, cs->nr_cores,
-                                                    cs->nr_threads);
+            *eax = apicid_core_offset(&topo_info);
             *ebx = cs->nr_threads;
             *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
             break;
         case 1:
-            *eax = apicid_die_offset(env->nr_dies, cs->nr_cores,
-                                                   cs->nr_threads);
+            *eax = apicid_die_offset(&topo_info);
             *ebx = cs->nr_cores * cs->nr_threads;
             *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
             break;
         case 2:
-            *eax = apicid_pkg_offset(env->nr_dies, cs->nr_cores,
-                                                   cs->nr_threads);
+            *eax = apicid_pkg_offset(&topo_info);
             *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
             *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
             break;



  parent reply	other threads:[~2020-03-03 19:58 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
2020-03-03 19:56 ` [PATCH v5 01/16] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs Babu Moger
2020-03-03 19:57 ` [PATCH v5 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info Babu Moger
2020-03-09 14:10   ` Igor Mammedov
2020-03-10 23:04   ` Eduardo Habkost
2020-03-03 19:57 ` Babu Moger [this message]
2020-03-03 19:57 ` [PATCH v5 04/16] machine: Add SMP Sockets in CpuTopology Babu Moger
2020-03-09 14:17   ` Igor Mammedov
2020-03-09 18:01     ` Babu Moger
2020-03-03 19:57 ` [PATCH v5 05/16] hw/i386: Remove unnecessary initialization in x86_cpu_new Babu Moger
2020-03-09 14:18   ` Igor Mammedov
2020-03-03 19:57 ` [PATCH v5 06/16] hw/i386: Update structures to save the number of nodes per package Babu Moger
2020-03-09 14:26   ` Igor Mammedov
2020-03-03 19:57 ` [PATCH v5 07/16] hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids Babu Moger
2020-03-03 19:57 ` [PATCH v5 08/16] hw/386: Add EPYC mode topology decoding functions Babu Moger
2020-03-03 19:57 ` [PATCH v5 09/16] target/i386: Cleanup and use the EPYC mode topology functions Babu Moger
2020-03-03 19:57 ` [PATCH v5 10/16] hw/i386: Introduce apicid functions inside X86MachineState Babu Moger
2020-03-09 14:34   ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition Babu Moger
2020-03-09 14:49   ` Igor Mammedov
2020-03-09 14:55     ` Igor Mammedov
2020-03-09 19:04     ` Babu Moger
2020-03-10  8:27       ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 12/16] hw/i386: Use the apicid handlers from X86MachineState Babu Moger
2020-03-09 15:01   ` Igor Mammedov
2020-03-09 19:08     ` Babu Moger
2020-03-10  8:31       ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 13/16] target/i386: Add EPYC model specific handlers Babu Moger
2020-03-09 15:03   ` Igor Mammedov
2020-03-09 19:12     ` Babu Moger
2020-03-10  8:25       ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 14/16] hw/i386: Move arch_id decode inside x86_cpus_init Babu Moger
2020-03-09 15:21   ` Igor Mammedov
2020-03-09 19:31     ` Babu Moger
2020-03-10  8:35       ` Igor Mammedov
2020-03-10 20:05         ` Babu Moger
2020-03-03 19:58 ` [PATCH v5 15/16] i386: Fix pkg_id offset for EPYC cpu models Babu Moger
2020-03-09 15:22   ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 16/16] tests: Update the Unit tests Babu Moger
2020-03-10 23:06   ` Eduardo Habkost
2020-03-10 23:09     ` Moger, Babu
2020-03-08 13:25 ` [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Michael S. Tsirkin
2020-03-09 17:50   ` Babu Moger
2020-03-10  8:40 ` Igor Mammedov
2020-03-10 20:07   ` Babu Moger

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