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Tue, 3 Mar 2020 19:57:51 +0000 Subject: [PATCH v5 09/16] target/i386: Cleanup and use the EPYC mode topology functions From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, pbonzini@redhat.com, rth@twiddle.net, mst@redhat.com, imammedo@redhat.com Date: Tue, 03 Mar 2020 13:57:49 -0600 Message-ID: <158326546983.40452.10693492138041061735.stgit@naples-babu.amd.com> In-Reply-To: <158326531474.40452.11433722850425537745.stgit@naples-babu.amd.com> References: <158326531474.40452.11433722850425537745.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: DM6PR07CA0053.namprd07.prod.outlook.com (2603:10b6:5:74::30) To SN1PR12MB2560.namprd12.prod.outlook.com (2603:10b6:802:26::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from naples-babu.amd.com (165.204.78.2) by DM6PR07CA0053.namprd07.prod.outlook.com (2603:10b6:5:74::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: 6x8oZPDUw8pGLp77LBw50l+RsuFf3zFXJH7BtwO785zo3YOEM7JPYqf7hL2UNPPUoW2cRXY0p+FLeRPLsX9a9ndroJzq1QJqy1FzLikujvrigaR04ye/23139YqXJaw/lAqCkrQEKLspcWd+ueZnCXuke2h57O2nAMI3GNN87GIH111oPxg7OMAlxjcUvM6k+679P7qbCBXV6FZ4xWSYLcjPK9RxUtzDO5u/9lCD746iyDUeTbJl1MWRbhvt0j3GDPjUiyj79AtggL2TUceQAVxCsebgMkA/jWDcppI4ajLLBWIYjMayUAvLahI0hcgo1mM0DOq/Dyo0hcp1l2Uw/cBdb+1SuZYvkNbaEqmCNgD+yDl4+E/jPI0by8Ux6emvr2E6JT6ubJoCOX4EoXuQRwCyZlIHKeqhJoaXnswDRpMoPigJMB1SDv3AIDYAi2SD X-MS-Exchange-AntiSpam-MessageData: yDs3lVryNF8/rKOYUzw4Ae4Vlh0IuIh5sPkCjk5mwNtHao9tNdMi+dfBzPthiYsdmHa7Z1ZD6Lq4xsedUeI3QSDmIr+uXsfjkvL24/aGSAJOSdy65+o7eOwzfxzFknjANqNbPMVEu6/9bIigodtB1Q== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e1c602cb-f0e8-4e18-9026-08d7bfad27b8 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2020 19:57:51.4897 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Hqsyc2kmQAwyVBE23p2w2J9aCL6QbMwNfy8hPw7AfCbrAy73eMeC9WJoveQwNRBr X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB2573 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 40.107.68.58 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Use the new functions from topology.h and delete the unused code. Given the sockets, nodes, cores and threads, the new functions generate apic id for E= PYC mode. Removes all the hardcoded values. Signed-off-by: Babu Moger --- target/i386/cpu.c | 162 +++++++++++--------------------------------------= ---- 1 file changed, 35 insertions(+), 127 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 40670f8aca..c75cf744ab 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -338,68 +338,15 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *= l2, } } =20 -/* - * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E - * Please refer to the AMD64 Architecture Programmer=E2=80=99s Manual Volu= me 3. - * Define the constants to build the cpu topology. Right now, TOPOEXT - * feature is enabled only on EPYC. So, these constants are based on - * EPYC supported configurations. We may need to handle the cases if - * these values change in future. - */ -/* Maximum core complexes in a node */ -#define MAX_CCX 2 -/* Maximum cores in a core complex */ -#define MAX_CORES_IN_CCX 4 -/* Maximum cores in a node */ -#define MAX_CORES_IN_NODE 8 -/* Maximum nodes in a socket */ -#define MAX_NODES_PER_SOCKET 4 - -/* - * Figure out the number of nodes required to build this config. - * Max cores in a node is 8 - */ -static int nodes_in_socket(int nr_cores) -{ - int nodes; - - nodes =3D DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE); - - /* Hardware does not support config with 3 nodes, return 4 in that case= */ - return (nodes =3D=3D 3) ? 4 : nodes; -} - -/* - * Decide the number of cores in a core complex with the given nr_cores us= ing - * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE an= d - * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible - * L3 cache is shared across all cores in a core complex. So, this will al= so - * tell us how many cores are sharing the L3 cache. - */ -static int cores_in_core_complex(int nr_cores) -{ - int nodes; - - /* Check if we can fit all the cores in one core complex */ - if (nr_cores <=3D MAX_CORES_IN_CCX) { - return nr_cores; - } - /* Get the number of nodes required to build this config */ - nodes =3D nodes_in_socket(nr_cores); - - /* - * Divide the cores accros all the core complexes - * Return rounded up value - */ - return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX); -} - /* Encode cache info for CPUID[8000001D] */ -static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, - uint32_t *eax, uint32_t *ebx, - uint32_t *ecx, uint32_t *edx) +static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, + X86CPUTopoInfo *topo_info, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) { uint32_t l3_cores; + unsigned nodes =3D MAX(topo_info->nodes_per_pkg, 1); + assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 @@ -408,10 +355,13 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, CPUState *cs, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_cores =3D cores_in_core_complex(cs->nr_cores); - *eax |=3D ((l3_cores * cs->nr_threads) - 1) << 14; + l3_cores =3D DIV_ROUND_UP((topo_info->dies_per_pkg * + topo_info->cores_per_die * + topo_info->threads_per_core), + nodes); + *eax |=3D (l3_cores - 1) << 14; } else { - *eax |=3D ((cs->nr_threads - 1) << 14); + *eax |=3D ((topo_info->threads_per_core - 1) << 14); } =20 assert(cache->line_size > 0); @@ -431,55 +381,17 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, CPUState *cs, (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); } =20 -/* Data structure to hold the configuration info for a given core index */ -struct core_topology { - /* core complex id of the current core index */ - int ccx_id; - /* - * Adjusted core index for this core in the topology - * This can be 0,1,2,3 with max 4 cores in a core complex - */ - int core_id; - /* Node id for this core index */ - int node_id; - /* Number of nodes in this config */ - int num_nodes; -}; - -/* - * Build the configuration closely match the EPYC hardware. Using the EPYC - * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_= NODE) - * right now. This could change in future. - * nr_cores : Total number of cores in the config - * core_id : Core index of the current CPU - * topo : Data structure to hold all the config info for this core ind= ex - */ -static void build_core_topology(int nr_cores, int core_id, - struct core_topology *topo) -{ - int nodes, cores_in_ccx; - - /* First get the number of nodes required */ - nodes =3D nodes_in_socket(nr_cores); - - cores_in_ccx =3D cores_in_core_complex(nr_cores); - - topo->node_id =3D core_id / (cores_in_ccx * MAX_CCX); - topo->ccx_id =3D (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx; - topo->core_id =3D core_id % cores_in_ccx; - topo->num_nodes =3D nodes; -} - /* Encode cache info for CPUID[8000001E] */ -static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, +static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *c= pu, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - struct core_topology topo =3D {0}; - unsigned long nodes; + X86CPUTopoIDs topo_ids =3D {0}; + unsigned long nodes =3D MAX(topo_info->nodes_per_pkg, 1); int shift; =20 - build_core_topology(cs->nr_cores, cpu->core_id, &topo); + x86_topo_ids_from_apicid_epyc(cpu->apic_id, topo_info, &topo_ids); + *eax =3D cpu->apic_id; /* * CPUID_Fn8000001E_EBX @@ -496,12 +408,8 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X8= 6CPU *cpu, * 3 Core complex id * 1:0 Core id */ - if (cs->nr_threads - 1) { - *ebx =3D ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) | - (topo.ccx_id << 2) | topo.core_id; - } else { - *ebx =3D (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id; - } + *ebx =3D ((topo_info->threads_per_core - 1) << 8) | (topo_ids.node_id = << 3) | + (topo_ids.core_id); /* * CPUID_Fn8000001E_ECX * 31:11 Reserved @@ -510,9 +418,9 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86= CPU *cpu, * 2 Socket id * 1:0 Node id */ - if (topo.num_nodes <=3D 4) { - *ecx =3D ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) | - topo.node_id; + + if (nodes <=3D 4) { + *ecx =3D ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.no= de_id; } else { /* * Node id fix up. Actual hardware supports up to 4 nodes. But wit= h @@ -527,10 +435,10 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X= 86CPU *cpu, * number of nodes. find_last_bit returns last set bit(0 based). L= eft * shift(+1) the socket id to represent all the nodes. */ - nodes =3D topo.num_nodes - 1; + nodes -=3D 1; shift =3D find_last_bit(&nodes, 8); - *ecx =3D ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift += 1)) | - topo.node_id; + *ecx =3D (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) | + topo_ids.node_id; } *edx =3D 0; } @@ -5371,6 +5279,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, uint32_t signature[3]; X86CPUTopoInfo topo_info; =20 + topo_info.nodes_per_pkg =3D env->nr_nodes; topo_info.dies_per_pkg =3D env->nr_dies; topo_info.cores_per_die =3D cs->nr_cores; topo_info.threads_per_core =3D cs->nr_threads; @@ -5790,20 +5699,20 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, } switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, + &topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, + &topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, + &topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, + &topo_info, eax, ebx, ecx, edx); break; default: /* end of info */ *eax =3D *ebx =3D *ecx =3D *edx =3D 0; @@ -5812,8 +5721,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 0x8000001E: assert(cpu->core_id <=3D 255); - encode_topo_cpuid8000001e(cs, cpu, - eax, ebx, ecx, edx); + encode_topo_cpuid8000001e(&topo_info, cpu, eax, ebx, ecx, edx); break; case 0xC0000000: *eax =3D env->cpuid_xlevel2;