From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.4 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7DE2C18E5A for ; Wed, 11 Mar 2020 09:22:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9B1C820828 for ; Wed, 11 Mar 2020 09:22:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="XRTznKKH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728637AbgCKJWb (ORCPT ); Wed, 11 Mar 2020 05:22:31 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:4126 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726097AbgCKJWb (ORCPT ); Wed, 11 Mar 2020 05:22:31 -0400 X-UUID: 9c83dbceb3bb44c6bfdc248612f0c23f-20200311 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=YWynqqGFWrui+bPw8+eUdxbiLNv0tlC1GONhbH/mI+0=; b=XRTznKKHAFsg9QE1mAbgUxIFtukPH+quc0nt04/gwuBh3OKbgmYKWh3EigUYhv/qvykIRTsC1YMUjaQfxthivZGY+3vckBtNGwsNQknN436UPCz8QZ20/Al/YmFIL3OS7gV1IJbnP9lALGG7hiRY+Y0jovnN1pXKayg74URbXGI=; X-UUID: 9c83dbceb3bb44c6bfdc248612f0c23f-20200311 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1485664839; Wed, 11 Mar 2020 17:22:25 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 11 Mar 2020 17:21:26 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 11 Mar 2020 17:22:32 +0800 Message-ID: <1583918544.19248.69.camel@mtkswgap22> Subject: Re: [PATCH 2/2] ASoC: codec: mediatek: add mt6359 codec driver From: Eason Yen To: Mark Brown CC: Matthias Brugger , , , , , Date: Wed, 11 Mar 2020 17:22:24 +0800 In-Reply-To: <20200309131346.GF4101@sirena.org.uk> References: <1583465622-16628-1-git-send-email-eason.yen@mediatek.com> <1583465622-16628-3-git-send-email-eason.yen@mediatek.com> <20200309131346.GF4101@sirena.org.uk> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org RGVhciBNYXJrLA0KDQoJVGhhbmtzIGZvciB5b3VyIGF0dGVudGl2ZSByZXZpZXcuDQoJVGhlIGZv bGxvd2luZyBpcyBteSBmZWVkYmFjay4NCglQbGVhc2Uga2luZGx5IGdpdmUgc3VnZ2VzdGlvbiwg dGhhbmtzLg0KDQpPbiBNb24sIDIwMjAtMDMtMDkgYXQgMTM6MTMgKzAwMDAsIE1hcmsgQnJvd24g d3JvdGU6DQo+IE9uIEZyaSwgTWFyIDA2LCAyMDIwIGF0IDExOjMzOjQyQU0gKzA4MDAsIEVhc29u IFllbiB3cm90ZToNCj4gDQo+ID4gK3N0YXRpYyB2b2lkIGNhcHR1cmVfZ3Bpb19yZXNldChzdHJ1 Y3QgbXQ2MzU5X3ByaXYgKnByaXYpDQo+ID4gK3sNCj4gPiArCS8qIHNldCBwYWRfYXVkXypfbWlz byB0byBHUElPIG1vZGUgYW5kIGRpciBpbnB1dA0KPiA+ICsJICogcmVhc29uOg0KPiA+ICsJICog cGFkX2F1ZF9jbGtfbWlzbywgYmVjYXVzZSB3aGVuIHBsYXliYWNrIG9ubHkgdGhlIG1pc29fY2xr DQo+ID4gKwkgKiB3aWxsIGFsc28gaGF2ZSAyNm0sIHNvIHdpbGwgaGF2ZSBwb3dlciBsZWFrDQo+ ID4gKwkgKiBwYWRfYXVkX2RhdF9taXNvKiwgYmVjYXVzZSB0aGUgcGluIGlzIHVzZWQgYXMgYm9v dCBzdHJhcA0KPiA+ICsJICovDQo+IA0KPiBUaGlzIGxvb2tzIGxpa2UgdGhpbmdzIHRoYXQgbWln aHQgYmUgYmV0dGVyIGV4cG9zZWQgdmlhIHBpbmN0cmwgYW5kDQo+IGdwaW9saWIgZm9yIGJvYXJk IHNwZWNpZmljIGNvbmZpZ3VyYXRpb24gLSB3aGF0IGV4YWN0bHkgYXJlIHRoZXNlIEdQSU9zDQo+ IGRvaW5nPyAgQSBsb3Qgb2YgdGhpcyBjb2RlIGxvb2tzIGxpa2UgaXQgbWlnaHQgYmUgYm9hcmQg c3BlY2lmaWMuDQo+IA0KTVQ2MzU5IGhhcyBzb21lIGdwaW9zIChwYWRfYXVkXyopIGZvciBkb3du bGluay91cGxpbmsuDQpBbmQgdGhlc2UgcGlucyBpcyBjb25uZWN0ZWQgYmV0d2VlbiBBUCBwYXJ0 IGFuZCBQTUlDIHBhcnQuDQooMSkgRm9yIEFQIHBhcnQsIHVzZXIgbmVlZCB0byBzZXQgZ3BpbyBw aW5tdXggZm9yIHRoZXNlIGdwaW8gdXNpbmcgRFQuDQooMikgRm9yIHBtaWMgcGFydCwgZ3BpbyBh cmUgY29uZmlndXJlZCBhdCBjb2RlYyBkcml2ZXIgYnkgZGVmYXVsdC4NCg0KRm9yIFBNSUMgcGFy dCwgdXNlciBuZWVkIHRvIHNldCBpbiB0aGVzZSByZWdpc3RlciA6DQpHUElPX01PREUxL0dQSU9f TU9ERTIvR1BJT19NT0RFMw0KDQpUaGUgZm9sbG93aW5nIGZ1bmN0aW9ucyBhcmUgdXNlZCB0byBz ZXQ6DQotIHBsYXliYWNrX2dwaW9fc2V0L3BsYXliYWNrX2dwaW9fcmVzZXQNCi0gY2FwdHVyZV9n cGlvX3NldC9jYXB0dXJlX2dwaW9fcmVzZXQNCi0gdm93X2dwaW9fc2V0L3Zvd19ncGlvX3Jlc2V0 DQoNCg0KPiA+ICsvKiB1c2Ugb25seSB3aGVuIG5vdCBnb3Zlcm4gYnkgREFQTSAqLw0KPiA+ICtz dGF0aWMgaW50IG10NjM1OV9zZXRfZGN4byhzdHJ1Y3QgbXQ2MzU5X3ByaXYgKnByaXYsIGJvb2wg ZW5hYmxlKQ0KPiA+ICt7DQo+IA0KPiBXaHkgbWlnaHQgdGhpcyBzb21ldGltZXMgYmUgY29udHJv bGxlZCBvdXRzaWRlIG9mIERBUE0/DQo+IA0KbXQ2MzU5X3NldF9kY3hvIGlzIHVzZWQgYXQgbXQ2 MzU5X210a2FpZl9jYWxpYnJhdGlvbl9lbmFibGUvZGlzYWJsZS4NCg0KbXRrYWlmX2NhbGlicmF0 aW9uIHByb2Nlc3MgbmVlZHMgYmUgY29tcGxldGVkIGF0IGJvb3Rpbmcgc3RhZ2Ugb25jZS4NCkFu ZCBpdCBoYXMgYSBzcGVjaWZpYyBjb250cm9sIHNlcXVlbmNlIHByb3ZpZGVkIGJ5IGNvZGVjIGRl c2lnbmVyLg0KU28gaXQgbmVlZCB0byBiZSBjb250cm9sbGVkIG91dHNpZGUgb2YgREFQTS4NCg0K PiA+ICsvKiByZWcgaWR4IGZvciAtNDBkQiovDQo+ID4gKyNkZWZpbmUgUEdBX01JTlVTXzQwX0RC X1JFR19WQUwgMHgxZg0KPiA+ICsjZGVmaW5lIEhQX1BHQV9NSU5VU180MF9EQl9SRUdfVkFMIDB4 M2YNCj4gPiArc3RhdGljIGNvbnN0IGNoYXIgKmNvbnN0IGRsX3BnYV9nYWluW10gPSB7DQo+ID4g KwkiOERiIiwgIjdEYiIsICI2RGIiLCAiNURiIiwgIjREYiIsDQo+ID4gKwkiM0RiIiwgIjJEYiIs ICIxRGIiLCAiMERiIiwgIi0xRGIiLA0KPiA+ICsJIi0yRGIiLCAiLTNEYiIsCSItNERiIiwgIi01 RGIiLCAiLTZEYiIsDQo+ID4gKwkiLTdEYiIsICItOERiIiwgIi05RGIiLCAiLTEwRGIiLCAiLTQw RGIiDQo+ID4gK307DQo+ID4gKw0KPiA+ICtzdGF0aWMgY29uc3QgY2hhciAqY29uc3QgaHBfZGxf cGdhX2dhaW5bXSA9IHsNCj4gPiArCSI4RGIiLCAiN0RiIiwgIjZEYiIsICI1RGIiLCAiNERiIiwN Cj4gPiArCSIzRGIiLCAiMkRiIiwgIjFEYiIsICIwRGIiLCAiLTFEYiIsDQo+ID4gKwkiLTJEYiIs ICItM0RiIiwJIi00RGIiLCAiLTVEYiIsICItNkRiIiwNCj4gPiArCSItN0RiIiwgIi04RGIiLCAi LTlEYiIsICItMTBEYiIsICItMTFEYiIsDQo+ID4gKwkiLTEyRGIiLCAiLTEzRGIiLCAiLTE0RGIi LCAiLTE1RGIiLCAiLTE2RGIiLA0KPiA+ICsJIi0xN0RiIiwgIi0xOERiIiwgIi0xOURiIiwgIi0y MERiIiwgIi0yMURiIiwNCj4gPiArCSItMjJEYiIsICItNDBEYiINCj4gPiArfTsNCj4gDQo+IEkg Y2FuJ3Qgc2VlIGFueSB1c2VycyBvZiB0aGVzZSB0YWJsZXMgaW4gdGhlIGRyaXZlcj8gIFRoYXQn cyBnb29kIHNpbmNlDQo+IHRoZSBkcml2ZXIgc2hvdWxkIGJlIHRyYW5zbGF0aW5nIHRoZXNlIGlu dG8gVExWIGNvbnRyb2xzIHJhdGhlciB0aGFuDQo+IHVzaW5nIGVudW1zIGJ1dCB0aGVzZSB2YXJp YWJsZXMgYXJlbid0IHVzZWQgdGhlbiBzbyBzaG91bGQgYmUgcmVtb3ZlZC4NCj4gDQpZZXMsIHlv dSBhcmUgcmlnaHQuIFRoZXNlIGVudW0gYXJlIHVzZWxlc3MgYW5kIEkgd2lsbCByZW1vdmUgaXQg YXQgbmV4dA0KcGF0Y2guDQoNCg0KPiA+ICsNCj4gPiArCWlmICghaXNfdmFsaWRfaHBfcGdhX2lk eChmcm9tKSB8fCAhaXNfdmFsaWRfaHBfcGdhX2lkeCh0bykpDQo+ID4gKwkJZGV2X3dhcm4ocHJp di0+ZGV2LCAiJXMoKSwgdm9sdW1lIGluZGV4IGlzIG5vdCB2YWxpZCwgZnJvbSAlZCwgdG8gJWRc biIsDQo+ID4gKwkJCSBfX2Z1bmNfXywgZnJvbSwgdG8pOw0KPiANCj4gU2hvdWxkbid0IHdlIHJl dHVybiBhbiBlcnJvciB0aGVuPw0KPiANClllcywgeW91IGFyZSByaWdodC4gSSB3aWxsIGFkZCBl cnJvciBoYW5kbGluZyBpbiBoZWFkc2V0X3ZvbHVtZV9yYW1wKCkNCmF0IG5leHQgcGF0Y2guDQoN Cj4gPiArDQo+ID4gKwlkZXZfaW5mbyhwcml2LT5kZXYsICIlcygpLCBmcm9tICVkLCB0byAlZFxu IiwNCj4gPiArCQkgX19mdW5jX18sIGZyb20sIHRvKTsNCj4gDQo+IEF0IG1vc3QgdGhpcyBzaG91 bGQgYmUgYSBkZXZfZGJnKCksIGhhdmluZyBhIGRldl9pbmZvKCkgbG9nIGlzIGdvaW5nIHRvDQo+ IGJlIGZhciB0b28gdmVyYm9zZS4gIFRoZXJlJ3MgYSBsb3Qgb2YgdGhlc2UgaW4gdGhlIGRyaXZl ci4NCj4gDQpvaywgSSB3aWxsIHJlcGxhY2UgZGV2X2luZm8gd2l0aCBkZXZfZGdiIGZvciB0aGVz ZSBkZWd1ZyBsb2dzLg0KDQo+ID4gK3N0YXRpYyBjb25zdCBjaGFyICpjb25zdCBtaWNfdHlwZV9t dXhfbWFwW10gPSB7DQo+ID4gKwkiSWRsZSIsDQo+ID4gKwkiQUNDIiwNCj4gPiArCSJETUlDIiwN Cj4gPiArCSJEQ0MiLA0KPiA+ICsJIkRDQ19FQ01fRElGRiIsDQo+ID4gKwkiRENDX0VDTV9TSU5H TEUiLA0KPiA+ICsJIlZPV19BQ0MiLA0KPiA+ICsJIlZPV19ETUlDIiwNCj4gPiArCSJWT1dfRE1J Q19MUCIsDQo+ID4gKwkiVk9XX0RDQyIsDQo+ID4gKwkiVk9XX0RDQ19FQ01fRElGRiIsDQo+ID4g KwkiVk9XX0RDQ19FQ01fU0lOR0xFIg0KPiA+ICt9Ow0KPiANCj4gVGhpcyBsb29rcyBsaWtlIHNv bWV0aGluZyB0aGF0IHNob3VsZCBiZSBiZWluZyBzZXQgYnkgRFQgb3Igb3RoZXINCj4gcGxhdGZv cm0gZGF0YSByYXRoZXIgdGhhbiBhdCBydW50aW1lIC0gd2UncmUgbm90IGxpa2VseSB0byBjaGFu Z2UgZnJvbSBhDQo+IGRpZ2l0YWwgdG8gYW5hbG9ndWUgbWljcm9waG9uZSBhdCBydW50aW1lIGZv ciBleGFtcGxlLg0KPiANCg0KRm9yIG1pYzEsIGl0J3MgbWljX3R5cGUgY2FuIHNldCBvbmUgb2Yg bWljX3R5cGVfbXV4X21hcFtdIGF0IGRpZmZlcmVudA0Kc2NlbmFyaW8uDQooMSkgV2hlbiBtaWMx IGlzIG5vdCB1c2VkLCBpdCBzaG91bGQgYmUgc2V0IGFzICJJZGxlIg0KKDIpIFdoZW4gbWljMSBp cyBBQ0MgbW9kZSBhbmQgdXNlZCBhdCBub3JtYWwgY2FwdHVyZSBzY2VuYXJpbywgaXQgc2hvdWxk DQpiZSBzZXQgYXMgIkFDQyINCigzKSBXaGVuIG1pYzEgaXMgQUNDIG1vZGUgYW5kIHVzZWQgYXQg Vm9pY2UgV2FrZXVwIHNjZW5hcmlvLCBpdCBzaG91bGQNCmJlIHNldCBhcyAiVk9XX0FDQyINCg0K U28gbWljJ3MgdHlwZSBtYXkgcnVudGltZSBjaGFuZ2VkIGJ5IHVzZXIgc2NlbmFyaW8uIEFuZCB3 aXRoIGRpZmZlcmVudA0KbWljIHR5cGUsIHNldHRpbmcgaW4gbXRfbWljX2JpYXNfKl9ldmVudCgp IGlzIGFsc28gZGlmZmVyZW50Lg0KDQoNCj4gPiArc3RhdGljIGludCBtdDYzNTlfcHV0X3ZvbHN3 KHN0cnVjdCBzbmRfa2NvbnRyb2wgKmtjb250cm9sLA0KPiA+ICsJCQkgICAgc3RydWN0IHNuZF9j dGxfZWxlbV92YWx1ZSAqdWNvbnRyb2wpDQo+ID4gK3sNCj4gPiArCXN0cnVjdCBzbmRfc29jX2Nv bXBvbmVudCAqY29tcG9uZW50ID0NCj4gPiArCQkJc25kX3NvY19rY29udHJvbF9jb21wb25lbnQo a2NvbnRyb2wpOw0KPiA+ICsJc3RydWN0IG10NjM1OV9wcml2ICpwcml2ID0gc25kX3NvY19jb21w b25lbnRfZ2V0X2RydmRhdGEoY29tcG9uZW50KTsNCj4gPiArCXN0cnVjdCBzb2NfbWl4ZXJfY29u dHJvbCAqbWMgPQ0KPiA+ICsJCQkoc3RydWN0IHNvY19taXhlcl9jb250cm9sICopa2NvbnRyb2wt PnByaXZhdGVfdmFsdWU7DQo+ID4gKwl1bnNpZ25lZCBpbnQgcmVnOw0KPiA+ICsJaW50IGluZGV4 ID0gdWNvbnRyb2wtPnZhbHVlLmludGVnZXIudmFsdWVbMF07DQo+ID4gKwlpbnQgcmV0Ow0KPiA+ ICsNCj4gPiArCXJldCA9IHNuZF9zb2NfcHV0X3ZvbHN3KGtjb250cm9sLCB1Y29udHJvbCk7DQo+ ID4gKwlpZiAocmV0IDwgMCkNCj4gPiArCQlyZXR1cm4gcmV0Ow0KPiA+ICsNCj4gPiArCXN3aXRj aCAobWMtPnJlZykgew0KPiA+ICsJY2FzZSBNVDYzNTlfWkNEX0NPTjI6DQo+ID4gKwkJcmVnbWFw X3JlYWQocHJpdi0+cmVnbWFwLCBNVDYzNTlfWkNEX0NPTjIsICZyZWcpOw0KPiA+ICsJCXByaXYt PmFuYV9nYWluW0FVRElPX0FOQUxPR19WT0xVTUVfSFBPVVRMXSA9DQo+ID4gKwkJCShyZWcgPj4g UkdfQVVESFBMR0FJTl9TRlQpICYgUkdfQVVESFBMR0FJTl9NQVNLOw0KPiA+ICsJCXByaXYtPmFu YV9nYWluW0FVRElPX0FOQUxPR19WT0xVTUVfSFBPVVRSXSA9DQo+ID4gKwkJCShyZWcgPj4gUkdf QVVESFBSR0FJTl9TRlQpICYgUkdfQVVESFBSR0FJTl9NQVNLOw0KPiA+ICsJCWJyZWFrOw0KPiAN Cj4gSXQncyB1bmNsZWFyIHdoYXQncyBnb2luZyBvbiB3aXRoIHRoaXMgY3VzdG9tIGZ1bmN0aW9u LiAgQXMgZmFyIGFzIEkgY2FuDQo+IHNlZSBhbGwgaXQncyBkb2luZyBpcyB0YWtpbmcgYSBjb3B5 IG9mIHRoZSBnYWluIHNldHRpbmcgZm9yIGxhdGVyIHVzZSBieQ0KPiByYW1waWcgZnVuY3Rpb25z IGJ1dCBzaW5jZSB3ZSdyZSBpbW1lZGlhdGVseSB3cml0aW5nIHRoZSBzZXQgdmFsdWUgaW50bw0K PiB0aGUgcmVnaXN0ZXIgbWFwIHN1cmVseSB3ZSBkb24ndCBuZWVkIHRoYXQgYXMgd2UgY2FuIGp1 c3QgcmVhZCB0aGUgdmFsdWUNCj4gYmFjayBmcm9tIHRoZSByZWdpc3Rlcj8NCj4gDQpZZXMsIGl0 IHNhdmVzIGdhaW4gc2V0dGluZyBhdCByZWdpc3RlciBtYXAsIGFuZCBhbHNvIHNhdmUgYXQgcHJp di0+YW5hX2dhaW5bXS4NCldoZW4gZGV2aWNlKGhlYWRzZXQvcmVjZWl2ZXIvbGluZW91dCkgaXMg ZW5hYmxlIG9yIGRpc2FibGUsIGl0IGNhbiB0YWtlIA0KcHJpdi0+YW5hX2dhaW5bXSBmb3IgZ2Fp biByYW1waW5nIGluc3RlYWQgb2YgcmVhZGluZyBiYWNrIGZyb20gcmVnaXN0ZXIgYWdhaW4uDQoN Ckl0IGlzIHJlZmVyZW5jZWQgYW5vdGhlciBjb2RlYyBkcml2ZXIobXQ2MzU4LmMpLg0KDQo+ID4g K3N0YXRpYyBjb25zdCBzdHJ1Y3Qgc25kX2tjb250cm9sX25ldyBtdDYzNTlfc25kX2NvbnRyb2xz W10gPSB7DQo+ID4gKwkvKiBkbCBwZ2EgZ2FpbiAqLw0KPiA+ICsJU09DX1NJTkdMRV9FWFRfVExW KCJIZWFkc2V0TCBWb2x1bWUiLA0KPiA+ICsJCQkgICBNVDYzNTlfWkNEX0NPTjIsIDAsIDB4MUUs IDAsDQo+ID4gKwkJCSAgIHNuZF9zb2NfZ2V0X3ZvbHN3LCBtdDYzNTlfcHV0X3ZvbHN3LA0KPiA+ ICsJCQkgICBocF9wbGF5YmFja190bHYpLA0KPiA+ICsJU09DX1NJTkdMRV9FWFRfVExWKCJIZWFk c2V0UiBWb2x1bWUiLA0KPiA+ICsJCQkgICBNVDYzNTlfWkNEX0NPTjIsIDcsIDB4MUUsIDAsDQo+ ID4gKwkJCSAgIHNuZF9zb2NfZ2V0X3ZvbHN3LCBtdDYzNTlfcHV0X3ZvbHN3LA0KPiA+ICsJCQkg ICBocF9wbGF5YmFja190bHYpLA0KPiA+ICsJU09DX1NJTkdMRV9FWFRfVExWKCJMaW5lb3V0TCBW b2x1bWUiLA0KPiA+ICsJCQkgICBNVDYzNTlfWkNEX0NPTjEsIDAsIDB4MTIsIDAsDQo+ID4gKwkJ CSAgIHNuZF9zb2NfZ2V0X3ZvbHN3LCBtdDYzNTlfcHV0X3ZvbHN3LCBwbGF5YmFja190bHYpLA0K PiA+ICsJU09DX1NJTkdMRV9FWFRfVExWKCJMaW5lb3V0UiBWb2x1bWUiLA0KPiA+ICsJCQkgICBN VDYzNTlfWkNEX0NPTjEsIDcsIDB4MTIsIDAsDQo+ID4gKwkJCSAgIHNuZF9zb2NfZ2V0X3ZvbHN3 LCBtdDYzNTlfcHV0X3ZvbHN3LCBwbGF5YmFja190bHYpLA0KPiANCj4gVGhlc2Ugc2hvdWxkIGJl IHN0ZXJlbyBjb250cm9scyBub3QgcGFpcnMgb2YgbW9ubyBjb250cm9scy4NCj4gDQpJdCBpcyBt b3JlIGZsZXhpYmxlIGZvciBjdXN0b21pemF0aW9uLg0KDQpGb3IgZXhhbXBsZSwgY3VzdG9tZXIg bWF5IHVzZSBsaW5lb3V0IHBhdGggZm9yIHN0ZXJlbyBzcGVha2VyIGFtcC4NCkFuZCBmb3Igc3Bl Y2lmaWMgYW1wLCBpdCBuZWVkIGRpZmZlcmVudCBnYWluIG9uIGNoYW5uZWwgTCBhbmQgY2hhbm5l bCBSLg0KDQoNCj4gPiArCS8qIHVsIHBnYSBnYWluICovDQo+ID4gKwlTT0NfU0lOR0xFX0VYVF9U TFYoIlBHQUwgVm9sdW1lIiwNCj4gPiArCQkJICAgTVQ2MzU5X0FVREVOQ19BTkFfQ09OMCwgUkdf QVVEUFJFQU1QTEdBSU5fU0ZULCA0LCAwLA0KPiA+ICsJCQkgICBzbmRfc29jX2dldF92b2xzdywg bXQ2MzU5X3B1dF92b2xzdywgY2FwdHVyZV90bHYpLA0KPiA+ICsJU09DX1NJTkdMRV9FWFRfVExW KCJQR0FSIFZvbHVtZSIsDQo+ID4gKwkJCSAgIE1UNjM1OV9BVURFTkNfQU5BX0NPTjEsIFJHX0FV RFBSRUFNUFJHQUlOX1NGVCwgNCwgMCwNCj4gPiArCQkJICAgc25kX3NvY19nZXRfdm9sc3csIG10 NjM1OV9wdXRfdm9sc3csIGNhcHR1cmVfdGx2KSwNCj4gDQo+IFNhbWUgaGVyZS4NCg0KRWFjaCBt aWMgbWF5IGhhcyBpdCdzIGRpZmZlcmVudCBnYWluIHNldHRpbmcgaW4gZGlmZmVyZW50IHNjZW5h cmlvLg0KDQpGb3IgZXhhbXBsZSwgaW4gcGhvbmUgY2FsbGluZyBzY2VuYXJpbywgbWljMSBpcyBt YWluIG1pYyBhbmQgbWljMiBpcw0KcmVmZXJlbmNlIG1pYy4NCkFuZCBpbiB2aWRlbyByZWNvcmRp bmcgc2NlbmFyaW8sIG1pYzEgaXMgcmVmZXJlbmNlIG1pYyBhbmQgbWljMiBpcyBtYWluDQptaWMu DQoNClBHQUwgaXMgZm9yIG1pYzEsIFBHQVIgaXMgZm9yIG1pYzIsIFBHQTMgaXMgZm9yIG1pYzMu DQpXZSB0aGluayBpdCBpcyBtb3JlIGZsZXhpYmxlIGluIGRpZmZlcmVudCB1c2VyIHNjZW5hcmlv Lg0KDQo+IA0KPiA+ICtzdGF0aWMgY29uc3QgY2hhciAqIGNvbnN0IGxvX2luX211eF9tYXBbXSA9 IHsNCj4gPiArCSJPcGVuIiwgIlBsYXliYWNrX0xfREFDIiwgIlBsYXliYWNrIiwgIlRlc3QgTW9k ZSINCj4gPiArfTsNCj4gPiArDQo+ID4gK3N0YXRpYyBpbnQgbG9faW5fbXV4X21hcF92YWx1ZVtd ID0gew0KPiA+ICsJMHgwLCAweDEsIDB4MiwgMHgzLA0KPiA+ICt9Ow0KPiANCj4gV2h5IHVzZSBh IHZhbHVlIGVudW0gaGVyZSwgYSBub3JtYWwgbXV4IHNob3VsZCBiZSBmaW5lPw0KPiANCg0KQ291 bGQgSSBtb2RpZnkgYXMgZm9sbG93Og0KDQovKiBMT0wgTVVYICovDQplbnVtIHsNCglMT19NVVhf T1BFTiA9IDAsDQoJTE9fTVVYX0xfREFDLA0KCUxPX01VWF8zUkRfREFDLA0KCUxPX01VWF9URVNU X01PREUsDQoJTE9fTVVYX01BU0sgPSAweDMsDQp9Ow0KDQpzdGF0aWMgY29uc3QgY2hhciAqIGNv bnN0IGxvX2luX211eF9tYXBbXSA9IHsNCgkiT3BlbiIsICJQbGF5YmFja19MX0RBQyIsICJQbGF5 YmFjayIsICJUZXN0IE1vZGUiDQp9Ow0KDQpzdGF0aWMgaW50IGxvX2luX211eF9tYXBfdmFsdWVb XSA9IHsNCglMT19NVVhfT1BFTiwNCglMT19NVVhfTF9EQUMsDQoJTE9fTVVYXzNSRF9EQUMsDQoJ TE9fTVVYX1RFU1RfTU9ERSwNCn07DQoNCj4gPiArc3RhdGljIGludCBtdF9kZWxheV8yNTBfZXZl bnQoc3RydWN0IHNuZF9zb2NfZGFwbV93aWRnZXQgKncsDQo+ID4gKwkJCSAgICAgIHN0cnVjdCBz bmRfa2NvbnRyb2wgKmtjb250cm9sLA0KPiA+ICsJCQkgICAgICBpbnQgZXZlbnQpDQo+ID4gK3sN Cj4gPiArCXN3aXRjaCAoZXZlbnQpIHsNCj4gPiArCWNhc2UgU05EX1NPQ19EQVBNX1BPU1RfUE1V Og0KPiA+ICsJY2FzZSBTTkRfU09DX0RBUE1fUFJFX1BNRDoNCj4gPiArCQl1c2xlZXBfcmFuZ2Uo MjUwLCAyNzApOw0KPiANCj4gV2h5IHdvdWxkIGhhdmluZyBhIHNsZWVwIGJlZm9yZSBwb3dlciBk b3duIGJlIHVzZWZ1bD8NCg0KSXQgaXMgYmFzZWQgb24gZGVzaWduZXIncyBjb250cm9sIHNlcXVl bmNlIHRvIGFkZCBzb21lIGRlbGF5IHdoaWxlDQpQTVUvUE1ELg0KDQpGb3IgIkFVRF9DSyIgcG93 ZXIgd2lkZ2V0Og0KDQoJU05EX1NPQ19EQVBNX1NVUFBMWV9TKCJBVURfQ0siLCBTVVBQTFlfU0VR X1RPUF9DS19MQVNULA0KCQkJICAgICAgTVQ2MzU5X0FVRF9UT1BfQ0tQRE5fQ09OMCwNCgkJCSAg ICAgIFJHX0FVRF9DS19QRE5fU0ZULCAxLA0KCQkJICAgICAgbXRfZGVsYXlfMjUwX2V2ZW50LA0K CQkJICAgICAgU05EX1NPQ19EQVBNX1BPU1RfUE1VIHwgU05EX1NPQ19EQVBNX1BSRV9QTUQpLAkJ CQkJCQkJCQkJCQkJDQoNCg0KPiANCj4gPiArc3RhdGljIGludCBtdDYzNTlfY29kZWNfcHJvYmUo c3RydWN0IHNuZF9zb2NfY29tcG9uZW50ICpjbXBudCkNCj4gPiArew0KPiA+ICsJc3RydWN0IG10 NjM1OV9wcml2ICpwcml2ID0gc25kX3NvY19jb21wb25lbnRfZ2V0X2RydmRhdGEoY21wbnQpOw0K PiA+ICsJaW50IHJldDsNCj4gPiArDQo+ID4gKwlzbmRfc29jX2NvbXBvbmVudF9pbml0X3JlZ21h cChjbXBudCwgcHJpdi0+cmVnbWFwKTsNCj4gPiArDQo+ID4gKwlzbmRfc29jX2FkZF9jb21wb25l bnRfY29udHJvbHMoY21wbnQsDQo+ID4gKwkJCQkgICAgICAgbXQ2MzU5X3NuZF92b3dfY29udHJv bHMsDQo+ID4gKwkJCQkgICAgICAgQVJSQVlfU0laRShtdDYzNTlfc25kX3Zvd19jb250cm9scykp Ow0KPiANCj4gVXNlIHRoZSBjb250cm9scyBtZW1iZXIgb2YgdGhlIGNvbXBvbmVudCBkcml2ZXIg c3RydWN0Lg0KPiANCg0KRG8geW91IG1lYW4gdGhhdCBJIHNob3VsZCBtZXJnZSBtdDYzNTlfc25k X3Zvd19jb250cm9scyBpbnRvDQptdDYzNTlfc25kX2NvbnRyb2xzPw0KDQptdDYzNTlfc25kX2Nv bnRyb2xzIGlzIGRlZmluZWQgYXQgOg0KDQpzdGF0aWMgY29uc3Qgc3RydWN0IHNuZF9zb2NfY29t cG9uZW50X2RyaXZlciBtdDYzNTlfc29jX2NvbXBvbmVudF9kcml2ZXINCj0gew0KCS5jb250cm9s cyA9IG10NjM1OV9zbmRfY29udHJvbHMsDQoNCg0KPiA+ICsJcHJpdi0+YW5hX2dhaW5bQVVESU9f QU5BTE9HX1ZPTFVNRV9IUE9VVExdID0gODsNCj4gPiArCXByaXYtPmFuYV9nYWluW0FVRElPX0FO QUxPR19WT0xVTUVfSFBPVVRSXSA9IDg7DQo+ID4gKwlwcml2LT5hbmFfZ2FpbltBVURJT19BTkFM T0dfVk9MVU1FX01JQ0FNUDFdID0gMzsNCj4gPiArCXByaXYtPmFuYV9nYWluW0FVRElPX0FOQUxP R19WT0xVTUVfTUlDQU1QMl0gPSAzOw0KPiA+ICsJcHJpdi0+YW5hX2dhaW5bQVVESU9fQU5BTE9H X1ZPTFVNRV9NSUNBTVAzXSA9IDM7DQo+IA0KPiBUaGVzZSBzaG91bGQgYmUgbGVmdCBhdCB0aGUg aGFyZHdhcmUgZGVmYXVsdHMuDQoNClRoZXNlIHNldHRpbmcgY2FuIGJlIHJlbW92ZWQgYmVjYXVz ZSBpdCBpcyBhbGlnbiB3aXRoIHJlZ2lzdGVyIGRlZmF1bHQuDQo+IA0KPiA+ICsJcHJpdi0+YXZk ZF9yZWcgPSBkZXZtX3JlZ3VsYXRvcl9nZXQocHJpdi0+ZGV2LCAidmF1ZDE4Iik7DQo+ID4gKwlp ZiAoSVNfRVJSKHByaXYtPmF2ZGRfcmVnKSkgew0KPiA+ICsJCWRldl9lcnIocHJpdi0+ZGV2LCAi JXMoKSwgaGF2ZSBubyB2YXVkMTggc3VwcGx5IiwgX19mdW5jX18pOw0KPiA+ICsJCXJldHVybiBQ VFJfRVJSKHByaXYtPmF2ZGRfcmVnKTsNCj4gPiArCX0NCj4gDQo+IFRoZSBkcml2ZXIgc2hvdWxk IHJlcXVlc3QgcmVzb3VyY2VzIGR1cmluZyBkZXZpY2UgbW9kZWwgcHJvYmUgcmF0aGVyDQo+IHRo YW4gY29tcG9uZW50IHByb2JlLg0KPiANCg0KRG8geW91IG1lYW4gdGhhdCBpdCBuZWVkIGJlIHJl cXVlc3RlZCBhdCBtdDYzNTlfcGxhdGZvcm1fZHJpdmVyX3Byb2JlKCkNCmluc3RlYWQgb2YgbXQ2 MzU5X2NvZGVjX3Byb2JlKCkgPw0KDQo+ID4gKwlyZXQgPSByZWd1bGF0b3JfZW5hYmxlKHByaXYt PmF2ZGRfcmVnKTsNCj4gPiArCWlmIChyZXQpDQo+ID4gKwkJcmV0dXJuIHJldDsNCj4gPiArDQo+ IA0KPiBUaGVyZSdzIG5vdGhpbmcgdG8gZGlzYWJsZSB0aGlzIG9uIHJlbW92ZS4NCg0KRG8geW91 IG1lYW4gdGhhdCBJIHNob3VsZCBhZGQgYSByZW1vdmUgZnVuY3Rpb24gdG8gZXhlY3V0ZQ0KcmVn dWxhdG9yX2Rpc2FibGUoKT8NCg0KDQpzdGF0aWMgc3RydWN0IHBsYXRmb3JtX2RyaXZlciBtdDYz NTlfcGxhdGZvcm1fZHJpdmVyID0gew0KLi4uDQoJLnByb2JlID0gbXQ2MzU5X3BsYXRmb3JtX2Ry aXZlcl9wcm9iZSwNCgkucmVtb3ZlID0gbXQ2MzU5X3BsYXRmb3JtX2RyaXZlcl9yZW1vdmUsICAv KiBhZGQgdGhpcyAqLw0KfTsNCg0KDQpHcmVhdCB0aGFua3MgZm9yIHlvdXIgcmV2aWV3IGFnYWlu Lg0K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3C5AC18E5A for ; Wed, 11 Mar 2020 09:22:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B6CE22146E for ; Wed, 11 Mar 2020 09:22:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="isZi9km0"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="XRTznKKH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B6CE22146E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PiAYdiepiblGijHNUGzwuPDMEkjWlFbnuRF1okNamfA=; b=isZi9km0aHWolo j6r6C095uNLzor8i4iuv6tHIAgrUD3XXfRhyzXcFEKUQry25xWtAhYE+1dLNjspnz8Yw/MLhB4vo8 +TFGPiysQ+oZr3BnCwt1RvsytlcSig27Ebtiy4VSBBAStElpLBb0s/TQM8R5dpvXEPjbsIsee5PRg dmJpT4iJwr2ug1/tUKku6IwS/1n4E/UAjkDVgvMUP+NTrDXoLEUoTl8bVV9Llq6WSBm9W3zHZtZGx BtK6juG6aSLkgBe1U94DqqarDPqmmjVFzROmk7WN5yTJL/YxdL/1zsXRWWNTb30/Q0WVapHZTzhdU XZLjl+bBoCvjlO4XvIUw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jBxZS-0006MF-O5; Wed, 11 Mar 2020 09:22:34 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jBxZP-0006Kr-3c for linux-mediatek@lists.infradead.org; Wed, 11 Mar 2020 09:22:32 +0000 X-UUID: 48cff85ef19e4e65ab3232bfa7137170-20200311 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=YWynqqGFWrui+bPw8+eUdxbiLNv0tlC1GONhbH/mI+0=; b=XRTznKKHAFsg9QE1mAbgUxIFtukPH+quc0nt04/gwuBh3OKbgmYKWh3EigUYhv/qvykIRTsC1YMUjaQfxthivZGY+3vckBtNGwsNQknN436UPCz8QZ20/Al/YmFIL3OS7gV1IJbnP9lALGG7hiRY+Y0jovnN1pXKayg74URbXGI=; X-UUID: 48cff85ef19e4e65ab3232bfa7137170-20200311 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1431225330; Wed, 11 Mar 2020 01:22:27 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 11 Mar 2020 02:22:26 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 11 Mar 2020 17:21:26 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 11 Mar 2020 17:22:32 +0800 Message-ID: <1583918544.19248.69.camel@mtkswgap22> Subject: Re: [PATCH 2/2] ASoC: codec: mediatek: add mt6359 codec driver From: Eason Yen To: Mark Brown Date: Wed, 11 Mar 2020 17:22:24 +0800 In-Reply-To: <20200309131346.GF4101@sirena.org.uk> References: <1583465622-16628-1-git-send-email-eason.yen@mediatek.com> <1583465622-16628-3-git-send-email-eason.yen@mediatek.com> <20200309131346.GF4101@sirena.org.uk> X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200311_022231_166108_0ABAA6DC X-CRM114-Status: GOOD ( 30.29 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, jiaxin.yu@mediatek.com, linux-mediatek@lists.infradead.org, Matthias Brugger Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Dear Mark, Thanks for your attentive review. The following is my feedback. Please kindly give suggestion, thanks. On Mon, 2020-03-09 at 13:13 +0000, Mark Brown wrote: > On Fri, Mar 06, 2020 at 11:33:42AM +0800, Eason Yen wrote: > > > +static void capture_gpio_reset(struct mt6359_priv *priv) > > +{ > > + /* set pad_aud_*_miso to GPIO mode and dir input > > + * reason: > > + * pad_aud_clk_miso, because when playback only the miso_clk > > + * will also have 26m, so will have power leak > > + * pad_aud_dat_miso*, because the pin is used as boot strap > > + */ > > This looks like things that might be better exposed via pinctrl and > gpiolib for board specific configuration - what exactly are these GPIOs > doing? A lot of this code looks like it might be board specific. > MT6359 has some gpios (pad_aud_*) for downlink/uplink. And these pins is connected between AP part and PMIC part. (1) For AP part, user need to set gpio pinmux for these gpio using DT. (2) For pmic part, gpio are configured at codec driver by default. For PMIC part, user need to set in these register : GPIO_MODE1/GPIO_MODE2/GPIO_MODE3 The following functions are used to set: - playback_gpio_set/playback_gpio_reset - capture_gpio_set/capture_gpio_reset - vow_gpio_set/vow_gpio_reset > > +/* use only when not govern by DAPM */ > > +static int mt6359_set_dcxo(struct mt6359_priv *priv, bool enable) > > +{ > > Why might this sometimes be controlled outside of DAPM? > mt6359_set_dcxo is used at mt6359_mtkaif_calibration_enable/disable. mtkaif_calibration process needs be completed at booting stage once. And it has a specific control sequence provided by codec designer. So it need to be controlled outside of DAPM. > > +/* reg idx for -40dB*/ > > +#define PGA_MINUS_40_DB_REG_VAL 0x1f > > +#define HP_PGA_MINUS_40_DB_REG_VAL 0x3f > > +static const char *const dl_pga_gain[] = { > > + "8Db", "7Db", "6Db", "5Db", "4Db", > > + "3Db", "2Db", "1Db", "0Db", "-1Db", > > + "-2Db", "-3Db", "-4Db", "-5Db", "-6Db", > > + "-7Db", "-8Db", "-9Db", "-10Db", "-40Db" > > +}; > > + > > +static const char *const hp_dl_pga_gain[] = { > > + "8Db", "7Db", "6Db", "5Db", "4Db", > > + "3Db", "2Db", "1Db", "0Db", "-1Db", > > + "-2Db", "-3Db", "-4Db", "-5Db", "-6Db", > > + "-7Db", "-8Db", "-9Db", "-10Db", "-11Db", > > + "-12Db", "-13Db", "-14Db", "-15Db", "-16Db", > > + "-17Db", "-18Db", "-19Db", "-20Db", "-21Db", > > + "-22Db", "-40Db" > > +}; > > I can't see any users of these tables in the driver? That's good since > the driver should be translating these into TLV controls rather than > using enums but these variables aren't used then so should be removed. > Yes, you are right. These enum are useless and I will remove it at next patch. > > + > > + if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to)) > > + dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n", > > + __func__, from, to); > > Shouldn't we return an error then? > Yes, you are right. I will add error handling in headset_volume_ramp() at next patch. > > + > > + dev_info(priv->dev, "%s(), from %d, to %d\n", > > + __func__, from, to); > > At most this should be a dev_dbg(), having a dev_info() log is going to > be far too verbose. There's a lot of these in the driver. > ok, I will replace dev_info with dev_dgb for these degug logs. > > +static const char *const mic_type_mux_map[] = { > > + "Idle", > > + "ACC", > > + "DMIC", > > + "DCC", > > + "DCC_ECM_DIFF", > > + "DCC_ECM_SINGLE", > > + "VOW_ACC", > > + "VOW_DMIC", > > + "VOW_DMIC_LP", > > + "VOW_DCC", > > + "VOW_DCC_ECM_DIFF", > > + "VOW_DCC_ECM_SINGLE" > > +}; > > This looks like something that should be being set by DT or other > platform data rather than at runtime - we're not likely to change from a > digital to analogue microphone at runtime for example. > For mic1, it's mic_type can set one of mic_type_mux_map[] at different scenario. (1) When mic1 is not used, it should be set as "Idle" (2) When mic1 is ACC mode and used at normal capture scenario, it should be set as "ACC" (3) When mic1 is ACC mode and used at Voice Wakeup scenario, it should be set as "VOW_ACC" So mic's type may runtime changed by user scenario. And with different mic type, setting in mt_mic_bias_*_event() is also different. > > +static int mt6359_put_volsw(struct snd_kcontrol *kcontrol, > > + struct snd_ctl_elem_value *ucontrol) > > +{ > > + struct snd_soc_component *component = > > + snd_soc_kcontrol_component(kcontrol); > > + struct mt6359_priv *priv = snd_soc_component_get_drvdata(component); > > + struct soc_mixer_control *mc = > > + (struct soc_mixer_control *)kcontrol->private_value; > > + unsigned int reg; > > + int index = ucontrol->value.integer.value[0]; > > + int ret; > > + > > + ret = snd_soc_put_volsw(kcontrol, ucontrol); > > + if (ret < 0) > > + return ret; > > + > > + switch (mc->reg) { > > + case MT6359_ZCD_CON2: > > + regmap_read(priv->regmap, MT6359_ZCD_CON2, ®); > > + priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = > > + (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK; > > + priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = > > + (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK; > > + break; > > It's unclear what's going on with this custom function. As far as I can > see all it's doing is taking a copy of the gain setting for later use by > rampig functions but since we're immediately writing the set value into > the register map surely we don't need that as we can just read the value > back from the register? > Yes, it saves gain setting at register map, and also save at priv->ana_gain[]. When device(headset/receiver/lineout) is enable or disable, it can take priv->ana_gain[] for gain ramping instead of reading back from register again. It is referenced another codec driver(mt6358.c). > > +static const struct snd_kcontrol_new mt6359_snd_controls[] = { > > + /* dl pga gain */ > > + SOC_SINGLE_EXT_TLV("HeadsetL Volume", > > + MT6359_ZCD_CON2, 0, 0x1E, 0, > > + snd_soc_get_volsw, mt6359_put_volsw, > > + hp_playback_tlv), > > + SOC_SINGLE_EXT_TLV("HeadsetR Volume", > > + MT6359_ZCD_CON2, 7, 0x1E, 0, > > + snd_soc_get_volsw, mt6359_put_volsw, > > + hp_playback_tlv), > > + SOC_SINGLE_EXT_TLV("LineoutL Volume", > > + MT6359_ZCD_CON1, 0, 0x12, 0, > > + snd_soc_get_volsw, mt6359_put_volsw, playback_tlv), > > + SOC_SINGLE_EXT_TLV("LineoutR Volume", > > + MT6359_ZCD_CON1, 7, 0x12, 0, > > + snd_soc_get_volsw, mt6359_put_volsw, playback_tlv), > > These should be stereo controls not pairs of mono controls. > It is more flexible for customization. For example, customer may use lineout path for stereo speaker amp. And for specific amp, it need different gain on channel L and channel R. > > + /* ul pga gain */ > > + SOC_SINGLE_EXT_TLV("PGAL Volume", > > + MT6359_AUDENC_ANA_CON0, RG_AUDPREAMPLGAIN_SFT, 4, 0, > > + snd_soc_get_volsw, mt6359_put_volsw, capture_tlv), > > + SOC_SINGLE_EXT_TLV("PGAR Volume", > > + MT6359_AUDENC_ANA_CON1, RG_AUDPREAMPRGAIN_SFT, 4, 0, > > + snd_soc_get_volsw, mt6359_put_volsw, capture_tlv), > > Same here. Each mic may has it's different gain setting in different scenario. For example, in phone calling scenario, mic1 is main mic and mic2 is reference mic. And in video recording scenario, mic1 is reference mic and mic2 is main mic. PGAL is for mic1, PGAR is for mic2, PGA3 is for mic3. We think it is more flexible in different user scenario. > > > +static const char * const lo_in_mux_map[] = { > > + "Open", "Playback_L_DAC", "Playback", "Test Mode" > > +}; > > + > > +static int lo_in_mux_map_value[] = { > > + 0x0, 0x1, 0x2, 0x3, > > +}; > > Why use a value enum here, a normal mux should be fine? > Could I modify as follow: /* LOL MUX */ enum { LO_MUX_OPEN = 0, LO_MUX_L_DAC, LO_MUX_3RD_DAC, LO_MUX_TEST_MODE, LO_MUX_MASK = 0x3, }; static const char * const lo_in_mux_map[] = { "Open", "Playback_L_DAC", "Playback", "Test Mode" }; static int lo_in_mux_map_value[] = { LO_MUX_OPEN, LO_MUX_L_DAC, LO_MUX_3RD_DAC, LO_MUX_TEST_MODE, }; > > +static int mt_delay_250_event(struct snd_soc_dapm_widget *w, > > + struct snd_kcontrol *kcontrol, > > + int event) > > +{ > > + switch (event) { > > + case SND_SOC_DAPM_POST_PMU: > > + case SND_SOC_DAPM_PRE_PMD: > > + usleep_range(250, 270); > > Why would having a sleep before power down be useful? It is based on designer's control sequence to add some delay while PMU/PMD. For "AUD_CK" power widget: SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST, MT6359_AUD_TOP_CKPDN_CON0, RG_AUD_CK_PDN_SFT, 1, mt_delay_250_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), > > > +static int mt6359_codec_probe(struct snd_soc_component *cmpnt) > > +{ > > + struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt); > > + int ret; > > + > > + snd_soc_component_init_regmap(cmpnt, priv->regmap); > > + > > + snd_soc_add_component_controls(cmpnt, > > + mt6359_snd_vow_controls, > > + ARRAY_SIZE(mt6359_snd_vow_controls)); > > Use the controls member of the component driver struct. > Do you mean that I should merge mt6359_snd_vow_controls into mt6359_snd_controls? mt6359_snd_controls is defined at : static const struct snd_soc_component_driver mt6359_soc_component_driver = { .controls = mt6359_snd_controls, > > + priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = 8; > > + priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = 8; > > + priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] = 3; > > + priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] = 3; > > + priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3] = 3; > > These should be left at the hardware defaults. These setting can be removed because it is align with register default. > > > + priv->avdd_reg = devm_regulator_get(priv->dev, "vaud18"); > > + if (IS_ERR(priv->avdd_reg)) { > > + dev_err(priv->dev, "%s(), have no vaud18 supply", __func__); > > + return PTR_ERR(priv->avdd_reg); > > + } > > The driver should request resources during device model probe rather > than component probe. > Do you mean that it need be requested at mt6359_platform_driver_probe() instead of mt6359_codec_probe() ? > > + ret = regulator_enable(priv->avdd_reg); > > + if (ret) > > + return ret; > > + > > There's nothing to disable this on remove. Do you mean that I should add a remove function to execute regulator_disable()? static struct platform_driver mt6359_platform_driver = { ... .probe = mt6359_platform_driver_probe, .remove = mt6359_platform_driver_remove, /* add this */ }; Great thanks for your review again. _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek