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* [PATCH v7 00/12] Actions S700 SoC support
@ 2020-03-20 17:35 Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 01/12] arm: actions: Add common framework for Actions Owl Semi SoCs Amit Singh Tomar
                   ` (11 more replies)
  0 siblings, 12 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

This adds Cubieboard7[1] support based on Action Semi's S700 SoC[2], It's Quad-core ARMv8 SoC
with Cortex-A53 cores. Peripheral like UART seems to be compatible with S900 SoC(basic support
for it is alreay present in u-boot).

This Series(v7) fixes a serious Bug that breaks S900, it was there since v5.Thanks to Andre
for pointing it out. 

Series(v6)[3] does following changes:

* [PATCH v5 06/11] becomes [PATCH v6 03/11]
* [PATCH v5 03/11] becomes [PATCH v6 04/11]
* Introduce a new patch to move defconfig options to Kconfig which is [PATCH v6 10/12]

Series(v5)[4] just re-orders the patches so that U-BOOT(with bubblegum96_defconfig) builds
after every patch of the series(suggested by Andre).

S700 support is tested[5] on Cubieboard7 board and S900 support is just compiled tested.

This patch series can be tested using below tree:
https://github.com/Atomar25/u-boot/commits/s700_v7

[1]: http://www.cubietech.com/product-detail/cubieboard7/
[2]: http://www.actions-semi.com/en/productview.aspx?id=225
[3]: http://u-boot.10912.n7.nabble.com/PATCH-v6-00-12-Actions-S700-SoC-support-td403562.html#a403567
[4]: http://u-boot.10912.n7.nabble.com/PATCH-v5-00-11-Actions-S700-SoC-support-td402752.html#a402762
[5]: https://paste.ubuntu.com/p/w2FvzmZBcS/

Amit Singh Tomar (12):
  arm: actions: Add common framework for Actions Owl Semi SoCs
  arm: actions: rename sysmap-s900 to sysmap-owl
  serial: actions: add compatible string
  arm: dts: sync dts for Action Semi S900
  arm: dts: actions: s900: add u-boot specific dtsi file
  clk: actions: Add common clock driver
  arm: actions: add S700 SoC device tree
  arm: dts: actions: s700: add u-boot specific dtsi file
  arm: add support Actions Semi S700
  actions: Move defconfig options to Kconfig
  arm: add Cubieboard7 board support
  doc: boards: add Cubieboard7 documentation

 MAINTAINERS                                    |   2 +
 arch/arm/Kconfig                               |   5 +-
 arch/arm/dts/Makefile                          |   6 +-
 arch/arm/dts/s700-cubieboard7.dts              |  92 +++++++
 arch/arm/dts/s700-u-boot.dtsi                  |  18 ++
 arch/arm/dts/s700.dtsi                         | 248 +++++++++++++++++++
 arch/arm/dts/s900-u-boot.dtsi                  |  17 ++
 arch/arm/dts/s900.dtsi                         | 322 +++++++++++++++++++++++--
 arch/arm/include/asm/arch-owl/clk_s900.h       |  57 -----
 arch/arm/include/asm/arch-owl/regs_s700.h      |  56 +++++
 arch/arm/mach-owl/Kconfig                      |  50 ++--
 arch/arm/mach-owl/Makefile                     |   3 +-
 arch/arm/mach-owl/soc.c                        |  57 +++++
 arch/arm/mach-owl/sysmap-owl.c                 |  32 +++
 arch/arm/mach-owl/sysmap-s900.c                |  32 ---
 board/ucRobotics/bubblegum_96/Kconfig          |  15 --
 board/ucRobotics/bubblegum_96/MAINTAINERS      |   6 -
 board/ucRobotics/bubblegum_96/Makefile         |   3 -
 board/ucRobotics/bubblegum_96/bubblegum_96.c   |  57 -----
 configs/bubblegum_96_defconfig                 |  12 +-
 configs/cubieboard7_defconfig                  |   9 +
 doc/board/actions/cubieboard7.rst              | 115 +++++++++
 doc/board/actions/index.rst                    |  10 +
 doc/board/index.rst                            |   1 +
 drivers/clk/owl/Kconfig                        |   8 +-
 drivers/clk/owl/Makefile                       |   2 +-
 drivers/clk/owl/clk_owl.c                      | 153 ++++++++++++
 drivers/clk/owl/clk_owl.h                      |  65 +++++
 drivers/clk/owl/clk_s900.c                     | 137 -----------
 drivers/serial/serial_owl.c                    |   2 +-
 include/configs/bubblegum_96.h                 |  40 ---
 include/configs/owl-common.h                   |  40 +++
 include/configs/s700.h                         |  13 +
 include/configs/s900.h                         |  16 ++
 include/dt-bindings/clock/actions,s700-cmu.h   | 118 +++++++++
 include/dt-bindings/clock/actions,s900-cmu.h   | 129 ++++++++++
 include/dt-bindings/clock/s900_cmu.h           |  77 ------
 include/dt-bindings/reset/actions,s700-reset.h |  34 +++
 include/dt-bindings/reset/actions,s900-reset.h |  65 +++++
 39 files changed, 1638 insertions(+), 486 deletions(-)
 create mode 100644 arch/arm/dts/s700-cubieboard7.dts
 create mode 100644 arch/arm/dts/s700-u-boot.dtsi
 create mode 100644 arch/arm/dts/s700.dtsi
 create mode 100644 arch/arm/dts/s900-u-boot.dtsi
 delete mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h
 create mode 100644 arch/arm/include/asm/arch-owl/regs_s700.h
 create mode 100644 arch/arm/mach-owl/soc.c
 create mode 100644 arch/arm/mach-owl/sysmap-owl.c
 delete mode 100644 arch/arm/mach-owl/sysmap-s900.c
 delete mode 100644 board/ucRobotics/bubblegum_96/Kconfig
 delete mode 100644 board/ucRobotics/bubblegum_96/MAINTAINERS
 delete mode 100644 board/ucRobotics/bubblegum_96/Makefile
 delete mode 100644 board/ucRobotics/bubblegum_96/bubblegum_96.c
 create mode 100644 configs/cubieboard7_defconfig
 create mode 100644 doc/board/actions/cubieboard7.rst
 create mode 100644 doc/board/actions/index.rst
 create mode 100644 drivers/clk/owl/clk_owl.c
 create mode 100644 drivers/clk/owl/clk_owl.h
 delete mode 100644 drivers/clk/owl/clk_s900.c
 delete mode 100644 include/configs/bubblegum_96.h
 create mode 100644 include/configs/owl-common.h
 create mode 100644 include/configs/s700.h
 create mode 100644 include/configs/s900.h
 create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h
 create mode 100644 include/dt-bindings/clock/actions,s900-cmu.h
 delete mode 100644 include/dt-bindings/clock/s900_cmu.h
 create mode 100644 include/dt-bindings/reset/actions,s700-reset.h
 create mode 100644 include/dt-bindings/reset/actions,s900-reset.h

-- 
2.7.4

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [PATCH v7 01/12] arm: actions: Add common framework for Actions Owl Semi SoCs
  2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
@ 2020-03-20 17:35 ` Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 02/12] arm: actions: rename sysmap-s900 to sysmap-owl Amit Singh Tomar
                   ` (10 subsequent siblings)
  11 siblings, 0 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

This commit adds common arch support for Actions Semi Owl
series SoCs and removes the Bubblegum96 board files.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v6:
	* No change.
Changes since v5:
        * No change.
Changes since v4:
        * No change.
Changes since v3:
        * Corrected the file list entry in MAINTAINERS file.
Changes since v2:
        * Moved the file list details to root MAINTAINERS file.
        * Updated the commit message as suggested by Mani.
        * Used the "Owl" keyword to describe SoC family.
Changes since v1:
        * Moved S700 specific changes to patch 4 of 9.
        * Moved couple of symbols from defconfig to arch/arm/Kconfig
          and platform owl Kconfig.
---
 MAINTAINERS                                  |  2 +
 arch/arm/Kconfig                             |  3 +-
 arch/arm/mach-owl/Kconfig                    | 29 ++++++--------
 arch/arm/mach-owl/Makefile                   |  1 +
 arch/arm/mach-owl/soc.c                      | 57 ++++++++++++++++++++++++++++
 board/ucRobotics/bubblegum_96/Kconfig        | 15 --------
 board/ucRobotics/bubblegum_96/MAINTAINERS    |  6 ---
 board/ucRobotics/bubblegum_96/Makefile       |  3 --
 board/ucRobotics/bubblegum_96/bubblegum_96.c | 57 ----------------------------
 configs/bubblegum_96_defconfig               |  4 +-
 include/configs/bubblegum_96.h               | 40 -------------------
 include/configs/owl-common.h                 | 40 +++++++++++++++++++
 include/configs/s900.h                       | 16 ++++++++
 13 files changed, 130 insertions(+), 143 deletions(-)
 create mode 100644 arch/arm/mach-owl/soc.c
 delete mode 100644 board/ucRobotics/bubblegum_96/Kconfig
 delete mode 100644 board/ucRobotics/bubblegum_96/MAINTAINERS
 delete mode 100644 board/ucRobotics/bubblegum_96/Makefile
 delete mode 100644 board/ucRobotics/bubblegum_96/bubblegum_96.c
 delete mode 100644 include/configs/bubblegum_96.h
 create mode 100644 include/configs/owl-common.h
 create mode 100644 include/configs/s900.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 92dda40..e1c03cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -275,6 +275,8 @@ F:	arch/arm/mach-owl/
 F:	board/ucRobotics/
 F:	drivers/clk/owl/
 F:	drivers/serial/serial_owl.c
+F:	include/configs/owl-common.h
+F:	configs/bubblegum_96_defconfig
 
 ARM RENESAS RMOBILE/R-CAR
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5d36788..1cfdcb6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -873,9 +873,9 @@ config ARCH_MX5
 
 config ARCH_OWL
 	bool "Actions Semi OWL SoCs"
-	select ARM64
 	select DM
 	select DM_SERIAL
+	select OWL_SERIAL
 	select OF_CONTROL
 	imply CMD_DM
 
@@ -1865,7 +1865,6 @@ source "board/spear/spear600/Kconfig"
 source "board/spear/x600/Kconfig"
 source "board/st/stv0991/Kconfig"
 source "board/tcl/sl50/Kconfig"
-source "board/ucRobotics/bubblegum_96/Kconfig"
 source "board/birdland/bav335x/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
 source "board/variscite/dart_6ul/Kconfig"
diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig
index 199e772..d0be2b5 100644
--- a/arch/arm/mach-owl/Kconfig
+++ b/arch/arm/mach-owl/Kconfig
@@ -1,27 +1,22 @@
 if ARCH_OWL
 
-config SYS_SOC
-	default "owl"
-
 choice
-        prompt "Actions Semi OWL SoCs board select"
+        prompt "Actions Semi Owl SoC Variant"
         optional
 
-config TARGET_BUBBLEGUM_96
-	bool "96Boards Bubblegum-96"
-	help
-	  Support for 96Boards Bubblegum-96. This board complies with
-	  96Board Consumer Edition Specification. Features:
-	  - Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU)
-	  - 2GiB RAM
-	  - 8GiB eMMC, uSD slot
-	  - WiFi, Bluetooth and GPS module
-	  - 2x Host, 1x Device USB port
-	  - HDMI
-	  - 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons
+config MACH_S900
+        bool "Actions Semi S900 SoC"
+        select ARM64
 
 endchoice
 
-source "board/ucRobotics/bubblegum_96/Kconfig"
+config SYS_TEXT_BASE
+        default 0x11000000
+
+config SYS_CONFIG_NAME
+        default "s900" if MACH_S900
+
+config SYS_SOC
+        default "s900" if MACH_S900
 
 endif
diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile
index 1b43dc2..0b181c6 100644
--- a/arch/arm/mach-owl/Makefile
+++ b/arch/arm/mach-owl/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
+obj-y += soc.o
 obj-y += sysmap-s900.o
diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c
new file mode 100644
index 0000000..409cbd3
--- /dev/null
+++ b/arch/arm/mach-owl/soc.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions Semi Owl SoCs platform support.
+ *
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <cpu_func.h>
+#include <linux/arm-smccc.h>
+#include <linux/psci.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/psci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * dram_init - sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
+}
+
+/* This is called after dram_init() so use get_ram_size result */
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
+static void show_psci_version(void)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+	printf("PSCI:  v%ld.%ld\n",
+		PSCI_VERSION_MAJOR(res.a0),
+		PSCI_VERSION_MINOR(res.a0));
+}
+
+int board_init(void)
+{
+	show_psci_version();
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
diff --git a/board/ucRobotics/bubblegum_96/Kconfig b/board/ucRobotics/bubblegum_96/Kconfig
deleted file mode 100644
index 2dd40d9..0000000
--- a/board/ucRobotics/bubblegum_96/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_BUBBLEGUM_96
-
-config SYS_BOARD
-	default "bubblegum_96"
-
-config SYS_VENDOR
-	default "ucRobotics"
-
-config SYS_SOC
-	default "s900"
-
-config SYS_CONFIG_NAME
-	default "bubblegum_96"
-
-endif
diff --git a/board/ucRobotics/bubblegum_96/MAINTAINERS b/board/ucRobotics/bubblegum_96/MAINTAINERS
deleted file mode 100644
index d0cb727..0000000
--- a/board/ucRobotics/bubblegum_96/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BUBBLEGUM_96 BOARD
-M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-S:	Maintained
-F:	board/ucRobotics/bubblegum_96/
-F:	include/configs/bubblegum_96.h
-F:	configs/bubblegum_96_defconfig
diff --git a/board/ucRobotics/bubblegum_96/Makefile b/board/ucRobotics/bubblegum_96/Makefile
deleted file mode 100644
index c4b524d..0000000
--- a/board/ucRobotics/bubblegum_96/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier:	GPL-2.0+
-
-obj-y   := bubblegum_96.o
diff --git a/board/ucRobotics/bubblegum_96/bubblegum_96.c b/board/ucRobotics/bubblegum_96/bubblegum_96.c
deleted file mode 100644
index c16f117..0000000
--- a/board/ucRobotics/bubblegum_96/bubblegum_96.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Bubblegum-96 Boards Support
- *
- * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- */
-
-#include <cpu_func.h>
-#include <linux/arm-smccc.h>
-#include <linux/psci.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/psci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * dram_init - sets uboots idea of sdram size
- */
-int dram_init(void)
-{
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-	return 0;
-}
-
-/* This is called after dram_init() so use get_ram_size result */
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = gd->ram_size;
-
-	return 0;
-}
-
-static void show_psci_version(void)
-{
-	struct arm_smccc_res res;
-
-	arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
-
-	printf("PSCI:  v%ld.%ld\n",
-	       PSCI_VERSION_MAJOR(res.a0),
-		PSCI_VERSION_MINOR(res.a0));
-}
-
-int board_init(void)
-{
-	show_psci_version();
-
-	return 0;
-}
-
-void reset_cpu(ulong addr)
-{
-	psci_system_reset();
-}
diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig
index ae44ce1..8c94def 100644
--- a/configs/bubblegum_96_defconfig
+++ b/configs/bubblegum_96_defconfig
@@ -1,9 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_OWL=y
-CONFIG_SYS_TEXT_BASE=0x11000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_TARGET_BUBBLEGUM_96=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_MACH_S900=y
 CONFIG_IDENT_STRING="\nBubblegum-96"
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=5
@@ -21,4 +20,3 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_CLK=y
 CONFIG_CLK_OWL=y
 CONFIG_CLK_S900=y
-CONFIG_OWL_SERIAL=y
diff --git a/include/configs/bubblegum_96.h b/include/configs/bubblegum_96.h
deleted file mode 100644
index c739d66..0000000
--- a/include/configs/bubblegum_96.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Board configuration file for Bubblegum-96
- *
- * Copyright (C) 2015 Actions Semi Co., Ltd.
- * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- *
- */
-
-#ifndef _BUBBLEGUM_96_H_
-#define _BUGGLEGUM_96_H_
-
-/* SDRAM Definitions */
-#define CONFIG_SYS_SDRAM_BASE		0x0
-#define CONFIG_SYS_SDRAM_SIZE		0x80000000
-
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY		(24000000)	/* 24MHz */
-
-#define CONFIG_SYS_MALLOC_LEN		(32 * 1024 * 1024)
-
-/* Some commands use this as the default load address */
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7ffc0)
-
-/*
- * This is the initial SP which is used only briefly for relocating the u-boot
- * image to the top of SDRAM. After relocation u-boot moves the stack to the
- * proper place.
- */
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x7ff00)
-
-/* UART Definitions */
-#define CONFIG_BAUDRATE			115200
-
-/* Console configuration */
-#define CONFIG_SYS_CBSIZE		1024	/* Console buffer size */
-#define CONFIG_SYS_MAXARGS		64
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#endif
diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h
new file mode 100644
index 0000000..f77a5fa
--- /dev/null
+++ b/include/configs/owl-common.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board configuration file for Actions Semi Owl SoCs.
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _OWL_COMMON_CONFIG_H_
+#define _OWL_COMMON_CONFIG_H_
+
+/* SDRAM Definitions */
+#define CONFIG_SYS_SDRAM_BASE		0x0
+#define CONFIG_SYS_SDRAM_SIZE		0x80000000
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		(24000000)	/* 24MHz */
+
+#define CONFIG_SYS_MALLOC_LEN		(32 * 1024 * 1024)
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7ffc0)
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x7ff00)
+
+/* UART Definitions */
+#define CONFIG_BAUDRATE			115200
+
+/* Console configuration */
+#define CONFIG_SYS_CBSIZE		1024	/* Console buffer size */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#endif
diff --git a/include/configs/s900.h b/include/configs/s900.h
new file mode 100644
index 0000000..7544cfc
--- /dev/null
+++ b/include/configs/s900.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _CONFIG_S900_H_
+#define _CONFIG_S900_H_
+
+/*
+ * Include common owl configuration where most the settings are
+ */
+#include <configs/owl-common.h>
+
+#endif
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH v7 02/12] arm: actions: rename sysmap-s900 to sysmap-owl
  2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 01/12] arm: actions: Add common framework for Actions Owl Semi SoCs Amit Singh Tomar
@ 2020-03-20 17:35 ` Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 03/12] serial: actions: add compatible string Amit Singh Tomar
                   ` (9 subsequent siblings)
  11 siblings, 0 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

Now that memory maps(for both S700 and S900 SoCs) can be managed using
a common file, rename sysmap-s900 to sysmap-owl to reflect the same.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v6:
	* No changes.
Changes since v5:
        * No changes.
Changes since v4:
        * No changes.
Changes since v3:
        * Added reviewed-by tag.
Changes since v2:
        * Fixed the commit message and header.
Changes since v1:
        * compile sysmap-owl.c against CONFIG_ARM64 now.
---
 arch/arm/mach-owl/Makefile      |  2 +-
 arch/arm/mach-owl/sysmap-owl.c  | 32 ++++++++++++++++++++++++++++++++
 arch/arm/mach-owl/sysmap-s900.c | 32 --------------------------------
 3 files changed, 33 insertions(+), 33 deletions(-)
 create mode 100644 arch/arm/mach-owl/sysmap-owl.c
 delete mode 100644 arch/arm/mach-owl/sysmap-s900.c

diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile
index 0b181c6..f3a69eb 100644
--- a/arch/arm/mach-owl/Makefile
+++ b/arch/arm/mach-owl/Makefile
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y += soc.o
-obj-y += sysmap-s900.o
+obj-$(CONFIG_ARM64) += sysmap-owl.o
diff --git a/arch/arm/mach-owl/sysmap-owl.c b/arch/arm/mach-owl/sysmap-owl.c
new file mode 100644
index 0000000..81f6ca2
--- /dev/null
+++ b/arch/arm/mach-owl/sysmap-owl.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Memory map for Actions Semi Owl series SoCs.
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region owl_mem_map[] = {
+	{
+		.virt = 0x0UL, /* DDR */
+		.phys = 0x0UL, /* DDR */
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xE0000000UL, /* Peripheral block */
+		.phys = 0xE0000000UL, /* Peripheral block */
+		.size = 0x08000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = owl_mem_map;
diff --git a/arch/arm/mach-owl/sysmap-s900.c b/arch/arm/mach-owl/sysmap-s900.c
deleted file mode 100644
index f78b639..0000000
--- a/arch/arm/mach-owl/sysmap-s900.c
+++ /dev/null
@@ -1,32 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Actions Semi S900 Memory map
- *
- * Copyright (C) 2015 Actions Semi Co., Ltd.
- * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- */
-
-#include <common.h>
-#include <asm/armv8/mmu.h>
-
-static struct mm_region s900_mem_map[] = {
-	{
-		.virt = 0x0UL, /* DDR */
-		.phys = 0x0UL, /* DDR */
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0xE0000000UL, /* Peripheral block */
-		.phys = 0xE0000000UL, /* Peripheral block */
-		.size = 0x08000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		/* List terminator */
-		0,
-	}
-};
-
-struct mm_region *mem_map = s900_mem_map;
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH v7 03/12] serial: actions: add compatible string
  2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 01/12] arm: actions: Add common framework for Actions Owl Semi SoCs Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 02/12] arm: actions: rename sysmap-s900 to sysmap-owl Amit Singh Tomar
@ 2020-03-20 17:35 ` Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 04/12] arm: dts: sync dts for Action Semi S900 Amit Singh Tomar
                   ` (8 subsequent siblings)
  11 siblings, 0 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

This patch adds "actions,owl-uart" string to the owl uart driver. It
is also defined in Linux kernel.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v6:
	* Added Reviewd-by tag.
Changes since v5:
        * Moved it to from 06/11 to 03/11.
        * Used appropriate commit message.
        * Removed the reviwed-by tag.
Changes since v4:
        * Moved it to from 09/11 to 06/11.
Changes since v3:
        * Used only owl-uart for compatible string.
Changes since v2:
        * No changes.
Changes since v1:
        * No changes.
---
 drivers/serial/serial_owl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c
index 7ead73e..539acdc 100644
--- a/drivers/serial/serial_owl.c
+++ b/drivers/serial/serial_owl.c
@@ -121,6 +121,7 @@ static const struct dm_serial_ops owl_serial_ops = {
 
 static const struct udevice_id owl_serial_ids[] = {
 	{ .compatible =	"actions,s900-serial" },
+	{ .compatible = "actions,owl-uart" },
 	{ }
 };
 
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH v7 04/12] arm: dts: sync dts for Action Semi S900
  2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
                   ` (2 preceding siblings ...)
  2020-03-20 17:35 ` [PATCH v7 03/12] serial: actions: add compatible string Amit Singh Tomar
@ 2020-03-20 17:35 ` Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 05/12] arm: dts: actions: s900: add u-boot specific dtsi file Amit Singh Tomar
                   ` (7 subsequent siblings)
  11 siblings, 0 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

Synchronize device tree bindings with v5.5-rc6 tag with commit id
"b3a987b0264d".

Also, it removes older clock binding defined for S900 along with undocumented
compatible string "actions,s900-serial" from serial driver and adapts clock
driver to cater to new bindings.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v6:
	* Added Reviewed-by tag.
Changes since v5:
        * Moved it 04/11 from 03/11.
        * removed the undocumented compatible string "actions,s900-serial".
        * removed the reviewed-by tag.
Changes since v4:
        * This patch is re-ordered, moved from 07/11 to 03/11.
        * Used the commit-id(12 chars long) in commit message.
Changes since v3:
        * Added Reviewed-by: tag.
Changes since v2:
        * Newly added patch, not there in v2/v1.
---
 arch/arm/dts/s900.dtsi                         | 322 +++++++++++++++++++++++--
 drivers/clk/owl/clk_s900.c                     |   6 +-
 drivers/serial/serial_owl.c                    |   1 -
 include/dt-bindings/clock/actions,s900-cmu.h   | 129 ++++++++++
 include/dt-bindings/clock/s900_cmu.h           |  77 ------
 include/dt-bindings/reset/actions,s900-reset.h |  65 +++++
 6 files changed, 498 insertions(+), 102 deletions(-)
 create mode 100644 include/dt-bindings/clock/actions,s900-cmu.h
 delete mode 100644 include/dt-bindings/clock/s900_cmu.h
 create mode 100644 include/dt-bindings/reset/actions,s900-reset.h

diff --git a/arch/arm/dts/s900.dtsi b/arch/arm/dts/s900.dtsi
index 2bbb30a..eb35cf7 100644
--- a/arch/arm/dts/s900.dtsi
+++ b/arch/arm/dts/s900.dtsi
@@ -1,17 +1,94 @@
-// SPDX-License-Identifier: GPL-2.0+
-//
-// Device Tree Source for Actions Semi S900 SoC
-//
-// Copyright (C) 2015 Actions Semi Co., Ltd.
-// Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Andreas F?rber
+ */
 
-/dts-v1/;
-#include <dt-bindings/clock/s900_cmu.h>
+#include <dt-bindings/clock/actions,s900-cmu.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/actions,s900-reset.h>
 
 / {
 	compatible = "actions,s900";
-	#address-cells = <0x2>;
-	#size-cells = <0x2>;
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secmon at 1f000000 {
+			reg = <0x0 0x1f000000 0x0 0x1000000>;
+			no-map;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	hosc: hosc {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		#clock-cells = <0>;
+	};
 
 	losc: losc {
 		compatible = "fixed-clock";
@@ -26,28 +103,231 @@
 	};
 
 	soc {
-		u-boot,dm-pre-reloc;
 		compatible = "simple-bus";
-		#address-cells = <0x2>;
-		#size-cells = <0x2>;
+		#address-cells = <2>;
+		#size-cells = <2>;
 		ranges;
 
+		gic: interrupt-controller at e00f1000 {
+			compatible = "arm,gic-400";
+			reg = <0x0 0xe00f1000 0x0 0x1000>,
+			      <0x0 0xe00f2000 0x0 0x2000>,
+			      <0x0 0xe00f4000 0x0 0x2000>,
+			      <0x0 0xe00f6000 0x0 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		uart0: serial at e0120000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0120000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART0>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart1: serial at e0122000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0122000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART1>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart2: serial at e0124000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0124000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART2>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart3: serial at e0126000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0126000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART3>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart4: serial at e0128000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0128000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART4>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
 		uart5: serial at e012a000 {
-			u-boot,dm-pre-reloc;
-			compatible = "actions,s900-serial";
-			reg = <0x0 0xe012a000 0x0 0x1000>;
-			clocks = <&cmu CLOCK_UART5>;
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe012a000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART5>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
 
+		uart6: serial at e012c000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe012c000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART6>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		sps: power-controller at e012e000 {
+			compatible = "actions,s900-sps";
+			reg = <0x0 0xe012e000 0x0 0x2000>;
+			#power-domain-cells = <1>;
+		};
+
 		cmu: clock-controller at e0160000 {
-			u-boot,dm-pre-reloc;
 			compatible = "actions,s900-cmu";
 			reg = <0x0 0xe0160000 0x0 0x1000>;
-			clocks = <&losc>, <&diff24M>;
-			clock-names = "losc", "diff24M";
+			clocks = <&hosc>, <&losc>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		i2c0: i2c at e0170000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe0170000 0 0x1000>;
+			clocks = <&cmu CLK_I2C0>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at e0172000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe0172000 0 0x1000>;
+			clocks = <&cmu CLK_I2C1>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at e0174000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe0174000 0 0x1000>;
+			clocks = <&cmu CLK_I2C2>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c at e0176000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe0176000 0 0x1000>;
+			clocks = <&cmu CLK_I2C3>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c at e0178000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe0178000 0 0x1000>;
+			clocks = <&cmu CLK_I2C4>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c5: i2c at e017a000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe017a000 0 0x1000>;
+			clocks = <&cmu CLK_I2C5>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl at e01b0000 {
+			compatible = "actions,s900-pinctrl";
+			reg = <0x0 0xe01b0000 0x0 0x1000>;
+			clocks = <&cmu CLK_GPIO>;
+			gpio-controller;
+			gpio-ranges = <&pinctrl 0 0 146>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		timer: timer at e0228000 {
+			compatible = "actions,s900-timer";
+			reg = <0x0 0xe0228000 0x0 0x8000>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "timer1";
+		};
+
+		dma: dma-controller at e0260000 {
+			compatible = "actions,s900-dma";
+			reg = <0x0 0xe0260000 0x0 0x1000>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			dma-channels = <12>;
+			dma-requests = <46>;
+			clocks = <&cmu CLK_DMAC>;
+		};
+
+		mmc0: mmc at e0330000 {
+			compatible = "actions,owl-mmc";
+			reg = <0x0 0xe0330000 0x0 0x4000>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_SD0>;
+			resets = <&cmu RESET_SD0>;
+			dmas = <&dma 2>;
+			dma-names = "mmc";
+			status = "disabled";
+		};
+
+		mmc1: mmc at e0334000 {
+			compatible = "actions,owl-mmc";
+			reg = <0x0 0xe0334000 0x0 0x4000>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_SD1>;
+			resets = <&cmu RESET_SD1>;
+			dmas = <&dma 3>;
+			dma-names = "mmc";
+			status = "disabled";
+		};
+
+		mmc2: mmc at e0338000 {
+			compatible = "actions,owl-mmc";
+			reg = <0x0 0xe0338000 0x0 0x4000>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_SD2>;
+			resets = <&cmu RESET_SD2>;
+			dmas = <&dma 4>;
+			dma-names = "mmc";
+			status = "disabled";
+		};
+
+		mmc3: mmc at e033c000 {
+			compatible = "actions,owl-mmc";
+			reg = <0x0 0xe033c000 0x0 0x4000>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu CLK_SD3>;
+			resets = <&cmu RESET_SD3>;
+			dmas = <&dma 46>;
+			dma-names = "mmc";
+			status = "disabled";
 		};
 	};
 };
-
diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_s900.c
index a7c15d2..d60f199 100644
--- a/drivers/clk/owl/clk_s900.c
+++ b/drivers/clk/owl/clk_s900.c
@@ -12,7 +12,7 @@
 #include <asm/arch-owl/regs_s900.h>
 #include <asm/io.h>
 
-#include <dt-bindings/clock/s900_cmu.h>
+#include <dt-bindings/clock/actions,s900-cmu.h>
 
 void owl_clk_init(struct owl_clk_priv *priv)
 {
@@ -78,7 +78,7 @@ int owl_clk_enable(struct clk *clk)
 	struct owl_clk_priv *priv = dev_get_priv(clk->dev);
 
 	switch (clk->id) {
-	case CLOCK_UART5:
+	case CLK_UART5:
 		owl_uart_clk_enable(priv);
 		break;
 	default:
@@ -93,7 +93,7 @@ int owl_clk_disable(struct clk *clk)
 	struct owl_clk_priv *priv = dev_get_priv(clk->dev);
 
 	switch (clk->id) {
-	case CLOCK_UART5:
+	case CLK_UART5:
 		owl_uart_clk_disable(priv);
 		break;
 	default:
diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c
index 539acdc..bb60ca2 100644
--- a/drivers/serial/serial_owl.c
+++ b/drivers/serial/serial_owl.c
@@ -120,7 +120,6 @@ static const struct dm_serial_ops owl_serial_ops = {
 };
 
 static const struct udevice_id owl_serial_ids[] = {
-	{ .compatible =	"actions,s900-serial" },
 	{ .compatible = "actions,owl-uart" },
 	{ }
 };
diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h
new file mode 100644
index 0000000..7c12515
--- /dev/null
+++ b/include/dt-bindings/clock/actions,s900-cmu.h
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree binding constants for Actions Semi S900 Clock Management Unit
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
+#define __DT_BINDINGS_CLOCK_S900_CMU_H
+
+#define CLK_NONE			0
+
+/* fixed rate clocks */
+#define CLK_LOSC			1
+#define CLK_HOSC			2
+
+/* pll clocks */
+#define CLK_CORE_PLL			3
+#define CLK_DEV_PLL			4
+#define CLK_DDR_PLL			5
+#define CLK_NAND_PLL			6
+#define CLK_DISPLAY_PLL			7
+#define CLK_DSI_PLL			8
+#define CLK_ASSIST_PLL			9
+#define CLK_AUDIO_PLL			10
+
+/* system clock */
+#define CLK_CPU				15
+#define CLK_DEV				16
+#define CLK_NOC				17
+#define CLK_NOC_MUX			18
+#define CLK_NOC_DIV			19
+#define CLK_AHB				20
+#define CLK_APB				21
+#define CLK_DMAC			22
+
+/* peripheral device clock */
+#define CLK_GPIO			23
+
+#define CLK_BISP			24
+#define CLK_CSI0			25
+#define CLK_CSI1			26
+
+#define CLK_DE0				27
+#define CLK_DE1				28
+#define CLK_DE2				29
+#define CLK_DE3				30
+#define CLK_DSI				32
+
+#define CLK_GPU				33
+#define CLK_GPU_CORE			34
+#define CLK_GPU_MEM			35
+#define CLK_GPU_SYS			36
+
+#define CLK_HDE				37
+#define CLK_I2C0			38
+#define CLK_I2C1			39
+#define CLK_I2C2			40
+#define CLK_I2C3			41
+#define CLK_I2C4			42
+#define CLK_I2C5			43
+#define CLK_I2SRX			44
+#define CLK_I2STX			45
+#define CLK_IMX				46
+#define CLK_LCD				47
+#define CLK_NAND0			48
+#define CLK_NAND1			49
+#define CLK_PWM0			50
+#define CLK_PWM1			51
+#define CLK_PWM2			52
+#define CLK_PWM3			53
+#define CLK_PWM4			54
+#define CLK_PWM5			55
+#define CLK_SD0				56
+#define CLK_SD1				57
+#define CLK_SD2				58
+#define CLK_SD3				59
+#define CLK_SENSOR			60
+#define CLK_SPEED_SENSOR		61
+#define CLK_SPI0			62
+#define CLK_SPI1			63
+#define CLK_SPI2			64
+#define CLK_SPI3			65
+#define CLK_THERMAL_SENSOR		66
+#define CLK_UART0			67
+#define CLK_UART1			68
+#define CLK_UART2			69
+#define CLK_UART3			70
+#define CLK_UART4			71
+#define CLK_UART5			72
+#define CLK_UART6			73
+#define CLK_VCE				74
+#define CLK_VDE				75
+
+#define CLK_USB3_480MPLL0		76
+#define CLK_USB3_480MPHY0		77
+#define CLK_USB3_5GPHY			78
+#define CLK_USB3_CCE			79
+#define CLK_USB3_MAC			80
+
+#define CLK_TIMER			83
+
+#define CLK_HDMI_AUDIO			84
+
+#define CLK_24M				85
+
+#define CLK_EDP				86
+
+#define CLK_24M_EDP			87
+#define CLK_EDP_PLL			88
+#define CLK_EDP_LINK			89
+
+#define CLK_USB2H0_PLLEN		90
+#define CLK_USB2H0_PHY			91
+#define CLK_USB2H0_CCE			92
+#define CLK_USB2H1_PLLEN		93
+#define CLK_USB2H1_PHY			94
+#define CLK_USB2H1_CCE			95
+
+#define CLK_DDR0			96
+#define CLK_DDR1			97
+#define CLK_DMM				98
+
+#define CLK_ETH_MAC			99
+#define CLK_RMII_REF			100
+
+#define CLK_NR_CLKS			(CLK_RMII_REF + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
diff --git a/include/dt-bindings/clock/s900_cmu.h b/include/dt-bindings/clock/s900_cmu.h
deleted file mode 100644
index 2685a6d..0000000
--- a/include/dt-bindings/clock/s900_cmu.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Actions Semi Co., Ltd.
- * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- *
- */
-
-#ifndef _DT_BINDINGS_CLOCK_S900_CMU_H_
-#define _DT_BINDINGS_CLOCK_S900_CMU_H_
-
-/* Module Clock ID */
-#define CLOCK_DDRCH1				0
-#define CLOCK_DMAC				1
-#define CLOCK_DDRCH0				2
-#define CLOCK_BROM				3
-#define CLOCK_NANDC0				4
-#define CLOCK_SD0				5
-#define CLOCK_SD1				6
-#define CLOCK_SD2				7
-#define CLOCK_DE				8
-#define CLOCK_LVDS				9
-#define CLOCK_EDP				10
-#define CLOCK_NANDC1				11
-#define CLOCK_DSI				12
-#define CLOCK_CSI0				13
-#define CLOCK_BISP				14
-#define CLOCK_CSI1				15
-#define CLOCK_SD3				16
-#define CLOCK_I2C4				17
-#define CLOCK_GPIO				18
-#define CLOCK_DMM				19
-#define CLOCK_I2STX				20
-#define CLOCK_I2SRX				21
-#define CLOCK_HDMIA				22
-#define CLOCK_SPDIF				23
-#define CLOCK_PCM0				24
-#define CLOCK_VDE				25
-#define CLOCK_VCE				26
-#define CLOCK_HDE				27
-#define CLOCK_SHARESRAM				28
-#define CLOCK_CMU_DDR1				29
-#define CLOCK_GPU3D				30
-#define CLOCK_CMUDDR0				31
-#define CLOCK_SPEED				32
-#define CLOCK_I2C5				33
-#define CLOCK_THERMAL				34
-#define CLOCK_HDMI				35
-#define CLOCK_PWM4				36
-#define CLOCK_PWM5				37
-#define CLOCK_UART0				38
-#define CLOCK_UART1				39
-#define CLOCK_UART2				40
-#define CLOCK_IRC				41
-#define CLOCK_SPI0				42
-#define CLOCK_SPI1				43
-#define CLOCK_SPI2				44
-#define CLOCK_SPI3				45
-#define CLOCK_I2C0				46
-#define CLOCK_I2C1				47
-#define CLOCK_PCM1				48
-#define CLOCK_IMX				49
-#define CLOCK_UART6				50
-#define CLOCK_UART3				51
-#define CLOCK_UART4				52
-#define CLOCK_UART5				53
-#define CLOCK_ETHERNET				54
-#define CLOCK_PWM0				55
-#define CLOCK_PWM1				56
-#define CLOCK_PWM2				57
-#define CLOCK_PWM3				58
-#define CLOCK_TIMER				59
-#define CLOCK_SE				60
-#define CLOCK_HDCP2TX				61
-#define CLOCK_I2C2				62
-#define CLOCK_I2C3				63
-
-#endif
diff --git a/include/dt-bindings/reset/actions,s900-reset.h b/include/dt-bindings/reset/actions,s900-reset.h
new file mode 100644
index 0000000..42c19d0
--- /dev/null
+++ b/include/dt-bindings/reset/actions,s900-reset.h
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+//
+// Device Tree binding constants for Actions Semi S900 Reset Management Unit
+//
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H
+#define __DT_BINDINGS_ACTIONS_S900_RESET_H
+
+#define RESET_CHIPID				0
+#define RESET_CPU_SCNT				1
+#define RESET_SRAMI				2
+#define RESET_DDR_CTL_PHY			3
+#define RESET_DMAC				4
+#define RESET_GPIO				5
+#define RESET_BISP_AXI				6
+#define RESET_CSI0				7
+#define RESET_CSI1				8
+#define RESET_DE				9
+#define RESET_DSI				10
+#define RESET_GPU3D_PA				11
+#define RESET_GPU3D_PB				12
+#define RESET_HDE				13
+#define RESET_I2C0				14
+#define RESET_I2C1				15
+#define RESET_I2C2				16
+#define RESET_I2C3				17
+#define RESET_I2C4				18
+#define RESET_I2C5				19
+#define RESET_IMX				20
+#define RESET_NANDC0				21
+#define RESET_NANDC1				22
+#define RESET_SD0				23
+#define RESET_SD1				24
+#define RESET_SD2				25
+#define RESET_SD3				26
+#define RESET_SPI0				27
+#define RESET_SPI1				28
+#define RESET_SPI2				29
+#define RESET_SPI3				30
+#define RESET_UART0				31
+#define RESET_UART1				32
+#define RESET_UART2				33
+#define RESET_UART3				34
+#define RESET_UART4				35
+#define RESET_UART5				36
+#define RESET_UART6				37
+#define RESET_HDMI				38
+#define RESET_LVDS				39
+#define RESET_EDP				40
+#define RESET_USB2HUB				41
+#define RESET_USB2HSIC				42
+#define RESET_USB3				43
+#define RESET_PCM1				44
+#define RESET_AUDIO				45
+#define RESET_PCM0				46
+#define RESET_SE				47
+#define RESET_GIC				48
+#define RESET_DDR_CTL_PHY_AXI			49
+#define RESET_CMU_DDR				50
+#define RESET_DMM				51
+#define RESET_HDCP2TX				52
+#define RESET_ETHERNET				53
+
+#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH v7 05/12] arm: dts: actions: s900: add u-boot specific dtsi file
  2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
                   ` (3 preceding siblings ...)
  2020-03-20 17:35 ` [PATCH v7 04/12] arm: dts: sync dts for Action Semi S900 Amit Singh Tomar
@ 2020-03-20 17:35 ` Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 06/12] clk: actions: Add common clock driver Amit Singh Tomar
                   ` (6 subsequent siblings)
  11 siblings, 0 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

Devices like uart and clk are needed to be enabled before relocation.
This patch adds u-boot.dtsi file that mark these device as dm-pre-reloc.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v6:
        * No changes.
Changes since v5:
        * No changes.
Changes since v4:
        * This patch is re-ordered, moved from 08/11 to 04/11.
Changes since v3:
        * Replaced dtsi with dts in subject line along with arm:dts:
          to the prefix.
        * Added reviewed-by tag.
Changes since v2:
        * Newly added patch, not there in v2/v1.
---
 arch/arm/dts/s900-u-boot.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 arch/arm/dts/s900-u-boot.dtsi

diff --git a/arch/arm/dts/s900-u-boot.dtsi b/arch/arm/dts/s900-u-boot.dtsi
new file mode 100644
index 0000000..a95f2cc
--- /dev/null
+++ b/arch/arm/dts/s900-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ */
+
+/{
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&uart5 {
+	u-boot,dm-pre-reloc;
+};
+
+&cmu {
+	u-boot,dm-pre-reloc;
+};
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH v7 06/12] clk: actions: Add common clock driver
  2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
                   ` (4 preceding siblings ...)
  2020-03-20 17:35 ` [PATCH v7 05/12] arm: dts: actions: s900: add u-boot specific dtsi file Amit Singh Tomar
@ 2020-03-20 17:35 ` Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 07/12] arm: actions: add S700 SoC device tree Amit Singh Tomar
                   ` (5 subsequent siblings)
  11 siblings, 0 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

This patch converts S900 clock driver to something common that can
be used for other SoCs, for instance S700(few of clk registers are same).

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v6:
	* Fixed the bug that breaks S900(missing break in switch statement).
Changes since v5:
        * No changes.
Changes since v4:
        * This patch is re-ordered, moved from 08/11 to 04/11.
Changes since v3:
        * Replaced dtsi with dts in subject line along with arm:dts:
          to the prefix.
        * Added reviewed-by tag.
Changes since v2:
        * Newly added patch, not there in v2/v1.
---
 arch/arm/Kconfig                          |   2 +
 arch/arm/include/asm/arch-owl/clk_s900.h  |  57 -----------
 arch/arm/include/asm/arch-owl/regs_s700.h |  56 +++++++++++
 configs/bubblegum_96_defconfig            |   3 -
 drivers/clk/owl/Kconfig                   |   8 +-
 drivers/clk/owl/Makefile                  |   2 +-
 drivers/clk/owl/clk_owl.c                 | 153 ++++++++++++++++++++++++++++++
 drivers/clk/owl/clk_owl.h                 |  65 +++++++++++++
 drivers/clk/owl/clk_s900.c                | 137 --------------------------
 9 files changed, 279 insertions(+), 204 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h
 create mode 100644 arch/arm/include/asm/arch-owl/regs_s700.h
 create mode 100644 drivers/clk/owl/clk_owl.c
 create mode 100644 drivers/clk/owl/clk_owl.h
 delete mode 100644 drivers/clk/owl/clk_s900.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1cfdcb6..dba4d8c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -876,6 +876,8 @@ config ARCH_OWL
 	select DM
 	select DM_SERIAL
 	select OWL_SERIAL
+	select CLK
+	select CLK_OWL
 	select OF_CONTROL
 	imply CMD_DM
 
diff --git a/arch/arm/include/asm/arch-owl/clk_s900.h b/arch/arm/include/asm/arch-owl/clk_s900.h
deleted file mode 100644
index 88e88f7..0000000
--- a/arch/arm/include/asm/arch-owl/clk_s900.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Actions Semi S900 Clock Definitions
- *
- * Copyright (C) 2015 Actions Semi Co., Ltd.
- * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- *
- */
-
-#ifndef _OWL_CLK_S900_H_
-#define _OWL_CLK_S900_H_
-
-#include <clk-uclass.h>
-
-struct owl_clk_priv {
-	phys_addr_t base;
-};
-
-/* BUSCLK register definitions */
-#define CMU_PDBGDIV_8		7
-#define CMU_PDBGDIV_SHIFT	26
-#define CMU_PDBGDIV_DIV		(CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
-#define CMU_PERDIV_8		7
-#define CMU_PERDIV_SHIFT	20
-#define CMU_PERDIV_DIV		(CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
-#define CMU_NOCDIV_2		1
-#define CMU_NOCDIV_SHIFT	19
-#define CMU_NOCDIV_DIV		(CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
-#define CMU_DMMCLK_SRC_APLL	2
-#define CMU_DMMCLK_SRC_SHIFT	10
-#define CMU_DMMCLK_SRC		(CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT)
-#define CMU_APBCLK_DIV		BIT(8)
-#define CMU_NOCCLK_SRC		BIT(7)
-#define CMU_AHBCLK_DIV		BIT(4)
-#define CMU_CORECLK_MASK	3
-#define CMU_CORECLK_CPLL	BIT(1)
-#define CMU_CORECLK_HOSC	BIT(0)
-
-/* COREPLL register definitions */
-#define CMU_COREPLL_EN		BIT(9)
-#define CMU_COREPLL_HOSC_EN	BIT(8)
-#define CMU_COREPLL_OUT		(1104 / 24)
-
-/* DEVPLL register definitions */
-#define CMU_DEVPLL_CLK		BIT(12)
-#define CMU_DEVPLL_EN		BIT(8)
-#define CMU_DEVPLL_OUT		(660 / 6)
-
-/* UARTCLK register definitions */
-#define CMU_UARTCLK_SRC_DEVPLL	BIT(16)
-
-/* DEVCLKEN1 register definitions */
-#define CMU_DEVCLKEN1_UART5	BIT(21)
-
-#define PLL_STABILITY_WAIT_US	50
-
-#endif
diff --git a/arch/arm/include/asm/arch-owl/regs_s700.h b/arch/arm/include/asm/arch-owl/regs_s700.h
new file mode 100644
index 0000000..2f21c15
--- /dev/null
+++ b/arch/arm/include/asm/arch-owl/regs_s700.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Actions Semi S700 Register Definitions
+ *
+ */
+
+#ifndef _OWL_REGS_S700_H_
+#define _OWL_REGS_S700_H_
+
+#define CMU_COREPLL		0x0000
+#define CMU_DEVPLL		0x0004
+#define CMU_DDRPLL		0x0008
+#define CMU_NANDPLL		0x000C
+#define CMU_DISPLAYPLL		0x0010
+#define CMU_AUDIOPLL		0x0014
+#define CMU_TVOUTPLL		0x0018
+#define CMU_BUSCLK		0x001C
+#define CMU_SENSORCLK		0x0020
+#define CMU_LCDCLK		0x0024
+#define CMU_DSIPLLCLK		0x0028
+#define CMU_CSICLK		0x002C
+#define CMU_DECLK		0x0030
+#define CMU_SICLK		0x0034
+#define CMU_BUSCLK1		0x0038
+#define CMU_HDECLK		0x003C
+#define CMU_VDECLK		0x0040
+#define CMU_VCECLK		0x0044
+#define CMU_NANDCCLK		0x004C
+#define CMU_SD0CLK		0x0050
+#define CMU_SD1CLK		0x0054
+#define CMU_SD2CLK		0x0058
+#define CMU_UART0CLK		0x005C
+#define CMU_UART1CLK		0x0060
+#define CMU_UART2CLK		0x0064
+#define CMU_UART3CLK		0x0068
+#define CMU_UART4CLK		0x006C
+#define CMU_UART5CLK		0x0070
+#define CMU_UART6CLK		0x0074
+#define CMU_PWM0CLK		0x0078
+#define CMU_PWM1CLK		0x007C
+#define CMU_PWM2CLK		0x0080
+#define CMU_PWM3CLK		0x0084
+#define CMU_PWM4CLK		0x0088
+#define CMU_PWM5CLK		0x008C
+#define CMU_GPU3DCLK		0x0090
+#define CMU_CORECTL		0x009C
+#define CMU_DEVCLKEN0		0x00A0
+#define CMU_DEVCLKEN1		0x00A4
+#define CMU_DEVRST0		0x00A8
+#define CMU_DEVRST1		0x00AC
+#define CMU_USBPLL		0x00B0
+#define CMU_ETHERNETPLL		0x00B4
+#define CMU_CVBSPLL		0x00B8
+#define CMU_SSTSCLK		0x00C0
+
+#endif
diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig
index 8c94def..e76e9a2 100644
--- a/configs/bubblegum_96_defconfig
+++ b/configs/bubblegum_96_defconfig
@@ -17,6 +17,3 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
 CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_CLK=y
-CONFIG_CLK_OWL=y
-CONFIG_CLK_S900=y
diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig
index 661f198..c6afef9 100644
--- a/drivers/clk/owl/Kconfig
+++ b/drivers/clk/owl/Kconfig
@@ -3,10 +3,6 @@ config CLK_OWL
         depends on CLK && ARCH_OWL
         help
           Enable support for clock managemet unit present in Actions Semi
-	  OWL SoCs.
+	  Owl series S900/S700 SoCs.
+
 
-config CLK_S900
-        bool "Actions Semi S900 clock driver"
-        depends on CLK_OWL && ARM64
-        help
-          Enable support for the clocks in Actions Semi S900 SoC.
diff --git a/drivers/clk/owl/Makefile b/drivers/clk/owl/Makefile
index 63ab573..5218b6b 100644
--- a/drivers/clk/owl/Makefile
+++ b/drivers/clk/owl/Makefile
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-obj-$(CONFIG_CLK_S900) += clk_s900.o
+obj-$(CONFIG_CLK_OWL) += clk_owl.o
diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c
new file mode 100644
index 0000000..9f114c7
--- /dev/null
+++ b/drivers/clk/owl/clk_owl.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Common clock driver for Actions Semi SoCs.
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include "clk_owl.h"
+#include <asm/io.h>
+#if defined(CONFIG_MACH_S900)
+#include <asm/arch-owl/regs_s900.h>
+#include <dt-bindings/clock/actions,s900-cmu.h>
+#elif defined(CONFIG_MACH_S700)
+#include <asm/arch-owl/regs_s700.h>
+#include <dt-bindings/clock/actions,s700-cmu.h>
+#endif
+
+void owl_clk_init(struct owl_clk_priv *priv)
+{
+	u32 bus_clk = 0, core_pll, dev_pll;
+
+#if defined(CONFIG_MACH_S900)
+	/* Enable ASSIST_PLL */
+	setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
+	udelay(PLL_STABILITY_WAIT_US);
+#endif
+
+	/* Source HOSC to DEV_CLK */
+	clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
+
+	/* Configure BUS_CLK */
+	bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |
+			CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
+			CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
+	writel(bus_clk, priv->base + CMU_BUSCLK);
+
+	udelay(PLL_STABILITY_WAIT_US);
+
+	/* Configure CORE_PLL */
+	core_pll = readl(priv->base + CMU_COREPLL);
+	core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
+	writel(core_pll, priv->base + CMU_COREPLL);
+
+	udelay(PLL_STABILITY_WAIT_US);
+
+	/* Configure DEV_PLL */
+	dev_pll = readl(priv->base + CMU_DEVPLL);
+	dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
+	writel(dev_pll, priv->base + CMU_DEVPLL);
+
+	udelay(PLL_STABILITY_WAIT_US);
+
+	/* Source CORE_PLL for CORE_CLK */
+	clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
+			CMU_CORECLK_CPLL);
+
+	/* Source DEV_PLL for DEV_CLK */
+	setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
+
+	udelay(PLL_STABILITY_WAIT_US);
+}
+
+int owl_clk_enable(struct clk *clk)
+{
+	struct owl_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case CLK_UART5:
+		if (priv->soc == S700)
+			return -EINVAL;
+		/* Source HOSC for UART5 interface */
+		clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
+		/* Enable UART5 interface clock */
+		setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
+		break;
+	case CLK_UART3:
+		if (priv->soc == S900)
+			return -EINVAL;
+		/* Source HOSC for UART3 interface */
+		clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL);
+		/* Enable UART3 interface clock */
+		setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int owl_clk_disable(struct clk *clk)
+{
+	struct owl_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case CLK_UART5:
+		if (priv->soc == S700)
+			return -EINVAL;
+		/* Disable UART5 interface clock */
+		clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
+		break;
+	case CLK_UART3:
+		if (priv->soc == S900)
+			return -EINVAL;
+		/* Disable UART3 interface clock */
+		clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int owl_clk_probe(struct udevice *dev)
+{
+	struct owl_clk_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	/* setup necessary clocks */
+	owl_clk_init(priv);
+
+	return 0;
+}
+
+static const struct clk_ops owl_clk_ops = {
+	.enable = owl_clk_enable,
+	.disable = owl_clk_disable,
+};
+
+static const struct udevice_id owl_clk_ids[] = {
+#if defined(CONFIG_MACH_S900)
+	{ .compatible = "actions,s900-cmu", .data = S900 },
+#elif defined(CONFIG_MACH_S700)
+	{ .compatible = "actions,s700-cmu", .data = S700 },
+#endif
+	{ }
+};
+
+U_BOOT_DRIVER(clk_owl) = {
+	.name		= "clk_owl",
+	.id		= UCLASS_CLK,
+	.of_match	= owl_clk_ids,
+	.ops		= &owl_clk_ops,
+	.priv_auto_alloc_size = sizeof(struct owl_clk_priv),
+	.probe		= owl_clk_probe,
+};
diff --git a/drivers/clk/owl/clk_owl.h b/drivers/clk/owl/clk_owl.h
new file mode 100644
index 0000000..8ebf012
--- /dev/null
+++ b/drivers/clk/owl/clk_owl.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Actions Semi SoCs Clock Definitions
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _OWL_CLK_H_
+#define _OWL_CLK_H_
+
+#include <clk-uclass.h>
+
+enum owl_soc {
+	S700,
+	S900,
+};
+
+struct owl_clk_priv {
+	phys_addr_t base;
+	enum owl_soc soc;
+};
+
+/* BUSCLK register definitions */
+#define CMU_PDBGDIV_8		7
+#define CMU_PDBGDIV_SHIFT	26
+#define CMU_PDBGDIV_DIV		(CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
+#define CMU_PERDIV_8		7
+#define CMU_PERDIV_SHIFT	20
+#define CMU_PERDIV_DIV		(CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
+#define CMU_NOCDIV_2		1
+#define CMU_NOCDIV_SHIFT	19
+#define CMU_NOCDIV_DIV		(CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
+#define CMU_DMMCLK_SRC_APLL	2
+#define CMU_DMMCLK_SRC_SHIFT	10
+#define CMU_DMMCLK_SRC		(CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT)
+#define CMU_APBCLK_DIV		BIT(8)
+#define CMU_NOCCLK_SRC		BIT(7)
+#define CMU_AHBCLK_DIV		BIT(4)
+#define CMU_CORECLK_MASK	3
+#define CMU_CORECLK_CPLL	BIT(1)
+#define CMU_CORECLK_HOSC	BIT(0)
+
+/* COREPLL register definitions */
+#define CMU_COREPLL_EN		BIT(9)
+#define CMU_COREPLL_HOSC_EN	BIT(8)
+#define CMU_COREPLL_OUT		(1104 / 24)
+
+/* DEVPLL register definitions */
+#define CMU_DEVPLL_CLK		BIT(12)
+#define CMU_DEVPLL_EN		BIT(8)
+#define CMU_DEVPLL_OUT		(660 / 6)
+
+/* UARTCLK register definitions */
+#define CMU_UARTCLK_SRC_DEVPLL	BIT(16)
+
+#define PLL_STABILITY_WAIT_US	50
+
+#define CMU_DEVCLKEN1_UART5	BIT(21)
+#define CMU_DEVCLKEN1_UART3	BIT(11)
+
+#define CMU_DEVCLKEN1_ETH_S700	BIT(23)
+
+#endif
diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_s900.c
deleted file mode 100644
index d60f199..0000000
--- a/drivers/clk/owl/clk_s900.c
+++ /dev/null
@@ -1,137 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Actions Semi S900 clock driver
- *
- * Copyright (C) 2015 Actions Semi Co., Ltd.
- * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/arch-owl/clk_s900.h>
-#include <asm/arch-owl/regs_s900.h>
-#include <asm/io.h>
-
-#include <dt-bindings/clock/actions,s900-cmu.h>
-
-void owl_clk_init(struct owl_clk_priv *priv)
-{
-	u32 bus_clk = 0, core_pll, dev_pll;
-
-	/* Enable ASSIST_PLL */
-	setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
-
-	udelay(PLL_STABILITY_WAIT_US);
-
-	/* Source HOSC to DEV_CLK */
-	clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
-
-	/* Configure BUS_CLK */
-	bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |
-			CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
-			CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
-	writel(bus_clk, priv->base + CMU_BUSCLK);
-
-	udelay(PLL_STABILITY_WAIT_US);
-
-	/* Configure CORE_PLL */
-	core_pll = readl(priv->base + CMU_COREPLL);
-	core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
-	writel(core_pll, priv->base + CMU_COREPLL);
-
-	udelay(PLL_STABILITY_WAIT_US);
-
-	/* Configure DEV_PLL */
-	dev_pll = readl(priv->base + CMU_DEVPLL);
-	dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
-	writel(dev_pll, priv->base + CMU_DEVPLL);
-
-	udelay(PLL_STABILITY_WAIT_US);
-
-	/* Source CORE_PLL for CORE_CLK */
-	clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
-			CMU_CORECLK_CPLL);
-
-	/* Source DEV_PLL for DEV_CLK */
-	setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
-
-	udelay(PLL_STABILITY_WAIT_US);
-}
-
-void owl_uart_clk_enable(struct owl_clk_priv *priv)
-{
-	/* Source HOSC for UART5 interface */
-	clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
-
-	/* Enable UART5 interface clock */
-	setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
-}
-
-void owl_uart_clk_disable(struct owl_clk_priv *priv)
-{
-	/* Disable UART5 interface clock */
-	clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
-}
-
-int owl_clk_enable(struct clk *clk)
-{
-	struct owl_clk_priv *priv = dev_get_priv(clk->dev);
-
-	switch (clk->id) {
-	case CLK_UART5:
-		owl_uart_clk_enable(priv);
-		break;
-	default:
-		return 0;
-	}
-
-	return 0;
-}
-
-int owl_clk_disable(struct clk *clk)
-{
-	struct owl_clk_priv *priv = dev_get_priv(clk->dev);
-
-	switch (clk->id) {
-	case CLK_UART5:
-		owl_uart_clk_disable(priv);
-		break;
-	default:
-		return 0;
-	}
-
-	return 0;
-}
-
-static int owl_clk_probe(struct udevice *dev)
-{
-	struct owl_clk_priv *priv = dev_get_priv(dev);
-
-	priv->base = dev_read_addr(dev);
-	if (priv->base == FDT_ADDR_T_NONE)
-		return -EINVAL;
-
-	/* setup necessary clocks */
-	owl_clk_init(priv);
-
-	return 0;
-}
-
-static struct clk_ops owl_clk_ops = {
-	.enable = owl_clk_enable,
-	.disable = owl_clk_disable,
-};
-
-static const struct udevice_id owl_clk_ids[] = {
-	{ .compatible = "actions,s900-cmu" },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_owl) = {
-	.name		= "clk_s900",
-	.id		= UCLASS_CLK,
-	.of_match	= owl_clk_ids,
-	.ops		= &owl_clk_ops,
-	.priv_auto_alloc_size = sizeof(struct owl_clk_priv),
-	.probe		= owl_clk_probe,
-};
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH v7 07/12] arm: actions: add S700 SoC device tree
  2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
                   ` (5 preceding siblings ...)
  2020-03-20 17:35 ` [PATCH v7 06/12] clk: actions: Add common clock driver Amit Singh Tomar
@ 2020-03-20 17:35 ` Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 08/12] arm: dts: actions: s700: add u-boot specific dtsi file Amit Singh Tomar
                   ` (4 subsequent siblings)
  11 siblings, 0 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

This patch adds .dtsi file(sync with Linux 5.5-rc6 with hash "b3a987b0264d")
and required binding for S700 SoC that is a 64-bit Quad-core ARM
Cortex-A53 cores.

It also provisions dts file to be built based on selected
platform(CONFIG_MACH_S900/S700).

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v6:
	* No changes.
Changes since v5:
        * Added reviwed-by tag.
Changes since v4:
        * Move it to 07/11 from 05/11.
Changes since v3:
        * Updated commit message to the Linux tag to
          which the dtsi file is synced.
Changes since v2:
        * Synced DTS bindings with Linux 5.5.
Changes since v1:
        * Moved the u-boot specific changes to s700-u-boot.dtsi, now
          s700.dtsi is in complete sync with Linux 4.20.
---
 arch/arm/dts/Makefile                          |   6 +-
 arch/arm/dts/s700.dtsi                         | 248 +++++++++++++++++++++++++
 include/dt-bindings/clock/actions,s700-cmu.h   | 118 ++++++++++++
 include/dt-bindings/reset/actions,s700-reset.h |  34 ++++
 4 files changed, 404 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/s700.dtsi
 create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h
 create mode 100644 include/dt-bindings/reset/actions,s700-reset.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9c593b2..308c76b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -64,8 +64,10 @@ dtb-$(CONFIG_KIRKWOOD) += \
 	kirkwood-pogo_e02.dtb \
 	kirkwood-sheevaplug.dtb
 
-dtb-$(CONFIG_ARCH_OWL) += \
-	bubblegum_96.dtb
+dtb-$(CONFIG_MACH_S900) += \
+        bubblegum_96.dtb
+dtb-$(CONFIG_MACH_S700) += \
+        s700-cubieboard7.dtb
 
 dtb-$(CONFIG_ROCKCHIP_PX30) += \
 	px30-evb.dtb \
diff --git a/arch/arm/dts/s700.dtsi b/arch/arm/dts/s700.dtsi
new file mode 100644
index 0000000..2006ad5
--- /dev/null
+++ b/arch/arm/dts/s700.dtsi
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Andreas F?rber
+ */
+
+#include <dt-bindings/clock/actions,s700-cmu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/actions,s700-reset.h>
+
+/ {
+	compatible = "actions,s700";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secmon at 1f000000 {
+			reg = <0x0 0x1f000000 0x0 0x1000000>;
+			no-map;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	hosc: hosc {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		#clock-cells = <0>;
+	};
+
+	losc: losc {
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		#clock-cells = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gic: interrupt-controller at e00f1000 {
+			compatible = "arm,gic-400";
+			reg = <0x0 0xe00f1000 0x0 0x1000>,
+			      <0x0 0xe00f2000 0x0 0x2000>,
+			      <0x0 0xe00f4000 0x0 0x2000>,
+			      <0x0 0xe00f6000 0x0 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		uart0: serial at e0120000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0120000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART0>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart1: serial at e0122000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0122000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART1>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart2: serial at e0124000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0124000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART2>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart3: serial at e0126000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0126000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART3>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart4: serial at e0128000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0128000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART4>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart5: serial at e012a000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe012a000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART5>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart6: serial at e012c000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe012c000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART6>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		cmu: clock-controller at e0168000 {
+			compatible = "actions,s700-cmu";
+			reg = <0x0 0xe0168000 0x0 0x1000>;
+			clocks = <&hosc>, <&losc>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		i2c0: i2c at e0170000 {
+			compatible = "actions,s700-i2c";
+			reg = <0 0xe0170000 0 0x1000>;
+			clocks = <&cmu CLK_I2C0>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at e0174000 {
+			compatible = "actions,s700-i2c";
+			reg = <0 0xe0174000 0 0x1000>;
+			clocks = <&cmu CLK_I2C1>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at e0178000 {
+			compatible = "actions,s700-i2c";
+			reg = <0 0xe0178000 0 0x1000>;
+			clocks = <&cmu CLK_I2C2>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c at e017c000 {
+			compatible = "actions,s700-i2c";
+			reg = <0 0xe017c000 0 0x1000>;
+			clocks = <&cmu CLK_I2C3>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		sps: power-controller at e01b0100 {
+			compatible = "actions,s700-sps";
+			reg = <0x0 0xe01b0100 0x0 0x100>;
+			#power-domain-cells = <1>;
+		};
+
+		timer: timer at e024c000 {
+			compatible = "actions,s700-timer";
+			reg = <0x0 0xe024c000 0x0 0x4000>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "timer1";
+		};
+
+		pinctrl: pinctrl at e01b0000 {
+			compatible = "actions,s700-pinctrl";
+			reg = <0x0 0xe01b0000 0x0 0x1000>;
+			clocks = <&cmu CLK_GPIO>;
+			gpio-controller;
+			gpio-ranges = <&pinctrl 0 0 136>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+};
diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h
new file mode 100644
index 0000000..3e19429
--- /dev/null
+++ b/include/dt-bindings/clock/actions,s700-cmu.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Device Tree binding constants for Actions Semi S700 Clock Management Unit
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <liuwei@actions-semi.com>
+ *
+ * Author: Pathiban Nallathambi <pn@denx.de>
+ * Author: Saravanan Sekar <sravanhome@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S700_H
+#define __DT_BINDINGS_CLOCK_S700_H
+
+#define CLK_NONE			0
+
+/* pll clocks */
+#define CLK_CORE_PLL			1
+#define CLK_DEV_PLL			2
+#define CLK_DDR_PLL			3
+#define CLK_NAND_PLL			4
+#define CLK_DISPLAY_PLL			5
+#define CLK_TVOUT_PLL			6
+#define CLK_CVBS_PLL			7
+#define CLK_AUDIO_PLL			8
+#define CLK_ETHERNET_PLL		9
+
+/* system clock */
+#define CLK_CPU				10
+#define CLK_DEV				11
+#define CLK_AHB				12
+#define CLK_APB				13
+#define CLK_DMAC			14
+#define CLK_NOC0_CLK_MUX		15
+#define CLK_NOC1_CLK_MUX		16
+#define CLK_HP_CLK_MUX			17
+#define CLK_HP_CLK_DIV			18
+#define CLK_NOC1_CLK_DIV		19
+#define CLK_NOC0			20
+#define CLK_NOC1			21
+#define CLK_SENOR_SRC			22
+
+/* peripheral device clock */
+#define CLK_GPIO			23
+#define CLK_TIMER			24
+#define CLK_DSI				25
+#define CLK_CSI				26
+#define CLK_SI				27
+#define CLK_DE				28
+#define CLK_HDE				29
+#define CLK_VDE				30
+#define CLK_VCE				31
+#define CLK_NAND			32
+#define CLK_SD0				33
+#define CLK_SD1				34
+#define CLK_SD2				35
+
+#define CLK_UART0			36
+#define CLK_UART1			37
+#define CLK_UART2			38
+#define CLK_UART3			39
+#define CLK_UART4			40
+#define CLK_UART5			41
+#define CLK_UART6			42
+
+#define CLK_PWM0			43
+#define CLK_PWM1			44
+#define CLK_PWM2			45
+#define CLK_PWM3			46
+#define CLK_PWM4			47
+#define CLK_PWM5			48
+#define CLK_GPU3D			49
+
+#define CLK_I2C0			50
+#define CLK_I2C1			51
+#define CLK_I2C2			52
+#define CLK_I2C3			53
+
+#define CLK_SPI0			54
+#define CLK_SPI1			55
+#define CLK_SPI2			56
+#define CLK_SPI3			57
+
+#define CLK_USB3_480MPLL0		58
+#define CLK_USB3_480MPHY0		59
+#define CLK_USB3_5GPHY			60
+#define CLK_USB3_CCE			61
+#define CLK_USB3_MAC			62
+
+#define CLK_LCD				63
+#define CLK_HDMI_AUDIO			64
+#define CLK_I2SRX			65
+#define CLK_I2STX			66
+
+#define CLK_SENSOR0			67
+#define CLK_SENSOR1			68
+
+#define CLK_HDMI_DEV			69
+
+#define CLK_ETHERNET			70
+#define CLK_RMII_REF			71
+
+#define CLK_USB2H0_PLLEN		72
+#define CLK_USB2H0_PHY			73
+#define CLK_USB2H0_CCE			74
+#define CLK_USB2H1_PLLEN		75
+#define CLK_USB2H1_PHY			76
+#define CLK_USB2H1_CCE			77
+
+#define CLK_TVOUT			78
+
+#define CLK_THERMAL_SENSOR		79
+
+#define CLK_IRC_SWITCH			80
+#define CLK_PCM1			81
+#define CLK_NR_CLKS			(CLK_PCM1 + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S700_H */
diff --git a/include/dt-bindings/reset/actions,s700-reset.h b/include/dt-bindings/reset/actions,s700-reset.h
new file mode 100644
index 0000000..5e3b16b
--- /dev/null
+++ b/include/dt-bindings/reset/actions,s700-reset.h
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+//
+// Device Tree binding constants for Actions Semi S700 Reset Management Unit
+//
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_ACTIONS_S700_RESET_H
+#define __DT_BINDINGS_ACTIONS_S700_RESET_H
+
+#define RESET_AUDIO				0
+#define RESET_CSI				1
+#define RESET_DE				2
+#define RESET_DSI				3
+#define RESET_GPIO				4
+#define RESET_I2C0				5
+#define RESET_I2C1				6
+#define RESET_I2C2				7
+#define RESET_I2C3				8
+#define RESET_KEY				9
+#define RESET_LCD0				10
+#define RESET_SI				11
+#define RESET_SPI0				12
+#define RESET_SPI1				13
+#define RESET_SPI2				14
+#define RESET_SPI3				15
+#define RESET_UART0				16
+#define RESET_UART1				17
+#define RESET_UART2				18
+#define RESET_UART3				19
+#define RESET_UART4				20
+#define RESET_UART5				21
+#define RESET_UART6				22
+
+#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH v7 08/12] arm: dts: actions: s700: add u-boot specific dtsi file
  2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
                   ` (6 preceding siblings ...)
  2020-03-20 17:35 ` [PATCH v7 07/12] arm: actions: add S700 SoC device tree Amit Singh Tomar
@ 2020-03-20 17:35 ` Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 09/12] arm: add support Actions Semi S700 Amit Singh Tomar
                   ` (3 subsequent siblings)
  11 siblings, 0 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

Devices like uart and clk are needed to be enabled before relocation.
this patch adds u-boot.dtsi file that mark these device as dm-pre-reloc.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v6:
	* No changes.
Changes since v5:
        * Added reviwed-by tag.
Changes since v4:
        * Moved it to 08/11 to 06/11.
Changes since v3:
        * Replaced dtsi with dts in subject line along with arm:dts:
          to the prefix.
Changes since v2:
        * Added License.
Changes since v1:
        * This is newly added file that was *not* present in v1 and
          contains u-boot specific changes.
---
 arch/arm/dts/s700-u-boot.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 arch/arm/dts/s700-u-boot.dtsi

diff --git a/arch/arm/dts/s700-u-boot.dtsi b/arch/arm/dts/s700-u-boot.dtsi
new file mode 100644
index 0000000..a527ccc
--- /dev/null
+++ b/arch/arm/dts/s700-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Amit Singh Tomar <amittomer25@gmail.com>
+ */
+
+/{
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&uart3 {
+	u-boot,dm-pre-reloc;
+};
+
+&cmu {
+	u-boot,dm-pre-reloc;
+};
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH v7 09/12] arm: add support Actions Semi S700
  2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
                   ` (7 preceding siblings ...)
  2020-03-20 17:35 ` [PATCH v7 08/12] arm: dts: actions: s700: add u-boot specific dtsi file Amit Singh Tomar
@ 2020-03-20 17:35 ` Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 10/12] actions: Move defconfig options to Kconfig Amit Singh Tomar
                   ` (2 subsequent siblings)
  11 siblings, 0 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

This patch adds basic support for Actions Semi based S700
SoC, which is driven by common owl framework.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v6:
	* No changes.
Changes since v5:
        * Added reviewed-by tag.
Changes since v4:
        * Moved it to 09/11 to 04/11.
Changes since v3:
        * Added "SoC" keyword to Actions Semi S700.
Changes since v2:
        * Fixed the commit message.
        * Checked for the clk->id.
        * Added a .data member with SoC type.
        * Removed #ifdefs from few places.
Changes since v1:
        * Moved CLK and CLK_OWL symbols from defconfig to arch/arm/Kconfig.
---
 arch/arm/mach-owl/Kconfig |  6 ++++++
 include/configs/s700.h    | 13 +++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 include/configs/s700.h

diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig
index d0be2b5..1d59d8f 100644
--- a/arch/arm/mach-owl/Kconfig
+++ b/arch/arm/mach-owl/Kconfig
@@ -8,6 +8,10 @@ config MACH_S900
         bool "Actions Semi S900 SoC"
         select ARM64
 
+config MACH_S700
+        bool "Actions Semi S700 SoC"
+        select ARM64
+
 endchoice
 
 config SYS_TEXT_BASE
@@ -15,8 +19,10 @@ config SYS_TEXT_BASE
 
 config SYS_CONFIG_NAME
         default "s900" if MACH_S900
+        default "s700" if MACH_S700
 
 config SYS_SOC
         default "s900" if MACH_S900
+        default "s700" if MACH_S700
 
 endif
diff --git a/include/configs/s700.h b/include/configs/s700.h
new file mode 100644
index 0000000..fab0d04
--- /dev/null
+++ b/include/configs/s700.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ */
+
+#ifndef _CONFIG_S700_H_
+#define _CONFIG_S700_H_
+
+/*
+ * Include common owl configuration where most the settings are
+ */
+#include <configs/owl-common.h>
+
+#endif
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH v7 10/12] actions: Move defconfig options to Kconfig
  2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
                   ` (8 preceding siblings ...)
  2020-03-20 17:35 ` [PATCH v7 09/12] arm: add support Actions Semi S700 Amit Singh Tomar
@ 2020-03-20 17:35 ` Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 11/12] arm: add Cubieboard7 board support Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 12/12] doc: boards: add Cubieboard7 documentation Amit Singh Tomar
  11 siblings, 0 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

This patch moves some of the config options from bubblegum_96_defconfig
to platform specific Kconfig file.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v6:
	* remove unnecessary string from SYS_PROMPT. 
Changes since v5:
        * Newly added patch, was not there in earlier versions.
---
 arch/arm/mach-owl/Kconfig      | 15 +++++++++++++++
 configs/bubblegum_96_defconfig |  5 -----
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig
index 1d59d8f..8344081 100644
--- a/arch/arm/mach-owl/Kconfig
+++ b/arch/arm/mach-owl/Kconfig
@@ -25,4 +25,19 @@ config SYS_SOC
         default "s900" if MACH_S900
         default "s700" if MACH_S700
 
+config DISTRO_DEFAULTS
+	default y
+
+config NR_DRAM_BANKS
+	default 1
+
+config SYS_RELOC_GD_ENV_ADDR
+	default y
+
+config SYS_PROMPT
+	default "U-Boot => "
+
+config DISPLAY_BOARDINFO
+	default n
+
 endif
diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig
index e76e9a2..0883167 100644
--- a/configs/bubblegum_96_defconfig
+++ b/configs/bubblegum_96_defconfig
@@ -1,19 +1,14 @@
 CONFIG_ARM=y
 CONFIG_ARCH_OWL=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_MACH_S900=y
 CONFIG_IDENT_STRING="\nBubblegum-96"
-CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=5
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyOWL5,115200n8"
 # CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="U-Boot => "
 CONFIG_CMD_MD5SUM=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
 CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH v7 11/12] arm: add Cubieboard7 board support
  2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
                   ` (9 preceding siblings ...)
  2020-03-20 17:35 ` [PATCH v7 10/12] actions: Move defconfig options to Kconfig Amit Singh Tomar
@ 2020-03-20 17:35 ` Amit Singh Tomar
  2020-03-20 17:35 ` [PATCH v7 12/12] doc: boards: add Cubieboard7 documentation Amit Singh Tomar
  11 siblings, 0 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

The Cubieboard is a single board computer containing a
Actions S700 SoC(with 4 ARMv8 Cortex-A53 cores).

This patch adds respective defconfig alongwith .dts(copied
from Linux v5.5-rc6 with hash "b3a987b0264d").

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v6:
	* Added Reviewed-by tag.
Changes since v5:
        * Trimmed of the cubieboard7_defconfig.
Changes since v4:
        * No changes.
Changes since v3:
        * added reviewed-by: tag.
Changes since v2:
        * No changes.
Changes since v1:
        * No changes.
---
 arch/arm/dts/s700-cubieboard7.dts | 92 +++++++++++++++++++++++++++++++++++++++
 configs/cubieboard7_defconfig     |  9 ++++
 2 files changed, 101 insertions(+)
 create mode 100644 arch/arm/dts/s700-cubieboard7.dts
 create mode 100644 configs/cubieboard7_defconfig

diff --git a/arch/arm/dts/s700-cubieboard7.dts b/arch/arm/dts/s700-cubieboard7.dts
new file mode 100644
index 0000000..63e375c
--- /dev/null
+++ b/arch/arm/dts/s700-cubieboard7.dts
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Andreas F?rber
+ */
+
+/dts-v1/;
+
+#include "s700.dtsi"
+
+/ {
+	compatible = "cubietech,cubieboard7", "actions,s700";
+	model = "CubieBoard7";
+
+	aliases {
+		serial3 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial3:115200n8";
+	};
+
+	memory at 0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	memory at 1,e0000000 {
+		device_type = "memory";
+		reg = <0x1 0xe0000000 0x0 0x0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_default>;
+};
+
+&i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_default>;
+};
+
+&i2c2 {
+	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_default>;
+};
+
+&pinctrl {
+	i2c0_default: i2c0_default {
+		pinmux {
+			groups = "i2c0_mfp";
+			function = "i2c0";
+		};
+		pinconf {
+			pins = "i2c0_sclk", "i2c0_sdata";
+			bias-pull-up;
+		};
+	};
+
+	i2c1_default: i2c1_default {
+		pinmux {
+			groups = "i2c1_dummy";
+			function = "i2c1";
+		};
+		pinconf {
+			pins = "i2c1_sclk", "i2c1_sdata";
+			bias-pull-up;
+		};
+	};
+
+	i2c2_default: i2c2_default {
+		pinmux {
+			groups = "i2c2_dummy";
+			function = "i2c2";
+		};
+		pinconf {
+			pins = "i2c2_sclk", "i2c2_sdata";
+			bias-pull-up;
+		};
+	};
+};
+
+&timer {
+	clocks = <&hosc>;
+};
+
+&uart3 {
+	status = "okay";
+};
diff --git a/configs/cubieboard7_defconfig b/configs/cubieboard7_defconfig
new file mode 100644
index 0000000..d12c293
--- /dev/null
+++ b/configs/cubieboard7_defconfig
@@ -0,0 +1,9 @@
+CONFIG_ARM=y
+CONFIG_ARCH_OWL=y
+CONFIG_MACH_S700=y
+CONFIG_IDENT_STRING="\ncubieboard7"
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyOWL3,115200n8"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7"
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH v7 12/12] doc: boards: add Cubieboard7 documentation
  2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
                   ` (10 preceding siblings ...)
  2020-03-20 17:35 ` [PATCH v7 11/12] arm: add Cubieboard7 board support Amit Singh Tomar
@ 2020-03-20 17:35 ` Amit Singh Tomar
  11 siblings, 0 replies; 13+ messages in thread
From: Amit Singh Tomar @ 2020-03-20 17:35 UTC (permalink / raw)
  To: u-boot

This adds build and flash steps for Actions S700
based Cubieboard7 board.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v6:
	* No changes.
Changes since v5:
        * No changes.
Changes since v4:
        * No changes.
Changes since v3:
        * Convert plain text documentation to reStructuredText format.
Changes since v2:
        * No Change.
Changes since v1:
        * No Change.
---
 doc/board/actions/cubieboard7.rst | 115 ++++++++++++++++++++++++++++++++++++++
 doc/board/actions/index.rst       |  10 ++++
 doc/board/index.rst               |   1 +
 3 files changed, 126 insertions(+)
 create mode 100644 doc/board/actions/cubieboard7.rst
 create mode 100644 doc/board/actions/index.rst

diff --git a/doc/board/actions/cubieboard7.rst b/doc/board/actions/cubieboard7.rst
new file mode 100644
index 0000000..ce39e6b
--- /dev/null
+++ b/doc/board/actions/cubieboard7.rst
@@ -0,0 +1,115 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2020 Amit Singh Tomar <amittomer25@gmail.com>
+
+ACTIONS
+========
+
+About this
+----------
+
+This document describes build and flash steps for Actions S700 SoC based Cubieboard7
+board.
+
+Cubieboard7 initial configuration
+---------------------------------
+
+Default Cubieboard7 comes with pre-installed Android where U-Boot is configured with
+a bootdelay of 0, entering a prompt by pressing keys does not seem to work.
+
+Though, one can enter ADFU mode and flash debian image(from host machine) where
+getting into u-boot prompt is easy.
+
+Enter ADFU Mode
+----------------
+
+Before write the firmware, let the development board entering the ADFU mode: insert
+one end of the USB cable to the PC, press and hold the ADFU button, and then connect
+the other end of the USB cable to the Mini USB port of the development board, release
+the ADFU button, after connecting it will enter the ADFU mode.
+
+Check whether entered ADFU Mode
+--------------------------------
+
+The user needs to run the following command on the PC side to check if the ADFU
+device is detected. ID realted to "Actions Semiconductor Co., Ltd"  means that
+the PC side has been correctly detected ADFU device, the development board
+also enter into the ADFU mode.
+
+.. code-block:: none
+
+   $ lsusb
+   Bus 001 Device 005: ID 04f2:b2eb Chicony Electronics Co., Ltd
+   Bus 001 Device 004: ID 0a5c:21e6 Broadcom Corp. BCM20702 Bluetooth 4.0 [ThinkPad]
+   Bus 001 Device 003: ID 046d:c534 Logitech, Inc. Unifying Receiver
+   Bus 001 Device 002: ID 8087:0024 Intel Corp. Integrated Rate Matching Hub
+   Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
+   Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
+   Bus 003 Device 013: ID 10d6:10d6 Actions Semiconductor Co., Ltd
+   Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
+
+Flashing debian image
+---------------------
+
+.. code-block:: none
+
+   $ sudo ./ActionsFWU.py --fw=debian-stretch-desktop-cb7-emmc-v2.0.fw
+   ActionsFWU.py	: 1.0.150828.0830
+   libScript.so    : 2.3.150825.0951
+   libFileSystem.so: 2.3.150825.0952
+   libProduction.so: 2.3.150915.1527
+   =====burn all partition====
+   FW_VER: 3.10.37.180608
+   3% DOWNLOAD ADFUDEC ...
+   5% DOWNLOAD BOOT PARA ...
+   7% SWITCH ADFUDEC ...
+   12% DOWNLOAD BL31 ...
+   13% DOWNLOAD BL32 ...
+   15% DOWNLOAD VMLINUX ...
+   20% DOWNLOAD INITRD ...
+   24% DOWNLOAD FDT ...
+   27% DOWNLOAD ADFUS ...
+   30% SWITCH ADFUS ...
+   32% DOWNLOAD MBR ...
+   35% DOWNLOAD PARTITIONS ...
+   WRITE_MBRC_PARTITION
+   35% write p0 size = 2048 : ok
+   WRITE_BOOT_PARTITION
+   35% write p1 size = 2048 : ok
+   WRITE_MISC_PARTITION
+   36% write p2 size = 98304 : ok
+   WRITE_SYSTEM_PARTITION
+   94% write p3 size = 4608000 : ok
+   FORMAT_SWAP_PARTITION
+   94% write p4 size = 20480 : ok
+   95% TRANSFER OVER ...
+   Firmware upgrade successfully!
+
+Debian image can be downloaded from here[1].
+
+Once debian image is flashed, one can get into u-boot prompt by pressing any key and from
+there run ums command(make sure, usb cable is connected between host and target):
+
+.. code-block:: none
+
+   owl> ums 0 mmc 1
+
+Above command would mount debian image partition on host machine.
+
+Building U-BOOT proper image
+----------------------------
+
+.. code-block:: none
+
+   $ make clean
+   $ export CROSS_COMPILE=aarch64-linux-gnu-
+   $ make ARCH=arm cubieboard7_defconfig
+   $ make -j16
+   $ mkimage -A arm -T firmware -C none -O u-boot -a 0x11000000 -e 0x11000000 -d u-boot-dtb.bin u-boot-dtb.img  >/dev/null
+
+u-boot-dtb.img can now be flashed to debian image partition mounted on host machine.
+
+.. code-block:: none
+
+   $ sudo dd if=u-boot-dtb.img of=/dev/sdb bs=1024 seek=3072
+
+[1]: https://pan.baidu.com/s/1uawPr0Jao2HgWFLZCLzHAg#list/path=%2FCubieBoard_Download%2FBoard%2FCubieBoard7%2F%E6%96%B9%E7%B3%96%E6%96%B9%E6%A1%88%E5%BC%80%E5%8F%91%E8%B5%84%E6%96%99%2FImage%2FDebian%2FV2.1-test&parentPath=%2F
diff --git a/doc/board/actions/index.rst b/doc/board/actions/index.rst
new file mode 100644
index 0000000..c596879
--- /dev/null
+++ b/doc/board/actions/index.rst
@@ -0,0 +1,10 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2020 Amit Singh Tomar <amittomer25@gmail.com>
+
+Actions
+========
+
+.. toctree::
+   :maxdepth: 2
+
+   cubieboard7
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 51a2ae6..01b233f 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -6,6 +6,7 @@ Board-specific doc
 .. toctree::
    :maxdepth: 2
 
+   actions/index
    AndesTech/index
    atmel/index
    coreboot/index
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 13+ messages in thread
end of thread, other threads:[~2020-03-20 17:35 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-20 17:35 [PATCH v7 00/12] Actions S700 SoC support Amit Singh Tomar
2020-03-20 17:35 ` [PATCH v7 01/12] arm: actions: Add common framework for Actions Owl Semi SoCs Amit Singh Tomar
2020-03-20 17:35 ` [PATCH v7 02/12] arm: actions: rename sysmap-s900 to sysmap-owl Amit Singh Tomar
2020-03-20 17:35 ` [PATCH v7 03/12] serial: actions: add compatible string Amit Singh Tomar
2020-03-20 17:35 ` [PATCH v7 04/12] arm: dts: sync dts for Action Semi S900 Amit Singh Tomar
2020-03-20 17:35 ` [PATCH v7 05/12] arm: dts: actions: s900: add u-boot specific dtsi file Amit Singh Tomar
2020-03-20 17:35 ` [PATCH v7 06/12] clk: actions: Add common clock driver Amit Singh Tomar
2020-03-20 17:35 ` [PATCH v7 07/12] arm: actions: add S700 SoC device tree Amit Singh Tomar
2020-03-20 17:35 ` [PATCH v7 08/12] arm: dts: actions: s700: add u-boot specific dtsi file Amit Singh Tomar
2020-03-20 17:35 ` [PATCH v7 09/12] arm: add support Actions Semi S700 Amit Singh Tomar
2020-03-20 17:35 ` [PATCH v7 10/12] actions: Move defconfig options to Kconfig Amit Singh Tomar
2020-03-20 17:35 ` [PATCH v7 11/12] arm: add Cubieboard7 board support Amit Singh Tomar
2020-03-20 17:35 ` [PATCH v7 12/12] doc: boards: add Cubieboard7 documentation Amit Singh Tomar

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