From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Subject: [Bug 1863247] Re: AArch64 EXT instruction for V register does not clear MSB side bits
Date: Wed, 25 Mar 2020 14:55:02 -0000 [thread overview]
Message-ID: <158514810304.16634.7342804291295003813.malone@gac.canonical.com> (raw)
In-Reply-To: 158168561076.14835.7019812774701035317.malonedeb@soybean.canonical.com
All of those, and tbl, tbx, ins, are fixed in the three subsequent
commits.
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https://bugs.launchpad.net/bugs/1863247
Title:
AArch64 EXT instruction for V register does not clear MSB side bits
Status in QEMU:
Fix Committed
Bug description:
On AArch64 CPU with SVE register, there seems to be a bug in the
operation when executing EXT instruction to V registers. Bits above
the 128 bits of the SVE register must be cleared to 0, but qemu-
aarch64 seems to hold the value.
Example
ext v0.16b, v1.16b v2.16b, 8
After executing above instruction, (N-1) to 128 bits of z0 register
must be 0, where N is SVE register width.
To manage notifications about this bug go to:
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next prev parent reply other threads:[~2020-03-25 15:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 13:06 [Bug 1863247] [NEW] AArch64 EXT instruction for V register does not clear MSB side bits Kentaro Kawakami
2020-02-14 17:51 ` [Bug 1863247] " Richard Henderson
2020-03-10 9:04 ` Laurent Vivier
2020-03-25 14:29 ` Kentaro Kawakami
2020-03-25 14:55 ` Richard Henderson [this message]
2020-04-30 13:29 ` Laurent Vivier
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